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[/] [fp_log/] [trunk/] [LAU/] [Virtex 4/] [SP-LAU/] [sp_fp_log_v2.vhd] - Blame information for rev 2

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1 2 NikosAl 
----------------------------------------------------------------------------------
2 
-- Company: TUM - Technischen Universität München
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-- Engineer: N.Alachiotis
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--
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-- Create Date:    11:03:31 06/24/2009
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-- Design Name:         SP-LAU (Single Precision Logarithm Approximation Unit)
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-- Module Name:    sp_fp_log_v2 - Behavioral
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-- Project Name:
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-- Target Devices: Virtex 5 SX
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-- Tool versions: Xilinx ISE 10.1
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
20 
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 
 
25 
---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
28 
--use UNISIM.VComponents.all;
29 
 
30 
entity sp_fp_log_v2 is
31 
    Port ( rst : in  STD_LOGIC;
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           clk : in  STD_LOGIC;
33 
           valid_in : in  STD_LOGIC;
34 
           input_val : in  STD_LOGIC_VECTOR (31 downto 0);
35 
           valid_out : out  STD_LOGIC;
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           output_val : out  STD_LOGIC_VECTOR (31 downto 0));
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end sp_fp_log_v2;
38 
 
39 
architecture Behavioral of sp_fp_log_v2 is
40 
 
41 
component reg_64b_1c is
42 
  port (
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    sclr : in STD_LOGIC := 'X';
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    clk : in STD_LOGIC := 'X';
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    d : in STD_LOGIC_VECTOR ( 63 downto 0 );
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    q : out STD_LOGIC_VECTOR ( 63 downto 0 )
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  );
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end component;
49 
 
50 
component reg_1b_1c is
51 
  port (
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    sclr : in STD_LOGIC := 'X';
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    clk : in STD_LOGIC := 'X';
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    d : in STD_LOGIC_VECTOR ( 0 downto 0 );
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    q : out STD_LOGIC_VECTOR ( 0 downto 0 )
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  );
57 
end component;
58 
 
59 
signal valid_output_1bvec_in, valid_output_1bvec_out : std_logic_vector(0 downto 0);
60 
signal tmp_valid_out : std_logic;
61 
component reg_1b_2c is
62 
  port (
63 
    sclr : in STD_LOGIC := 'X';
64 
    clk : in STD_LOGIC := 'X';
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    d : in STD_LOGIC_VECTOR ( 0 downto 0 );
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    q : out STD_LOGIC_VECTOR ( 0 downto 0 )
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  );
68 
end component;
69 
 
70 
component reg_32b_8c is
71 
  port (
72 
    sclr : in STD_LOGIC := 'X';
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    clk : in STD_LOGIC := 'X';
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    d : in STD_LOGIC_VECTOR ( 31 downto 0 );
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    q : out STD_LOGIC_VECTOR ( 31 downto 0 )
76 
  );
77 
end component;
78 
 
79 
component reg_32b_1c is
80 
  port (
81 
    sclr : in STD_LOGIC := 'X';
82 
    clk : in STD_LOGIC := 'X';
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    d : in STD_LOGIC_VECTOR ( 31 downto 0 );
84 
    q : out STD_LOGIC_VECTOR ( 31 downto 0 )
85 
  );
86 
end component;
87 
 
88 
signal input_val_valid_reg : std_logic_Vector (31 downto 0);
89 
 
90 
constant log_base_e_of_2 : std_logic_vector(31 downto 0):="00111111001100010111001000011000";
91 
 
92 
component special_case_detector is
93 
    Port ( rst : in  STD_LOGIC;
94 
           clk : in  STD_LOGIC;
95 
           input_val : in  STD_LOGIC_VECTOR (31 downto 0);
96 
                          special_val_sel : out STD_LOGIC;
97 
                          output_special_val : out STD_LOGIC_VECTOR(31 downto 0));
98 
end component;
99 
 
100 
signal scd_out_special_val_sel , scd_out_special_val_sel_reg : std_logic;
101 
signal scd_out_special_val_sel_1bvec , scd_out_special_val_sel_reg_1bvec : std_logic_vector(0 downto 0);
102 
signal scd_out_output_special_val , scd_out_output_special_val_reg: std_logic_vector(31 downto 0);
103 
 
104 
signal scd_out_special_val_sel_reg_vec , scd_out_special_val_not_sel_reg_vec,
105 
       temp_final_result ,
106 
                 temp_final_result_reg: std_logic_vector(31 downto 0);
107 
 
108 
 
109 
 
110 
component Construct_sp_fp_mult_factor is
111 
    Port ( rst : in  STD_LOGIC;
112 
           clk : in  STD_LOGIC;
113 
                          input_exponent : in  STD_LOGIC_VECTOR (7 downto 0);
114 
           sp_fp_mult_fact : out  STD_LOGIC_VECTOR (31 downto 0));
115 
end component;
116 
 
117 
signal csfmf_sp_fp_mult_fact : std_logic_vector(31 downto 0);
118 
 
119 
 
120 
component sp_fp_mult is
121 
  port (
122 
    sclr : in STD_LOGIC := 'X';
123 
    rdy : out STD_LOGIC;
124 
    operation_nd : in STD_LOGIC := 'X';
125 
    clk : in STD_LOGIC := 'X';
126 
    a : in STD_LOGIC_VECTOR ( 31 downto 0 );
127 
    b : in STD_LOGIC_VECTOR ( 31 downto 0 );
128 
    result : out STD_LOGIC_VECTOR ( 31 downto 0 )
129 
  );
130 
end component;
131 
 
132 
signal mult_result : std_logic_vector(31 downto 0);
133 
signal mult_valid_out : std_logic;
134 
 
135 
 
136 
signal tmp_valid_in_vec_in1,tmp_valid_in_vec_out1,
137 
                 tmp_valid_in_vec_in2,tmp_valid_in_vec_out2: std_logic_vector(0 downto 0);
138 
 
139 
component Construct_sp_fp_add_offset is
140 
  Port ( rst : in  STD_LOGIC;
141 
         clk : in  STD_LOGIC;
142 
         lut_index : in  STD_LOGIC_VECTOR(12 downto 0);
143 
         sp_fp_add_offset : out  STD_LOGIC_VECTOR (31 downto 0));
144 
end component;
145 
 
146 
signal sp_fp_val_offset_reg_in , sp_fp_val_offset_reg_out: std_logic_vector(31 downto 0);
147 
 
148 
component sp_fp_add is
149 
  port (
150 
    sclr : in STD_LOGIC := 'X';
151 
    rdy : out STD_LOGIC;
152 
    operation_nd : in STD_LOGIC := 'X';
153 
    clk : in STD_LOGIC := 'X';
154 
    a : in STD_LOGIC_VECTOR ( 31 downto 0 );
155 
    b : in STD_LOGIC_VECTOR ( 31 downto 0 );
156 
    result : out STD_LOGIC_VECTOR ( 31 downto 0 )
157 
  );
158 
end component;
159 
 
160 
signal add_result : std_logic_vector(31 downto 0);
161 
signal add_valid_out : std_logic;
162 
 
163 
signal no_special_case_result_32b : std_logic_Vector(31 downto 0);
164 
 
165 
component reg_1b_18c is
166 
  port (
167 
    sclr : in STD_LOGIC := 'X';
168 
    clk : in STD_LOGIC := 'X';
169 
    d : in STD_LOGIC_VECTOR ( 0 downto 0 );
170 
    q : out STD_LOGIC_VECTOR ( 0 downto 0 )
171 
  );
172 
end component;
173 
 
174 
component reg_32b_18c is
175 
  port (
176 
    sclr : in STD_LOGIC := 'X';
177 
    clk : in STD_LOGIC := 'X';
178 
    d : in STD_LOGIC_VECTOR ( 31 downto 0 );
179 
    q : out STD_LOGIC_VECTOR ( 31 downto 0 )
180 
  );
181 
end component;
182 
 
183 
component reg_33b_1c is
184 
  port (
185 
    sclr : in STD_LOGIC := 'X';
186 
    clk : in STD_LOGIC := 'X';
187 
    d : in STD_LOGIC_VECTOR ( 32 downto 0 );
188 
    q : out STD_LOGIC_VECTOR ( 32 downto 0 )
189 
  );
190 
end component;
191 
 
192 
signal tmp_final_output_vec , tmp_final_output_vec_out : std_logic_vector(32 downto 0);
193 
 
194 
signal rst_reg_in , rst_reg_out : std_logic_vector(0 downto 0);
195 
 
196 
begin
197 
 
198 
rst_reg_in(0) <=rst;
199 
Reset_Register : reg_1b_1c port map (rst, clk, rst_reg_in, rst_reg_out);
200 
 
201 
 
202 
Valid_Input_Pipeline_Reg : reg_32b_1c port map (rst, clk, input_val, input_val_valid_reg);
203 
 
204 
tmp_valid_in_vec_in1(0)<=valid_in;
205 
Valid_Input_Pipeline_Reg1 : reg_1b_1c port map (rst, clk, tmp_valid_in_vec_in1, tmp_valid_in_vec_out1);
206 
 
207 
-- Special Case Detector
208 
special_case_detector_port_map: special_case_detector port map (
209 
rst,
210 
clk,
211 
input_val_valid_reg,
212 
scd_out_special_val_sel,
213 
scd_out_output_special_val
214 
);
215 
 
216 
-- Construct_sp_fp_mult_factor
217 
Construct_sp_fp_mult_factor_port_map : Construct_sp_fp_mult_factor port map (
218 
rst,
219 
clk,
220 
input_val_valid_reg(30 downto 23),
221 
csfmf_sp_fp_mult_fact
222 
);
223 
 
224 
-- Multiplier with constant port b : log10(2)
225 
 
226 
Valid_Input_Pipeline_Reg2 : reg_1b_2c port map (rst, clk, tmp_valid_in_vec_out1, tmp_valid_in_vec_out2);
227 
 
228 
 
229 
sp_fp_mult_port_map : sp_fp_mult port map (
230 
rst,
231 
mult_valid_out,
232 
tmp_valid_in_vec_out2(0),
233 
clk,
234 
csfmf_sp_fp_mult_fact,
235 
log_base_e_of_2,
236 
mult_result
237 
);
238 
 
239 
 
240 
-- Construct sp_fp_add_offset
241 
 
242 
Construct_sp_fp_add_offset_port_map: Construct_sp_fp_add_offset port map (
243 
rst,
244 
clk,
245 
input_val_valid_reg(22 downto 10),
246 
sp_fp_val_offset_reg_in
247 
 
248 
);
249 
 
250 
-- Pipeline Register for sp_fp_val_offset
251 
val_offset_pipeline_reg : reg_32b_8c port map(rst,clk,sp_fp_val_offset_reg_in,sp_fp_val_offset_reg_out);
252 
 
253 
-- Final adder
254 
 
255 
sp_fp_add_port_map : sp_fp_add port map (
256 
rst_reg_out(0),
257 
tmp_valid_out,
258 
mult_valid_out,
259 
clk,
260 
mult_result,
261 
sp_fp_val_offset_reg_out,
262 
no_special_case_result_32b
263 
);
264 
 
265 
valid_output_1bvec_in(0) <= tmp_valid_out ;
266 
reg_1b_1c_port_map_for_valid_out : reg_1b_1c port map (rst_reg_out(0), clk, valid_output_1bvec_in , valid_output_1bvec_out );
267 
valid_out<=valid_output_1bvec_out(0);
268 
 
269 
-- Pipeline Register for special case value selection
270 
scd_out_special_val_sel_1bvec(0)<=scd_out_special_val_sel;
271 
reg_1b_21c_port_map : reg_1b_18c port map (rst_reg_out(0), clk, scd_out_special_val_sel_1bvec , scd_out_special_val_sel_reg_1bvec );
272 
reg_32b_21c_port_map: reg_32b_18c port map (rst_reg_out(0),clk,scd_out_output_special_val,scd_out_output_special_val_reg);
273 
 
274 
scd_out_special_val_sel_reg_vec<=(others=>scd_out_special_val_sel_reg_1bvec(0));
275 
scd_out_special_val_not_sel_reg_vec<=(others=>not scd_out_special_val_sel_reg_1bvec(0));
276 
 
277 
 
278 
temp_final_result<= (scd_out_special_val_sel_reg_vec and scd_out_output_special_val_reg) or
279 
                                                  (scd_out_special_val_not_sel_reg_vec and no_special_case_result_32b) ;
280 
 
281 
 
282 
reg_32b_1c_port_map : reg_32b_1c port map (rst_reg_out(0), clk, temp_final_result , temp_final_result_reg );
283 
 
284 
 
285 
output_val<=temp_final_result_reg;
286 
 
287 
 
288 
 
289 
 
290 
end Behavioral;
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