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[/] [fp_log/] [trunk/] [LAU/] [Virtex 5/] [DP-LAU/] [reg_64b_1c.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 NikosAl 
--------------------------------------------------------------------------------
2 
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
3 
--------------------------------------------------------------------------------
4 
--   ____  ____
5 
--  /   /\/   /
6 
-- /___/  \  /    Vendor: Xilinx
7 
-- \   \   \/     Version: K.39
8 
--  \   \         Application: netgen
9 
--  /   /         Filename: reg_64b_1c.vhd
10 
-- /___/   /\     Timestamp: Mon Jun 22 17:47:59 2009
11 
-- \   \  /  \
12 
--  \___\/\___\
13 
--
14 
-- Command      : -intstyle ise -w -sim -ofmt vhdl "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\reg_64b_1c.ngc" "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\reg_64b_1c.vhd"
15 
-- Device       : 5vsx95tff1136-2
16 
-- Input file   : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/reg_64b_1c.ngc
17 
-- Output file  : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/reg_64b_1c.vhd
18 
-- # of Entities        : 1
19 
-- Design Name  : reg_64b_1c
20 
-- Xilinx       : C:\Xilinx\10.1\ISE
21 
--
22 
-- Purpose:
23 
--     This VHDL netlist is a verification model and uses simulation
24 
--     primitives which may not represent the true implementation of the
25 
--     device, however the netlist is functionally correct and should not
26 
--     be modified. This file cannot be synthesized and should only be used
27 
--     with supported simulation tools.
28 
--
29 
-- Reference:
30 
--     Development System Reference Guide, Chapter 23
31 
--     Synthesis and Simulation Design Guide, Chapter 6
32 
--
33 
--------------------------------------------------------------------------------
34 
 
35 
 
36 
-- synthesis translate_off
37 
library IEEE;
38 
use IEEE.STD_LOGIC_1164.ALL;
39 
library UNISIM;
40 
use UNISIM.VCOMPONENTS.ALL;
41 
use UNISIM.VPKG.ALL;
42 
 
43 
entity reg_64b_1c is
44 
  port (
45 
    sclr : in STD_LOGIC := 'X';
46 
    clk : in STD_LOGIC := 'X';
47 
    d : in STD_LOGIC_VECTOR ( 63 downto 0 );
48 
    q : out STD_LOGIC_VECTOR ( 63 downto 0 )
49 
  );
50 
end reg_64b_1c;
51 
 
52 
architecture STRUCTURE of reg_64b_1c is
53 
  signal BU2_sset : STD_LOGIC;
54 
  signal BU2_sinit : STD_LOGIC;
55 
  signal BU2_ainit : STD_LOGIC;
56 
  signal BU2_aclr : STD_LOGIC;
57 
  signal BU2_ce : STD_LOGIC;
58 
  signal BU2_aset : STD_LOGIC;
59 
  signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
60 
  signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
61 
  signal d_2 : STD_LOGIC_VECTOR ( 63 downto 0 );
62 
  signal q_3 : STD_LOGIC_VECTOR ( 63 downto 0 );
63 
  signal BU2_a : STD_LOGIC_VECTOR ( 3 downto 0 );
64 
begin
65 
  d_2(63) <= d(63);
66 
  d_2(62) <= d(62);
67 
  d_2(61) <= d(61);
68 
  d_2(60) <= d(60);
69 
  d_2(59) <= d(59);
70 
  d_2(58) <= d(58);
71 
  d_2(57) <= d(57);
72 
  d_2(56) <= d(56);
73 
  d_2(55) <= d(55);
74 
  d_2(54) <= d(54);
75 
  d_2(53) <= d(53);
76 
  d_2(52) <= d(52);
77 
  d_2(51) <= d(51);
78 
  d_2(50) <= d(50);
79 
  d_2(49) <= d(49);
80 
  d_2(48) <= d(48);
81 
  d_2(47) <= d(47);
82 
  d_2(46) <= d(46);
83 
  d_2(45) <= d(45);
84 
  d_2(44) <= d(44);
85 
  d_2(43) <= d(43);
86 
  d_2(42) <= d(42);
87 
  d_2(41) <= d(41);
88 
  d_2(40) <= d(40);
89 
  d_2(39) <= d(39);
90 
  d_2(38) <= d(38);
91 
  d_2(37) <= d(37);
92 
  d_2(36) <= d(36);
93 
  d_2(35) <= d(35);
94 
  d_2(34) <= d(34);
95 
  d_2(33) <= d(33);
96 
  d_2(32) <= d(32);
97 
  d_2(31) <= d(31);
98 
  d_2(30) <= d(30);
99 
  d_2(29) <= d(29);
100 
  d_2(28) <= d(28);
101 
  d_2(27) <= d(27);
102 
  d_2(26) <= d(26);
103 
  d_2(25) <= d(25);
104 
  d_2(24) <= d(24);
105 
  d_2(23) <= d(23);
106 
  d_2(22) <= d(22);
107 
  d_2(21) <= d(21);
108 
  d_2(20) <= d(20);
109 
  d_2(19) <= d(19);
110 
  d_2(18) <= d(18);
111 
  d_2(17) <= d(17);
112 
  d_2(16) <= d(16);
113 
  d_2(15) <= d(15);
114 
  d_2(14) <= d(14);
115 
  d_2(13) <= d(13);
116 
  d_2(12) <= d(12);
117 
  d_2(11) <= d(11);
118 
  d_2(10) <= d(10);
119 
  d_2(9) <= d(9);
120 
  d_2(8) <= d(8);
121 
  d_2(7) <= d(7);
122 
  d_2(6) <= d(6);
123 
  d_2(5) <= d(5);
124 
  d_2(4) <= d(4);
125 
  d_2(3) <= d(3);
126 
  d_2(2) <= d(2);
127 
  d_2(1) <= d(1);
128 
  d_2(0) <= d(0);
129 
  q(63) <= q_3(63);
130 
  q(62) <= q_3(62);
131 
  q(61) <= q_3(61);
132 
  q(60) <= q_3(60);
133 
  q(59) <= q_3(59);
134 
  q(58) <= q_3(58);
135 
  q(57) <= q_3(57);
136 
  q(56) <= q_3(56);
137 
  q(55) <= q_3(55);
138 
  q(54) <= q_3(54);
139 
  q(53) <= q_3(53);
140 
  q(52) <= q_3(52);
141 
  q(51) <= q_3(51);
142 
  q(50) <= q_3(50);
143 
  q(49) <= q_3(49);
144 
  q(48) <= q_3(48);
145 
  q(47) <= q_3(47);
146 
  q(46) <= q_3(46);
147 
  q(45) <= q_3(45);
148 
  q(44) <= q_3(44);
149 
  q(43) <= q_3(43);
150 
  q(42) <= q_3(42);
151 
  q(41) <= q_3(41);
152 
  q(40) <= q_3(40);
153 
  q(39) <= q_3(39);
154 
  q(38) <= q_3(38);
155 
  q(37) <= q_3(37);
156 
  q(36) <= q_3(36);
157 
  q(35) <= q_3(35);
158 
  q(34) <= q_3(34);
159 
  q(33) <= q_3(33);
160 
  q(32) <= q_3(32);
161 
  q(31) <= q_3(31);
162 
  q(30) <= q_3(30);
163 
  q(29) <= q_3(29);
164 
  q(28) <= q_3(28);
165 
  q(27) <= q_3(27);
166 
  q(26) <= q_3(26);
167 
  q(25) <= q_3(25);
168 
  q(24) <= q_3(24);
169 
  q(23) <= q_3(23);
170 
  q(22) <= q_3(22);
171 
  q(21) <= q_3(21);
172 
  q(20) <= q_3(20);
173 
  q(19) <= q_3(19);
174 
  q(18) <= q_3(18);
175 
  q(17) <= q_3(17);
176 
  q(16) <= q_3(16);
177 
  q(15) <= q_3(15);
178 
  q(14) <= q_3(14);
179 
  q(13) <= q_3(13);
180 
  q(12) <= q_3(12);
181 
  q(11) <= q_3(11);
182 
  q(10) <= q_3(10);
183 
  q(9) <= q_3(9);
184 
  q(8) <= q_3(8);
185 
  q(7) <= q_3(7);
186 
  q(6) <= q_3(6);
187 
  q(5) <= q_3(5);
188 
  q(4) <= q_3(4);
189 
  q(3) <= q_3(3);
190 
  q(2) <= q_3(2);
191 
  q(1) <= q_3(1);
192 
  q(0) <= q_3(0);
193 
  VCC_0 : VCC
194 
    port map (
195 
      P => NLW_VCC_P_UNCONNECTED
196 
    );
197 
  GND_1 : GND
198 
    port map (
199 
      G => NLW_GND_G_UNCONNECTED
200 
    );
201 
  BU2_U0_gen_output_regs_output_regs_fd_output_64 : FDR
202 
    generic map(
203 
      INIT => '0'
204 
    )
205 
    port map (
206 
      C => clk,
207 
      D => d_2(63),
208 
      R => sclr,
209 
      Q => q_3(63)
210 
    );
211 
  BU2_U0_gen_output_regs_output_regs_fd_output_63 : FDR
212 
    generic map(
213 
      INIT => '0'
214 
    )
215 
    port map (
216 
      C => clk,
217 
      D => d_2(62),
218 
      R => sclr,
219 
      Q => q_3(62)
220 
    );
221 
  BU2_U0_gen_output_regs_output_regs_fd_output_62 : FDR
222 
    generic map(
223 
      INIT => '0'
224 
    )
225 
    port map (
226 
      C => clk,
227 
      D => d_2(61),
228 
      R => sclr,
229 
      Q => q_3(61)
230 
    );
231 
  BU2_U0_gen_output_regs_output_regs_fd_output_61 : FDR
232 
    generic map(
233 
      INIT => '0'
234 
    )
235 
    port map (
236 
      C => clk,
237 
      D => d_2(60),
238 
      R => sclr,
239 
      Q => q_3(60)
240 
    );
241 
  BU2_U0_gen_output_regs_output_regs_fd_output_60 : FDR
242 
    generic map(
243 
      INIT => '0'
244 
    )
245 
    port map (
246 
      C => clk,
247 
      D => d_2(59),
248 
      R => sclr,
249 
      Q => q_3(59)
250 
    );
251 
  BU2_U0_gen_output_regs_output_regs_fd_output_59 : FDR
252 
    generic map(
253 
      INIT => '0'
254 
    )
255 
    port map (
256 
      C => clk,
257 
      D => d_2(58),
258 
      R => sclr,
259 
      Q => q_3(58)
260 
    );
261 
  BU2_U0_gen_output_regs_output_regs_fd_output_58 : FDR
262 
    generic map(
263 
      INIT => '0'
264 
    )
265 
    port map (
266 
      C => clk,
267 
      D => d_2(57),
268 
      R => sclr,
269 
      Q => q_3(57)
270 
    );
271 
  BU2_U0_gen_output_regs_output_regs_fd_output_57 : FDR
272 
    generic map(
273 
      INIT => '0'
274 
    )
275 
    port map (
276 
      C => clk,
277 
      D => d_2(56),
278 
      R => sclr,
279 
      Q => q_3(56)
280 
    );
281 
  BU2_U0_gen_output_regs_output_regs_fd_output_56 : FDR
282 
    generic map(
283 
      INIT => '0'
284 
    )
285 
    port map (
286 
      C => clk,
287 
      D => d_2(55),
288 
      R => sclr,
289 
      Q => q_3(55)
290 
    );
291 
  BU2_U0_gen_output_regs_output_regs_fd_output_55 : FDR
292 
    generic map(
293 
      INIT => '0'
294 
    )
295 
    port map (
296 
      C => clk,
297 
      D => d_2(54),
298 
      R => sclr,
299 
      Q => q_3(54)
300 
    );
301 
  BU2_U0_gen_output_regs_output_regs_fd_output_54 : FDR
302 
    generic map(
303 
      INIT => '0'
304 
    )
305 
    port map (
306 
      C => clk,
307 
      D => d_2(53),
308 
      R => sclr,
309 
      Q => q_3(53)
310 
    );
311 
  BU2_U0_gen_output_regs_output_regs_fd_output_53 : FDR
312 
    generic map(
313 
      INIT => '0'
314 
    )
315 
    port map (
316 
      C => clk,
317 
      D => d_2(52),
318 
      R => sclr,
319 
      Q => q_3(52)
320 
    );
321 
  BU2_U0_gen_output_regs_output_regs_fd_output_52 : FDR
322 
    generic map(
323 
      INIT => '0'
324 
    )
325 
    port map (
326 
      C => clk,
327 
      D => d_2(51),
328 
      R => sclr,
329 
      Q => q_3(51)
330 
    );
331 
  BU2_U0_gen_output_regs_output_regs_fd_output_51 : FDR
332 
    generic map(
333 
      INIT => '0'
334 
    )
335 
    port map (
336 
      C => clk,
337 
      D => d_2(50),
338 
      R => sclr,
339 
      Q => q_3(50)
340 
    );
341 
  BU2_U0_gen_output_regs_output_regs_fd_output_50 : FDR
342 
    generic map(
343 
      INIT => '0'
344 
    )
345 
    port map (
346 
      C => clk,
347 
      D => d_2(49),
348 
      R => sclr,
349 
      Q => q_3(49)
350 
    );
351 
  BU2_U0_gen_output_regs_output_regs_fd_output_49 : FDR
352 
    generic map(
353 
      INIT => '0'
354 
    )
355 
    port map (
356 
      C => clk,
357 
      D => d_2(48),
358 
      R => sclr,
359 
      Q => q_3(48)
360 
    );
361 
  BU2_U0_gen_output_regs_output_regs_fd_output_48 : FDR
362 
    generic map(
363 
      INIT => '0'
364 
    )
365 
    port map (
366 
      C => clk,
367 
      D => d_2(47),
368 
      R => sclr,
369 
      Q => q_3(47)
370 
    );
371 
  BU2_U0_gen_output_regs_output_regs_fd_output_47 : FDR
372 
    generic map(
373 
      INIT => '0'
374 
    )
375 
    port map (
376 
      C => clk,
377 
      D => d_2(46),
378 
      R => sclr,
379 
      Q => q_3(46)
380 
    );
381 
  BU2_U0_gen_output_regs_output_regs_fd_output_46 : FDR
382 
    generic map(
383 
      INIT => '0'
384 
    )
385 
    port map (
386 
      C => clk,
387 
      D => d_2(45),
388 
      R => sclr,
389 
      Q => q_3(45)
390 
    );
391 
  BU2_U0_gen_output_regs_output_regs_fd_output_45 : FDR
392 
    generic map(
393 
      INIT => '0'
394 
    )
395 
    port map (
396 
      C => clk,
397 
      D => d_2(44),
398 
      R => sclr,
399 
      Q => q_3(44)
400 
    );
401 
  BU2_U0_gen_output_regs_output_regs_fd_output_44 : FDR
402 
    generic map(
403 
      INIT => '0'
404 
    )
405 
    port map (
406 
      C => clk,
407 
      D => d_2(43),
408 
      R => sclr,
409 
      Q => q_3(43)
410 
    );
411 
  BU2_U0_gen_output_regs_output_regs_fd_output_43 : FDR
412 
    generic map(
413 
      INIT => '0'
414 
    )
415 
    port map (
416 
      C => clk,
417 
      D => d_2(42),
418 
      R => sclr,
419 
      Q => q_3(42)
420 
    );
421 
  BU2_U0_gen_output_regs_output_regs_fd_output_42 : FDR
422 
    generic map(
423 
      INIT => '0'
424 
    )
425 
    port map (
426 
      C => clk,
427 
      D => d_2(41),
428 
      R => sclr,
429 
      Q => q_3(41)
430 
    );
431 
  BU2_U0_gen_output_regs_output_regs_fd_output_41 : FDR
432 
    generic map(
433 
      INIT => '0'
434 
    )
435 
    port map (
436 
      C => clk,
437 
      D => d_2(40),
438 
      R => sclr,
439 
      Q => q_3(40)
440 
    );
441 
  BU2_U0_gen_output_regs_output_regs_fd_output_40 : FDR
442 
    generic map(
443 
      INIT => '0'
444 
    )
445 
    port map (
446 
      C => clk,
447 
      D => d_2(39),
448 
      R => sclr,
449 
      Q => q_3(39)
450 
    );
451 
  BU2_U0_gen_output_regs_output_regs_fd_output_39 : FDR
452 
    generic map(
453 
      INIT => '0'
454 
    )
455 
    port map (
456 
      C => clk,
457 
      D => d_2(38),
458 
      R => sclr,
459 
      Q => q_3(38)
460 
    );
461 
  BU2_U0_gen_output_regs_output_regs_fd_output_38 : FDR
462 
    generic map(
463 
      INIT => '0'
464 
    )
465 
    port map (
466 
      C => clk,
467 
      D => d_2(37),
468 
      R => sclr,
469 
      Q => q_3(37)
470 
    );
471 
  BU2_U0_gen_output_regs_output_regs_fd_output_37 : FDR
472 
    generic map(
473 
      INIT => '0'
474 
    )
475 
    port map (
476 
      C => clk,
477 
      D => d_2(36),
478 
      R => sclr,
479 
      Q => q_3(36)
480 
    );
481 
  BU2_U0_gen_output_regs_output_regs_fd_output_36 : FDR
482 
    generic map(
483 
      INIT => '0'
484 
    )
485 
    port map (
486 
      C => clk,
487 
      D => d_2(35),
488 
      R => sclr,
489 
      Q => q_3(35)
490 
    );
491 
  BU2_U0_gen_output_regs_output_regs_fd_output_35 : FDR
492 
    generic map(
493 
      INIT => '0'
494 
    )
495 
    port map (
496 
      C => clk,
497 
      D => d_2(34),
498 
      R => sclr,
499 
      Q => q_3(34)
500 
    );
501 
  BU2_U0_gen_output_regs_output_regs_fd_output_34 : FDR
502 
    generic map(
503 
      INIT => '0'
504 
    )
505 
    port map (
506 
      C => clk,
507 
      D => d_2(33),
508 
      R => sclr,
509 
      Q => q_3(33)
510 
    );
511 
  BU2_U0_gen_output_regs_output_regs_fd_output_33 : FDR
512 
    generic map(
513 
      INIT => '0'
514 
    )
515 
    port map (
516 
      C => clk,
517 
      D => d_2(32),
518 
      R => sclr,
519 
      Q => q_3(32)
520 
    );
521 
  BU2_U0_gen_output_regs_output_regs_fd_output_32 : FDR
522 
    generic map(
523 
      INIT => '0'
524 
    )
525 
    port map (
526 
      C => clk,
527 
      D => d_2(31),
528 
      R => sclr,
529 
      Q => q_3(31)
530 
    );
531 
  BU2_U0_gen_output_regs_output_regs_fd_output_31 : FDR
532 
    generic map(
533 
      INIT => '0'
534 
    )
535 
    port map (
536 
      C => clk,
537 
      D => d_2(30),
538 
      R => sclr,
539 
      Q => q_3(30)
540 
    );
541 
  BU2_U0_gen_output_regs_output_regs_fd_output_30 : FDR
542 
    generic map(
543 
      INIT => '0'
544 
    )
545 
    port map (
546 
      C => clk,
547 
      D => d_2(29),
548 
      R => sclr,
549 
      Q => q_3(29)
550 
    );
551 
  BU2_U0_gen_output_regs_output_regs_fd_output_29 : FDR
552 
    generic map(
553 
      INIT => '0'
554 
    )
555 
    port map (
556 
      C => clk,
557 
      D => d_2(28),
558 
      R => sclr,
559 
      Q => q_3(28)
560 
    );
561 
  BU2_U0_gen_output_regs_output_regs_fd_output_28 : FDR
562 
    generic map(
563 
      INIT => '0'
564 
    )
565 
    port map (
566 
      C => clk,
567 
      D => d_2(27),
568 
      R => sclr,
569 
      Q => q_3(27)
570 
    );
571 
  BU2_U0_gen_output_regs_output_regs_fd_output_27 : FDR
572 
    generic map(
573 
      INIT => '0'
574 
    )
575 
    port map (
576 
      C => clk,
577 
      D => d_2(26),
578 
      R => sclr,
579 
      Q => q_3(26)
580 
    );
581 
  BU2_U0_gen_output_regs_output_regs_fd_output_26 : FDR
582 
    generic map(
583 
      INIT => '0'
584 
    )
585 
    port map (
586 
      C => clk,
587 
      D => d_2(25),
588 
      R => sclr,
589 
      Q => q_3(25)
590 
    );
591 
  BU2_U0_gen_output_regs_output_regs_fd_output_25 : FDR
592 
    generic map(
593 
      INIT => '0'
594 
    )
595 
    port map (
596 
      C => clk,
597 
      D => d_2(24),
598 
      R => sclr,
599 
      Q => q_3(24)
600 
    );
601 
  BU2_U0_gen_output_regs_output_regs_fd_output_24 : FDR
602 
    generic map(
603 
      INIT => '0'
604 
    )
605 
    port map (
606 
      C => clk,
607 
      D => d_2(23),
608 
      R => sclr,
609 
      Q => q_3(23)
610 
    );
611 
  BU2_U0_gen_output_regs_output_regs_fd_output_23 : FDR
612 
    generic map(
613 
      INIT => '0'
614 
    )
615 
    port map (
616 
      C => clk,
617 
      D => d_2(22),
618 
      R => sclr,
619 
      Q => q_3(22)
620 
    );
621 
  BU2_U0_gen_output_regs_output_regs_fd_output_22 : FDR
622 
    generic map(
623 
      INIT => '0'
624 
    )
625 
    port map (
626 
      C => clk,
627 
      D => d_2(21),
628 
      R => sclr,
629 
      Q => q_3(21)
630 
    );
631 
  BU2_U0_gen_output_regs_output_regs_fd_output_21 : FDR
632 
    generic map(
633 
      INIT => '0'
634 
    )
635 
    port map (
636 
      C => clk,
637 
      D => d_2(20),
638 
      R => sclr,
639 
      Q => q_3(20)
640 
    );
641 
  BU2_U0_gen_output_regs_output_regs_fd_output_20 : FDR
642 
    generic map(
643 
      INIT => '0'
644 
    )
645 
    port map (
646 
      C => clk,
647 
      D => d_2(19),
648 
      R => sclr,
649 
      Q => q_3(19)
650 
    );
651 
  BU2_U0_gen_output_regs_output_regs_fd_output_19 : FDR
652 
    generic map(
653 
      INIT => '0'
654 
    )
655 
    port map (
656 
      C => clk,
657 
      D => d_2(18),
658 
      R => sclr,
659 
      Q => q_3(18)
660 
    );
661 
  BU2_U0_gen_output_regs_output_regs_fd_output_18 : FDR
662 
    generic map(
663 
      INIT => '0'
664 
    )
665 
    port map (
666 
      C => clk,
667 
      D => d_2(17),
668 
      R => sclr,
669 
      Q => q_3(17)
670 
    );
671 
  BU2_U0_gen_output_regs_output_regs_fd_output_17 : FDR
672 
    generic map(
673 
      INIT => '0'
674 
    )
675 
    port map (
676 
      C => clk,
677 
      D => d_2(16),
678 
      R => sclr,
679 
      Q => q_3(16)
680 
    );
681 
  BU2_U0_gen_output_regs_output_regs_fd_output_16 : FDR
682 
    generic map(
683 
      INIT => '0'
684 
    )
685 
    port map (
686 
      C => clk,
687 
      D => d_2(15),
688 
      R => sclr,
689 
      Q => q_3(15)
690 
    );
691 
  BU2_U0_gen_output_regs_output_regs_fd_output_15 : FDR
692 
    generic map(
693 
      INIT => '0'
694 
    )
695 
    port map (
696 
      C => clk,
697 
      D => d_2(14),
698 
      R => sclr,
699 
      Q => q_3(14)
700 
    );
701 
  BU2_U0_gen_output_regs_output_regs_fd_output_14 : FDR
702 
    generic map(
703 
      INIT => '0'
704 
    )
705 
    port map (
706 
      C => clk,
707 
      D => d_2(13),
708 
      R => sclr,
709 
      Q => q_3(13)
710 
    );
711 
  BU2_U0_gen_output_regs_output_regs_fd_output_13 : FDR
712 
    generic map(
713 
      INIT => '0'
714 
    )
715 
    port map (
716 
      C => clk,
717 
      D => d_2(12),
718 
      R => sclr,
719 
      Q => q_3(12)
720 
    );
721 
  BU2_U0_gen_output_regs_output_regs_fd_output_12 : FDR
722 
    generic map(
723 
      INIT => '0'
724 
    )
725 
    port map (
726 
      C => clk,
727 
      D => d_2(11),
728 
      R => sclr,
729 
      Q => q_3(11)
730 
    );
731 
  BU2_U0_gen_output_regs_output_regs_fd_output_11 : FDR
732 
    generic map(
733 
      INIT => '0'
734 
    )
735 
    port map (
736 
      C => clk,
737 
      D => d_2(10),
738 
      R => sclr,
739 
      Q => q_3(10)
740 
    );
741 
  BU2_U0_gen_output_regs_output_regs_fd_output_10 : FDR
742 
    generic map(
743 
      INIT => '0'
744 
    )
745 
    port map (
746 
      C => clk,
747 
      D => d_2(9),
748 
      R => sclr,
749 
      Q => q_3(9)
750 
    );
751 
  BU2_U0_gen_output_regs_output_regs_fd_output_9 : FDR
752 
    generic map(
753 
      INIT => '0'
754 
    )
755 
    port map (
756 
      C => clk,
757 
      D => d_2(8),
758 
      R => sclr,
759 
      Q => q_3(8)
760 
    );
761 
  BU2_U0_gen_output_regs_output_regs_fd_output_8 : FDR
762 
    generic map(
763 
      INIT => '0'
764 
    )
765 
    port map (
766 
      C => clk,
767 
      D => d_2(7),
768 
      R => sclr,
769 
      Q => q_3(7)
770 
    );
771 
  BU2_U0_gen_output_regs_output_regs_fd_output_7 : FDR
772 
    generic map(
773 
      INIT => '0'
774 
    )
775 
    port map (
776 
      C => clk,
777 
      D => d_2(6),
778 
      R => sclr,
779 
      Q => q_3(6)
780 
    );
781 
  BU2_U0_gen_output_regs_output_regs_fd_output_6 : FDR
782 
    generic map(
783 
      INIT => '0'
784 
    )
785 
    port map (
786 
      C => clk,
787 
      D => d_2(5),
788 
      R => sclr,
789 
      Q => q_3(5)
790 
    );
791 
  BU2_U0_gen_output_regs_output_regs_fd_output_5 : FDR
792 
    generic map(
793 
      INIT => '0'
794 
    )
795 
    port map (
796 
      C => clk,
797 
      D => d_2(4),
798 
      R => sclr,
799 
      Q => q_3(4)
800 
    );
801 
  BU2_U0_gen_output_regs_output_regs_fd_output_4 : FDR
802 
    generic map(
803 
      INIT => '0'
804 
    )
805 
    port map (
806 
      C => clk,
807 
      D => d_2(3),
808 
      R => sclr,
809 
      Q => q_3(3)
810 
    );
811 
  BU2_U0_gen_output_regs_output_regs_fd_output_3 : FDR
812 
    generic map(
813 
      INIT => '0'
814 
    )
815 
    port map (
816 
      C => clk,
817 
      D => d_2(2),
818 
      R => sclr,
819 
      Q => q_3(2)
820 
    );
821 
  BU2_U0_gen_output_regs_output_regs_fd_output_2 : FDR
822 
    generic map(
823 
      INIT => '0'
824 
    )
825 
    port map (
826 
      C => clk,
827 
      D => d_2(1),
828 
      R => sclr,
829 
      Q => q_3(1)
830 
    );
831 
  BU2_U0_gen_output_regs_output_regs_fd_output_1 : FDR
832 
    generic map(
833 
      INIT => '0'
834 
    )
835 
    port map (
836 
      C => clk,
837 
      D => d_2(0),
838 
      R => sclr,
839 
      Q => q_3(0)
840 
    );
841 
 
842 
end STRUCTURE;
843 
 
844 
-- synthesis translate_on

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