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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
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<html>
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<head>
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   <meta name="GENERATOR" content="Mozilla/4.7 (Macintosh; I; PPC) [Netscape]">
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<body>
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<b><font face="Helvetica, Arial"><font color="#BF0000"><font size=+2>Project
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Name: Floating Point Unit</font></font></font></b>
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<p><font size=-1>(See change Log at bottom of page for changes/updates)</font>
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<br> 
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<p><u><font size=+1>Description</font></u>
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<p>This is a single precision floating point unit. It is fully IEEE 754
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compliant. It can currently perform Add/Sub,  Mul and Divide operations,
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as well as integer to floating point and floating point to integer conversions.
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It supports four rounding modes: Round to Nearest Even, Round to Zero,
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Round to +INF and Round to -INF.
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<p>There is now also a separate FP compare unit. It is located in the fpu/fcmp
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directory.
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<br> 
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<p><u><font size=+1>Motivation</font></u>
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<ul>
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<li>
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A 100% IEEE 754 compliant Floating Point Unit</li>
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<li>
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Usable by the OR1K CPU</li>
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<li>
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Options to extend the core</li>
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<li>
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Free !</li>
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</ul>
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<p><br><u><font size=+1>Compatibility</font></u>
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<p>To the best of my knowledge the FPU is 100% IEEE 754 compliant. I have
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run over 14Mil. test vectors on it,  that where generated using the
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SoftFloat library by John R. Hauser, which can be found at: <a href="http://HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/SoftFloat.html">http://HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/SoftFloat.html</a>
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<br>The test pattern generator is included with the distribution.
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<br> 
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<p><u><font size=+1>Performance</font></u>
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<ul>
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<li>
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Single cycle execution</li>
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<li>
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4 stage pipeline (this will probably be change in the future)</li>
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</ul>
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<p><br><u><font size=+1>Implementing the Core</font></u>
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<p>It is very difficult to partition such a complex piece of hardware for
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optimal pipe lining. Therefore you will need a synthesis tool that has
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a "retiring" feature to obtain best results.
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<p>Actual Add/Sub, Multiply and Divide cores must be replaced in the primitives.v
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file, or your synthesis tool must be able to synthesize them for you. I
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might fix this in the future.
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<br> 
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<p><u><font size=+1>Status</font></u>
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<p>Second version of the core is released. Included with the release is
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also a  test bench and a test pattern generator.
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<p>I won't be doing any more work on the core in the near future, except
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for bug fixes.
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<p>The core can be downloaded from OpenCores CVS via <a href="http://www.opencores.org/cvsweb.shtml/">cvsweb</a>
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or via <a href="/cvsmodule.shtml">cvsget</a> (use fpu for module name)
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<br> 
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<p><u><font size=+1>To-Do</font></u>
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<p>Things that need to be done:
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<ul>
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<li>
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Add a remainder function</li>
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<li>
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Predict leading zeros to improve performance of post normalize unit</li>
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</ul>
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<p><br><u><font size=+1>Author / Maintainer</font></u>
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<p>I have been doing ASIC design, verification and synthesis for over 15
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years. I hope you find this cores useful. Please send me a note if you
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intend to use it  !
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<p>Many thanks to Damjan Lampret for his support and motivation !
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<p>Rudolf Usselmann
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<br><a href="mailto:rudi@asics.ws_NOSPAM">rudi@asics.ws_NOSPAM</a>
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<br><a href="http://www.asics.ws">www.asics.ws</a>
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<p>Feel free to send me comments, suggestions and bug reports.
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<br> 
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<p><u><font size=+1>Change Log</font></u>
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<p>9/16/00 RU
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<br>- Added FP compare unit
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<p>9/15/00 RU
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<br>- Added int to float and float to int conversion
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<br>- Fixed documentation
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<p>9/13/200 RU
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<br>- Initial release
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<br> 
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</body>
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</html>
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