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davidklun |
---------------------------------------------------------------------
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---- ----
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---- FPU ----
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---- Floating Point Unit (Double precision) ----
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---- ----
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---- Author: David Lundgren ----
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---- davidklun@gmail.com ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 David Lundgren ----
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---- davidklun@gmail.com ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_misc.all;
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use IEEE.numeric_std.all;
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library work;
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use work.fpupack.all;
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ENTITY fpu_div IS
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PORT(
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clk, rst, enable : IN std_logic;
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opa, opb : IN std_logic_vector (63 DOWNTO 0);
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sign : OUT std_logic;
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mantissa_7 : OUT std_logic_vector (55 DOWNTO 0);
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exponent_out : OUT std_logic_vector (11 DOWNTO 0)
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);
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END fpu_div;
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architecture rtl of fpu_div is
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signal dividend_signal : std_logic_vector(53 downto 0);
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signal divisor_signal : std_logic_vector(53 downto 0);
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signal enable_signal : std_logic;
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signal enable_signal_2 : std_logic;
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signal enable_signal_a : std_logic;
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signal enable_signal_b : std_logic;
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signal enable_signal_c : std_logic;
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signal enable_signal_d : std_logic;
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signal enable_signal_e : std_logic;
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signal dividend_shift : std_logic_vector(5 downto 0);
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signal dividend_shift_2 : std_logic_vector(5 downto 0);
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signal divisor_shift : std_logic_vector(5 downto 0);
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signal divisor_shift_2 : std_logic_vector(5 downto 0);
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signal count_out : std_logic_vector(5 downto 0);
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signal mantissa_a : std_logic_vector(51 downto 0);
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signal mantissa_b : std_logic_vector(51 downto 0);
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signal expon_a : std_logic_vector(10 downto 0);
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signal expon_b : std_logic_vector(10 downto 0);
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signal a_is_norm : std_logic;
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signal b_is_norm : std_logic;
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signal a_is_zero : std_logic;
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signal exponent_a : std_logic_vector(11 downto 0);
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signal exponent_b : std_logic_vector(11 downto 0);
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signal dividend_a : std_logic_vector(51 downto 0);
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signal dividend_a_shifted : std_logic_vector(51 downto 0);
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signal dividend_denorm : std_logic_vector(52 downto 0);
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signal dividend_1 : std_logic_vector(53 downto 0);
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signal divisor_b : std_logic_vector(51 downto 0);
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signal divisor_b_shifted : std_logic_vector(51 downto 0);
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signal divisor_denorm : std_logic_vector(52 downto 0);
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signal divisor_1 : std_logic_vector(53 downto 0);
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signal count_index : std_logic_vector(5 downto 0);
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signal count_nonzero : std_logic;
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signal quotient : std_logic_vector(53 downto 0);
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signal quotient_out : std_logic_vector(53 downto 0);
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signal remainder : std_logic_vector(53 downto 0);
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signal remainder_out : std_logic_vector(53 downto 0);
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signal remainder_msb : std_logic;
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signal count_nonzero_signal : std_logic;
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signal count_nonzero_signal_2 : std_logic;
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signal expon_term : std_logic_vector(11 downto 0);
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signal expon_uf_1 : std_logic;
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signal expon_uf_term_1 : std_logic_vector(11 downto 0);
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signal expon_final_1 : std_logic_vector(11 downto 0);
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signal expon_final_2 : std_logic_vector(11 downto 0);
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signal expon_shift_a : std_logic_vector(11 downto 0);
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signal expon_shift_b : std_logic_vector(11 downto 0);
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signal expon_uf_2 : std_logic;
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signal expon_uf_term_2 : std_logic_vector(11 downto 0);
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signal expon_uf_term_3 : std_logic_vector(11 downto 0);
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signal expon_uf_gt_maxshift : std_logic;
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signal expon_uf_term_4 : std_logic_vector(11 downto 0);
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signal expon_final_3 : std_logic_vector(11 downto 0);
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signal expon_final_4 : std_logic_vector(11 downto 0);
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signal quotient_msb : std_logic;
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signal expon_final_4_et0 : std_logic;
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signal expon_final_4_term : std_logic;
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signal expon_final_5 : std_logic_vector(11 downto 0);
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signal mantissa_1 : std_logic_vector(51 downto 0);
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signal mantissa_2 : std_logic_vector(51 downto 0);
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signal mantissa_3 : std_logic_vector(51 downto 0);
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signal mantissa_4 : std_logic_vector(51 downto 0);
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signal mantissa_5 : std_logic_vector(51 downto 0);
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signal mantissa_6 : std_logic_vector(51 downto 0);
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signal remainder_a : std_logic_vector(107 downto 0);
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signal remainder_shift_term : std_logic_vector(11 downto 0);
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signal remainder_b : std_logic_vector(107 downto 0);
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signal remainder_1 : std_logic_vector(55 downto 0);
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signal remainder_2 : std_logic_vector(55 downto 0);
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signal remainder_3 : std_logic_vector(55 downto 0);
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signal remainder_4 : std_logic_vector(55 downto 0);
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signal remainder_5 : std_logic_vector(55 downto 0);
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signal remainder_6 : std_logic_vector(55 downto 0);
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signal m_norm : std_logic;
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signal rem_lsb : std_logic;
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begin
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sign <= opa(63) xor opb(63);
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expon_a <= opa(62 downto 52);
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expon_b <= opb(62 downto 52);
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a_is_norm <= or_reduce(expon_a);
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b_is_norm <= or_reduce(expon_b);
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a_is_zero <= not or_reduce(opa(62 downto 0));
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exponent_a <= '0' & expon_a;
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exponent_b <= '0' & expon_b;
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dividend_denorm <= dividend_a_shifted & '0';
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dividend_1 <= "01" & dividend_a when a_is_norm = '1' else '0' & dividend_denorm;
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divisor_denorm <= divisor_b_shifted & '0';
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divisor_1 <= "01" & divisor_b when b_is_norm = '1' else '0' & divisor_denorm;
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count_nonzero <= '0' when count_index = "000000" else '1';
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count_index <= count_out;
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quotient_msb <= quotient_out(53);
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mantissa_2 <= quotient_out(52 downto 1);
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mantissa_3 <= quotient_out(51 downto 0);
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mantissa_4 <= mantissa_2 when quotient_msb = '1' else mantissa_3;
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mantissa_5 <= mantissa_2 when expon_final_4 = "000000000001" else mantissa_4;
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mantissa_6 <= mantissa_1 when expon_final_4_et0 = '1' else mantissa_5;
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remainder_a <= quotient_out(53 downto 0) & remainder_msb & remainder_out(52 downto 0);
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remainder_1 <= remainder_b(107 downto 53) & or_reduce(remainder_b(52 downto 0));
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remainder_2 <= quotient_out(0) & remainder_msb & remainder_out(52 downto 0) & '0' ;
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remainder_3 <= remainder_msb & remainder_out(52 downto 0) & "00" ;
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remainder_4 <= remainder_2 when quotient_msb = '1' else remainder_3;
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remainder_5 <= remainder_2 when expon_final_4 = "000000000001" else remainder_4;
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remainder_6 <= remainder_1 when expon_final_4_et0 = '1' else remainder_5;
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m_norm <= or_reduce(expon_final_5);
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rem_lsb <= or_reduce(remainder_6(54 downto 0));
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mantissa_7 <= '0' & m_norm & mantissa_6 & remainder_6(55) & rem_lsb ;
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process
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begin
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wait until clk'event and clk = '1';
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if (rst = '1') then
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exponent_out <= (others =>'0');
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else
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if (a_is_zero = '1') then
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exponent_out <= "000000000000";
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else
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exponent_out <= expon_final_5;
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end if;
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end if;
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end process;
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process
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begin
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wait until clk'event and clk = '1';
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if (rst = '1') then
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count_out <= (others =>'0');
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elsif (enable_signal = '1') then
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count_out <= "110101"; -- 53
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elsif (count_nonzero = '1') then
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count_out <= count_out - "000001";
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end if;
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end process;
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process
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begin
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wait until clk'event and clk = '1';
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if (rst = '1') then
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quotient_out <= (others =>'0');
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remainder_out <= (others =>'0');
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else
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quotient_out <= quotient;
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remainder_out <= remainder;
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end if;
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end process;
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process
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begin
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wait until clk'event and clk = '1';
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if (rst = '1') then
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quotient <= (others =>'0');
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elsif (count_nonzero_signal = '1') then
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if (divisor_signal > dividend_signal) then
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quotient(conv_integer(count_index)) <= '0';
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else
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quotient(conv_integer(count_index)) <= '1';
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end if;
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end if;
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end process;
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process
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begin
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wait until clk'event and clk = '1';
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if (rst = '1') then
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remainder <= (others =>'0');
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remainder_msb <= '0';
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elsif ((not count_nonzero_signal and count_nonzero_signal_2) = '1') then
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remainder <= dividend_signal;
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if (divisor_signal > dividend_signal) then
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remainder_msb <= '0';
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else
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remainder_msb <= '1';
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end if;
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end if;
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end process;
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process
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begin
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wait until clk'event and clk = '1';
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if (rst = '1') then
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dividend_signal <= (others =>'0');
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divisor_signal <= (others =>'0');
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elsif (enable_signal_e = '1') then
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dividend_signal <= dividend_1;
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divisor_signal <= divisor_1;
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elsif (count_nonzero_signal = '1') then
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if (divisor_signal > dividend_signal) then
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dividend_signal <= shl(dividend_signal, conv_std_logic_vector('1', 54));
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else
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dividend_signal <= shl(dividend_signal - divisor_signal, conv_std_logic_vector('1', 54));
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end if;
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end if;
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end process;
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process
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begin
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wait until clk'event and clk = '1';
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if (rst = '1') then
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expon_term <= (others =>'0');
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expon_uf_1 <= '0';
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expon_uf_term_1 <= (others =>'0');
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expon_final_1 <= (others =>'0');
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expon_final_2 <= (others =>'0');
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expon_shift_a <= (others =>'0');
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expon_shift_b <= (others =>'0');
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expon_uf_2 <= '0';
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expon_uf_term_2 <= (others =>'0');
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expon_uf_term_3 <= (others =>'0');
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expon_uf_gt_maxshift <= '0';
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expon_uf_term_4 <= (others =>'0');
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expon_final_3 <= (others =>'0');
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expon_final_4 <= (others =>'0');
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expon_final_4_et0 <= '0';
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expon_final_4_term <= '0';
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expon_final_5 <= (others =>'0');
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mantissa_a <= (others =>'0');
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mantissa_b <= (others =>'0');
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dividend_a <= (others =>'0');
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divisor_b <= (others =>'0');
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dividend_shift <= (others =>'0');
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divisor_shift <= (others =>'0');
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dividend_shift_2 <= (others =>'0');
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divisor_shift_2 <= (others =>'0');
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remainder_shift_term <= (others =>'0');
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remainder_b <= (others =>'0');
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dividend_a_shifted <= (others =>'0');
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divisor_b_shifted <= (others =>'0');
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mantissa_1 <= (others =>'0');
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elsif (enable_signal_2 = '1') then
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expon_term <= exponent_a + "001111111111"; -- 1023
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if (exponent_b > expon_term) then
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expon_uf_1 <= '1';
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else
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expon_uf_1 <= '0';
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end if;
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if (expon_uf_1 = '1') then
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expon_uf_term_1 <= exponent_b - expon_term;
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expon_final_2 <= (others =>'0');
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else
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expon_uf_term_1 <= (others =>'0');
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expon_final_2 <= expon_final_1;
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end if;
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expon_final_1 <= expon_term - exponent_b;
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| 302 |
|
|
if (expon_uf_1 = '1') then
|
| 303 |
|
|
expon_uf_term_1 <= exponent_b - expon_term;
|
| 304 |
|
|
else
|
| 305 |
|
|
expon_uf_term_1 <= (others =>'0');
|
| 306 |
|
|
end if;
|
| 307 |
|
|
if (a_is_norm = '1') then
|
| 308 |
|
|
expon_shift_a <= (others =>'0');
|
| 309 |
|
|
else
|
| 310 |
|
|
expon_shift_a <= "000000" & dividend_shift_2;
|
| 311 |
|
|
end if;
|
| 312 |
|
|
if (b_is_norm = '1') then
|
| 313 |
|
|
expon_shift_b <= (others =>'0');
|
| 314 |
|
|
else
|
| 315 |
|
|
expon_shift_b <= "000000" & divisor_shift_2;
|
| 316 |
|
|
end if;
|
| 317 |
|
|
if (expon_shift_a > expon_final_2) then
|
| 318 |
|
|
expon_uf_2 <= '1';
|
| 319 |
|
|
else
|
| 320 |
|
|
expon_uf_2 <= '0';
|
| 321 |
|
|
end if;
|
| 322 |
|
|
if (expon_uf_2 = '1') then
|
| 323 |
|
|
expon_uf_term_2 <= expon_shift_a - expon_final_2;
|
| 324 |
|
|
else
|
| 325 |
|
|
expon_uf_term_2 <= (others =>'0');
|
| 326 |
|
|
end if;
|
| 327 |
|
|
expon_uf_term_3 <= expon_uf_term_2 + expon_uf_term_1;
|
| 328 |
|
|
if (expon_uf_term_3 > "000000110011") then -- 51
|
| 329 |
|
|
expon_uf_gt_maxshift <= '1';
|
| 330 |
|
|
else
|
| 331 |
|
|
expon_uf_gt_maxshift <= '0';
|
| 332 |
|
|
end if;
|
| 333 |
|
|
if (expon_uf_gt_maxshift = '1') then
|
| 334 |
|
|
expon_uf_term_4 <= "000000110100"; --52
|
| 335 |
|
|
else
|
| 336 |
|
|
expon_uf_term_4 <= expon_uf_term_3;
|
| 337 |
|
|
end if;
|
| 338 |
|
|
if (expon_uf_2 = '1') then
|
| 339 |
|
|
expon_final_3 <= (others =>'0');
|
| 340 |
|
|
else
|
| 341 |
|
|
expon_final_3 <= expon_final_2 - expon_shift_a;
|
| 342 |
|
|
end if;
|
| 343 |
|
|
expon_final_4 <= expon_final_3 + expon_shift_b;
|
| 344 |
|
|
if (expon_final_4 = "000000000000") then
|
| 345 |
|
|
expon_final_4_et0 <= '1';
|
| 346 |
|
|
else
|
| 347 |
|
|
expon_final_4_et0 <= '0';
|
| 348 |
|
|
end if;
|
| 349 |
|
|
if (expon_final_4_et0 = '1') then
|
| 350 |
|
|
expon_final_4_term <= '0';
|
| 351 |
|
|
else
|
| 352 |
|
|
expon_final_4_term <= '1';
|
| 353 |
|
|
end if;
|
| 354 |
|
|
if (quotient_msb = '1') then
|
| 355 |
|
|
expon_final_5 <= expon_final_4;
|
| 356 |
|
|
else
|
| 357 |
|
|
expon_final_5 <= expon_final_4 - expon_final_4_term;
|
| 358 |
|
|
end if;
|
| 359 |
|
|
mantissa_a <= opa(51 downto 0);
|
| 360 |
|
|
mantissa_b <= opb(51 downto 0);
|
| 361 |
|
|
dividend_a <= mantissa_a;
|
| 362 |
|
|
divisor_b <= mantissa_b;
|
| 363 |
|
|
dividend_shift <= count_l_zeros(dividend_a);
|
| 364 |
|
|
divisor_shift <= count_l_zeros(divisor_b);
|
| 365 |
|
|
dividend_shift_2 <= dividend_shift;
|
| 366 |
|
|
divisor_shift_2 <= divisor_shift;
|
| 367 |
|
|
remainder_shift_term <= "000000110100" - expon_uf_term_4; -- 52
|
| 368 |
|
|
remainder_b <= shl(remainder_a, remainder_shift_term);
|
| 369 |
|
|
dividend_a_shifted <= shl(dividend_a, dividend_shift_2);
|
| 370 |
|
|
divisor_b_shifted <= shl(divisor_b, divisor_shift_2);
|
| 371 |
|
|
mantissa_1 <= shr(quotient_out(53 downto 2), expon_uf_term_4);
|
| 372 |
|
|
end if;
|
| 373 |
|
|
end process;
|
| 374 |
|
|
|
| 375 |
|
|
process
|
| 376 |
|
|
begin
|
| 377 |
|
|
wait until clk'event and clk = '1';
|
| 378 |
|
|
if (rst = '1') then
|
| 379 |
|
|
count_nonzero_signal <= '0';
|
| 380 |
|
|
count_nonzero_signal_2 <= '0';
|
| 381 |
|
|
enable_signal <= '0';
|
| 382 |
|
|
enable_signal_a <= '0';
|
| 383 |
|
|
enable_signal_b <= '0';
|
| 384 |
|
|
enable_signal_c <= '0';
|
| 385 |
|
|
enable_signal_d <= '0';
|
| 386 |
|
|
enable_signal_e <= '0';
|
| 387 |
|
|
else
|
| 388 |
|
|
count_nonzero_signal <= count_nonzero;
|
| 389 |
|
|
count_nonzero_signal_2 <= count_nonzero_signal;
|
| 390 |
|
|
enable_signal <= enable_signal_e;
|
| 391 |
|
|
enable_signal_a <= enable;
|
| 392 |
|
|
enable_signal_b <= enable_signal_a;
|
| 393 |
|
|
enable_signal_c <= enable_signal_b;
|
| 394 |
|
|
enable_signal_d <= enable_signal_c;
|
| 395 |
|
|
enable_signal_e <= enable_signal_d;
|
| 396 |
|
|
end if;
|
| 397 |
|
|
end process;
|
| 398 |
|
|
|
| 399 |
|
|
process
|
| 400 |
|
|
begin
|
| 401 |
|
|
wait until clk'event and clk = '1';
|
| 402 |
|
|
if (rst = '1') then
|
| 403 |
|
|
enable_signal_2 <= '0';
|
| 404 |
|
|
elsif (enable = '1') then
|
| 405 |
|
|
enable_signal_2 <= '1';
|
| 406 |
|
|
end if;
|
| 407 |
|
|
end process;
|
| 408 |
|
|
|
| 409 |
|
|
end rtl;
|
