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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPDivide96.sv] - Blame information for rev 82

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`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      DFPDivide96.sv
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//    - decimal floating point divider
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//    - parameterized width
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//
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//      Floating Point Divider
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//
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//Properties:
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//+-inf * +-inf = -+inf    (this is handled by exOver)
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//+-inf * 0     = QNaN
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//+-0 / +-0      = QNaN
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// ============================================================================
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import DFPPkg::*;
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`define QINFDIV         4'd2
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`define QZEROZERO       4'd3
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module DFPDivide96(rst, clk, ce, ld, op, a, b, o, done, sign_exe, overflow, underflow);
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parameter N=25;
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// FADD is a constant that makes the divider width a multiple of four and includes eight extra bits.
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input rst;
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input clk;
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input ce;
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input ld;
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input op;
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input  DFP96 a, b;
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output DFP96UD o;
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output reg done;
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output sign_exe;
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output overflow;
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output underflow;
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// registered outputs
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reg sign_exe=0;
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reg inf=0;
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reg     overflow=0;
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reg     underflow=0;
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reg so, sxo;
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reg [11:0] xo;
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reg [(N+1)*4*2-1:0] mo;
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DFP96U au, bu;
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DFPUnpack96 u01 (a, au);
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DFPUnpack96 u02 (b, bu);
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// constants
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wire [11:0] infXp = 12'hBFF;    // infinite / NaN - all ones
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wire [11:0] bias = 12'h5FF;
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// The following is the value for an exponent of zero, with the offset
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// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
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// The following is a template for a quiet nan. (MSB=1)
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wire [N*4-1:0] qNaN  = {4'h1,{(N-1)*4{1'b0}}};
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// variables
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wire [(N+2)*4*2-1:0] divo;
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// Operands
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reg sa, sb;                     // sign bit
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reg [N*4-1:0] siga, sigb;
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reg az, bz;
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reg aInf, bInf;
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reg aNan,bNan;
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wire done1;
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wire signed [7:0] lzcnt;
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// -----------------------------------------------------------
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// Clock #1
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// - decode the input operands
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// - derive basic information
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// - calculate fraction
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// -----------------------------------------------------------
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reg ld1;
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always @(posedge clk)
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        if (ce) sa <= au.sign;
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always @(posedge clk)
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        if (ce) sb <= bu.sign;
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always @(posedge clk)
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        if (ce) siga <= au.sig;
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always @(posedge clk)
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        if (ce) sigb <= bu.sig;
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always @(posedge clk)
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        if (ce) az <= au.exp==12'd0 && au.sig==100'd0;
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always @(posedge clk)
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        if (ce) bz <= bu.exp==12'd0 && bu.sig==100'd0;
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always @(posedge clk)
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        if (ce) aInf <= au.infinity;
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always @(posedge clk)
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        if (ce) bInf <= bu.infinity;
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always @(posedge clk)
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        if (ce) aNan <= au.nan;
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always @(posedge clk)
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        if (ce) bNan <= bu.nan;
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ft_delay #(.WID(1), .DEP(1)) udly1 (.clk(clk), .ce(ce), .i(ld), .o(ld1));
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// -----------------------------------------------------------
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// Clock #2 to N
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// - calculate fraction
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// -----------------------------------------------------------
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wire done3a,done3;
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// Perform divide
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dfdiv #(N+2) u2 (.clk(clk), .ld(ld1), .a({siga,8'b0}), .b({sigb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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//wire [7:0] lzcnt_bin = lzcnt[3:0] + (lzcnt[7:4] * 10);
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wire [(N+2)*4*2-1:0] divo1 = divo[(N+2)*4*2-1:0] << ({lzcnt-1,2'b0});//WAS FPWID=128?+44
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ft_delay #(.WID(1), .DEP(3)) u3 (.clk(clk), .ce(ce), .i(done1), .o(done3a));
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assign done3 = done1&done3a;
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// -----------------------------------------------------------
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// Clock #N+1
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// - calculate exponent
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// - calculate fraction
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// - determine when a NaN is output
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// -----------------------------------------------------------
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// Compute the exponent.
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// - correct the exponent for denormalized operands
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// - adjust the difference by the bias (add 127)
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// - also factor in the different decimal position for division
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reg [13:0] ex1; // sum of exponents
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reg qNaNOut;
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always @(posedge clk)
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  if (ce) ex1 <= au.exp - bu.exp + bias - ((lzcnt > N+2) ? lzcnt-(N+2) : 0);
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always @(posedge clk)
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  if (ce) qNaNOut <= (az&bz)|(aInf&bInf);
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wire over = 1'b0;
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wire under = &ex1[13:12];
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reg [3:0] st;
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// -----------------------------------------------------------
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// Clock #N+3
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// -----------------------------------------------------------
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always_ff @(posedge clk)
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// Simulation likes to see these values reset to zero on reset. Otherwise the
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// values propagate in sim as X's.
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if (rst) begin
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        xo <= 1'd0;
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        mo <= 1'd0;
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        so <= 1'd0;
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        sign_exe <= 1'd0;
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        overflow <= 1'd0;
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        underflow <= 1'd0;
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        done <= 1'b1;
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end
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else if (ce) begin
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  done <= 1'b0;
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        if (done3&done1) begin
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          done <= 1'b1;
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                casez({qNaNOut|aNan|bNan,bInf,bz,over,under})
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                5'b1????:               xo <= infXp;    // NaN exponent value
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                5'b01???:               xo <= 1'd0;             // divide by inf
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                5'b001??:               xo <= infXp;    // divide by zero
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                5'b0001?:               xo <= infXp;    // overflow
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                5'b00001:               xo <= 1'd0;             // underflow
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                default:                xo <= ex1;      // normal or underflow: passthru neg. exp. for normalization
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                endcase
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                casez({aNan,bNan,qNaNOut,bInf,bz,over,aInf&bInf,az&bz})
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                8'b1???????:  begin mo <= {4'h1,au[N*4-1:0],{(N+1)*4-1{1'b0}}}; st[3] <= 1'b1; end
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                8'b01??????:  begin mo <= {4'h1,bu[N*4-1:0],{(N+1)*4-1{1'b0}}}; st[3] <= 1'b1; end
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                8'b001?????:    begin mo <= {4'h1,qNaN[N*4-1:0]|{aInf,1'b0}|{az,bz},{(N+1)*4-1{1'b0}}}; st[3] <= 1'b1; end
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                8'b0001????:    begin mo <= {(N+1)*4*2-1{1'd0}};        st[3] <= 1'b0; end      // div by inf
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                8'b00001???:    begin mo <= {(N+1)*4*2-1{1'd0}};        st[3] <= 1'b0; end      // div by zero
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                8'b000001??:    begin mo <= {(N+1)*4*2-1{1'd0}};        st[3] <= 1'b0; end      // Inf exponent
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                8'b0000001?:    begin mo <= {4'h1,qNaN|`QINFDIV,{(N+1)*4-1{1'b0}}};     st[3] <= 1'b1; end      // infinity / infinity
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                8'b00000001:    begin mo <= {4'h1,qNaN|`QZEROZERO,{(N+1)*4-1{1'b0}}};   st[3] <= 1'b1; end      // zero / zero
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                default:                begin mo <= divo1[(N+2)*4*2-1:8];       st[3] <= 1'b0; end      // plain div
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                endcase
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                sign_exe        <= sa & sb;
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                overflow        <= over;
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                underflow       <= under;
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                o.nan <= aNan|bNan|qNaNOut;
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                o.snan <= aNan|bNan|qNaNOut;
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                o.qnan <= 1'b0;
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                o.infinity <= over|aInf;
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                o.sign <= sa ^ sb;
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                o.exp <= xo;
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                o.sig <= mo;
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        end
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end
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endmodule
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module DFPDivide96nr(rst, clk, ce, ld, op, a, b, o, rm, done, sign_exe, inf, overflow, underflow);
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parameter N=25;
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input rst;
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input clk;
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input ce;
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input ld;
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input op;
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input  DFP96 a, b;
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output DFP96 o;
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input [2:0] rm;
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output sign_exe;
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output done;
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output inf;
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output overflow;
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output underflow;
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DFP96UD o1;
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wire sign_exe1, inf1, overflow1, underflow1;
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DFP96UN fpn0;
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wire done1, done1a;
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DFPDivide96    #(.N(N)) u1 (rst, clk, ce, ld, op, a, b, o1, done1, sign_exe1, overflow1, underflow1);
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DFPNormalize96 #(.N(N)) u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
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DFPRound96     #(.N(N)) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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delay2      #(1)   u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
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delay2      #(1)   u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2      #(1)   u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
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delay2      #(1)   u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
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ft_delay        #(.WID(1),.DEP(14))   u8(.clk(clk), .ce(ce), .i(done1), .o(done1a));
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assign done = done1&done1a;
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endmodule
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