OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPPack.sv] - Blame information for rev 57

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 57 robfinch
// ============================================================================
2
//        __
3
//   \\__/ o\    (C) 2020-2021  Robert Finch, Waterloo
4
//    \  __ /    All rights reserved.
5
//     \/_//     robfinch@finitron.ca
6
//       ||
7
//
8
//      DPDPack.sv
9
//
10
// BSD 3-Clause License
11
// Redistribution and use in source and binary forms, with or without
12
// modification, are permitted provided that the following conditions are met:
13
//
14
// 1. Redistributions of source code must retain the above copyright notice, this
15
//    list of conditions and the following disclaimer.
16
//
17
// 2. Redistributions in binary form must reproduce the above copyright notice,
18
//    this list of conditions and the following disclaimer in the documentation
19
//    and/or other materials provided with the distribution.
20
//
21
// 3. Neither the name of the copyright holder nor the names of its
22
//    contributors may be used to endorse or promote products derived from
23
//    this software without specific prior written permission.
24
//
25
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
29
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35
//
36
// ============================================================================
37
 
38
import DFPPkg::*;
39
 
40
module DFPPack128(i, o);
41
input DFP128U i;
42
output DFP128 o;
43
 
44
wire [109:0] enc_sig;
45
DPDEncodeN #(.N(11)) u1 (i.sig[131:0], enc_sig);
46
 
47
always @*
48
begin
49
        // sign
50
        o.sign <= i.sign;
51
        // combo
52
        if (i.qnan|i.snan)
53
                o.combo <= 5'b11111;
54
        else if (i.infinity)
55
                o.combo <= 5'b11110;
56
        else
57
                o.combo <= i.sig[135:132] > 4'h7 ? {2'b11,i.exp[13:12],i.sig[132]} : {i.exp[13:12],i.sig[134:132]};
58
        // exponent continuation
59
        if (i.qnan)
60
                o.expc <= {1'b0,i.exp[10:0]};
61
        else if (i.snan)
62
                o.expc <= {1'b1,i.exp[10:0]};
63
        else
64
                o.expc <= i.exp[11:0];
65
        // significand continuation
66
        o.sigc <= enc_sig;
67
end
68
 
69
endmodule
70
 
71
module DFPPack64(i, o);
72
input DFP64U i;
73
output DFP64 o;
74
 
75
wire [49:0] enc_sig;
76
DPDEncodeN #(.N(5)) u1 (i.sig[59:0], enc_sig);
77
 
78
always @*
79
begin
80
        // sign
81
        o.sign <= i.sign;
82
        // combo
83
        if (i.qnan|i.snan)
84
                o.combo <= 5'b11111;
85
        else if (i.infinity)
86
                o.combo <= 5'b11110;
87
        else
88
                o.combo <= i.sig[63:60] > 4'h7 ? {2'b11,i.exp[9:8],i.sig[60]} : {i.exp[9:8],i.sig[62:60]};
89
        // exponent continuation
90
        if (i.qnan)
91
                o.expc <= {1'b0,i.exp[6:0]};
92
        else if (i.snan)
93
                o.expc <= {1'b1,i.exp[6:0]};
94
        else
95
                o.expc <= i.exp[7:0];
96
        // significand continuation
97
        o.sigc <= enc_sig;
98
end
99
 
100
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.