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1 2 mballance 
// See LICENSE for license details.
2 
 
3 
#ifndef __TEST_MACROS_SCALAR_H
4 
#define __TEST_MACROS_SCALAR_H
5 
 
6 
 
7 
#-----------------------------------------------------------------------
8 
# Helper macros
9 
#-----------------------------------------------------------------------
10 
 
11 
#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
12 
 
13 
#define SWSIG( testnum, testreg ) \
14 
    la  x28, test_res; \
15 
    sw testreg, (testnum<<2)(x28); \
16 
 
17 
#
18 
# Address = base+(testnum<<2)
19 
# sw testreg, (testnum<<2)(basereg)
20 
#
21 
#define TEST_CASE( testnum, testreg, correctval, code... ) \
22 
test_ ## testnum: \
23 
    code; \
24 
    li  x29, MASK_XLEN(correctval); \
25 
    li  TESTNUM, testnum; \
26 
        SWSIG(testnum,testreg); \
27 
    bne testreg, x29, fail;
28 
 
29 
# We use a macro hack to simpify code generation for various numbers
30 
# of bubble cycles.
31 
 
32 
#define TEST_INSERT_NOPS_0
33 
#define TEST_INSERT_NOPS_1  nop; TEST_INSERT_NOPS_0
34 
#define TEST_INSERT_NOPS_2  nop; TEST_INSERT_NOPS_1
35 
#define TEST_INSERT_NOPS_3  nop; TEST_INSERT_NOPS_2
36 
#define TEST_INSERT_NOPS_4  nop; TEST_INSERT_NOPS_3
37 
#define TEST_INSERT_NOPS_5  nop; TEST_INSERT_NOPS_4
38 
#define TEST_INSERT_NOPS_6  nop; TEST_INSERT_NOPS_5
39 
#define TEST_INSERT_NOPS_7  nop; TEST_INSERT_NOPS_6
40 
#define TEST_INSERT_NOPS_8  nop; TEST_INSERT_NOPS_7
41 
#define TEST_INSERT_NOPS_9  nop; TEST_INSERT_NOPS_8
42 
#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
43 
 
44 
 
45 
#-----------------------------------------------------------------------
46 
# RV64UI MACROS
47 
#-----------------------------------------------------------------------
48 
 
49 
#-----------------------------------------------------------------------
50 
# Tests for instructions with immediate operand
51 
#-----------------------------------------------------------------------
52 
 
53 
#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
54 
 
55 
#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
56 
    TEST_CASE( testnum, x30, result, \
57 
      li  x1, MASK_XLEN(val1); \
58 
      inst x30, x1, SEXT_IMM(imm); \
59 
    )
60 
 
61 
#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
62 
    TEST_CASE( testnum, x1, result, \
63 
      li  x1, MASK_XLEN(val1); \
64 
      inst x1, x1, SEXT_IMM(imm); \
65 
    )
66 
 
67 
#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
68 
    TEST_CASE( testnum, x6, result, \
69 
      li  x4, 0; \
70 
1:    li  x1, MASK_XLEN(val1); \
71 
      inst x30, x1, SEXT_IMM(imm); \
72 
      TEST_INSERT_NOPS_ ## nop_cycles \
73 
      addi  x6, x30, 0; \
74 
      addi  x4, x4, 1; \
75 
      li  x5, 2; \
76 
      bne x4, x5, 1b \
77 
    )
78 
 
79 
#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
80 
    TEST_CASE( testnum, x30, result, \
81 
      li  x4, 0; \
82 
1:    li  x1, MASK_XLEN(val1); \
83 
      TEST_INSERT_NOPS_ ## nop_cycles \
84 
      inst x30, x1, SEXT_IMM(imm); \
85 
      addi  x4, x4, 1; \
86 
      li  x5, 2; \
87 
      bne x4, x5, 1b \
88 
    )
89 
 
90 
#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
91 
    TEST_CASE( testnum, x1, result, \
92 
      inst x1, x0, SEXT_IMM(imm); \
93 
    )
94 
 
95 
#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
96 
    TEST_CASE( testnum, x0, 0, \
97 
      li  x1, MASK_XLEN(val1); \
98 
      inst x0, x1, SEXT_IMM(imm); \
99 
    )
100 
 
101 
#-----------------------------------------------------------------------
102 
# Tests for an instruction with register operands
103 
#-----------------------------------------------------------------------
104 
 
105 
#define TEST_R_OP( testnum, inst, result, val1 ) \
106 
    TEST_CASE( testnum, x30, result, \
107 
      li  x1, val1; \
108 
      inst x30, x1; \
109 
    )
110 
 
111 
#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
112 
    TEST_CASE( testnum, x1, result, \
113 
      li  x1, val1; \
114 
      inst x1, x1; \
115 
    )
116 
 
117 
#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
118 
    TEST_CASE( testnum, x6, result, \
119 
      li  x4, 0; \
120 
1:    li  x1, val1; \
121 
      inst x30, x1; \
122 
      TEST_INSERT_NOPS_ ## nop_cycles \
123 
      addi  x6, x30, 0; \
124 
      addi  x4, x4, 1; \
125 
      li  x5, 2; \
126 
      bne x4, x5, 1b \
127 
    )
128 
 
129 
#-----------------------------------------------------------------------
130 
# Tests for an instruction with register-register operands
131 
#-----------------------------------------------------------------------
132 
 
133 
#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
134 
    TEST_CASE( testnum, x30, result, \
135 
      li  x1, MASK_XLEN(val1); \
136 
      li  x2, MASK_XLEN(val2); \
137 
      inst x30, x1, x2; \
138 
    )
139 
 
140 
#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
141 
    TEST_CASE( testnum, x1, result, \
142 
      li  x1, MASK_XLEN(val1); \
143 
      li  x2, MASK_XLEN(val2); \
144 
      inst x1, x1, x2; \
145 
    )
146 
 
147 
#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
148 
    TEST_CASE( testnum, x2, result, \
149 
      li  x1, MASK_XLEN(val1); \
150 
      li  x2, MASK_XLEN(val2); \
151 
      inst x2, x1, x2; \
152 
    )
153 
 
154 
#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
155 
    TEST_CASE( testnum, x1, result, \
156 
      li  x1, MASK_XLEN(val1); \
157 
      inst x1, x1, x1; \
158 
    )
159 
 
160 
#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
161 
    TEST_CASE( testnum, x6, result, \
162 
      li  x4, 0; \
163 
1:    li  x1, MASK_XLEN(val1); \
164 
      li  x2, MASK_XLEN(val2); \
165 
      inst x30, x1, x2; \
166 
      TEST_INSERT_NOPS_ ## nop_cycles \
167 
      addi  x6, x30, 0; \
168 
      addi  x4, x4, 1; \
169 
      li  x5, 2; \
170 
      bne x4, x5, 1b \
171 
    )
172 
 
173 
#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
174 
    TEST_CASE( testnum, x30, result, \
175 
      li  x4, 0; \
176 
1:    li  x1, MASK_XLEN(val1); \
177 
      TEST_INSERT_NOPS_ ## src1_nops \
178 
      li  x2, MASK_XLEN(val2); \
179 
      TEST_INSERT_NOPS_ ## src2_nops \
180 
      inst x30, x1, x2; \
181 
      addi  x4, x4, 1; \
182 
      li  x5, 2; \
183 
      bne x4, x5, 1b \
184 
    )
185 
 
186 
#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
187 
    TEST_CASE( testnum, x30, result, \
188 
      li  x4, 0; \
189 
1:    li  x2, MASK_XLEN(val2); \
190 
      TEST_INSERT_NOPS_ ## src1_nops \
191 
      li  x1, MASK_XLEN(val1); \
192 
      TEST_INSERT_NOPS_ ## src2_nops \
193 
      inst x30, x1, x2; \
194 
      addi  x4, x4, 1; \
195 
      li  x5, 2; \
196 
      bne x4, x5, 1b \
197 
    )
198 
 
199 
#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
200 
    TEST_CASE( testnum, x2, result, \
201 
      li x1, MASK_XLEN(val); \
202 
      inst x2, x0, x1; \
203 
    )
204 
 
205 
#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
206 
    TEST_CASE( testnum, x2, result, \
207 
      li x1, MASK_XLEN(val); \
208 
      inst x2, x1, x0; \
209 
    )
210 
 
211 
#define TEST_RR_ZEROSRC12( testnum, inst, result ) \
212 
    TEST_CASE( testnum, x1, result, \
213 
      inst x1, x0, x0; \
214 
    )
215 
 
216 
#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
217 
    TEST_CASE( testnum, x0, 0, \
218 
      li x1, MASK_XLEN(val1); \
219 
      li x2, MASK_XLEN(val2); \
220 
      inst x0, x1, x2; \
221 
    )
222 
 
223 
#-----------------------------------------------------------------------
224 
# Test memory instructions
225 
#-----------------------------------------------------------------------
226 
 
227 
#define TEST_LD_OP( testnum, inst, result, offset, base ) \
228 
    TEST_CASE( testnum, x30, result, \
229 
      la  x1, base; \
230 
      inst x30, offset(x1); \
231 
    )
232 
 
233 
#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
234 
    TEST_CASE( testnum, x30, result, \
235 
      la  x1, base; \
236 
      li  x2, result; \
237 
      store_inst x2, offset(x1); \
238 
      load_inst x30, offset(x1); \
239 
    )
240 
 
241 
#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
242 
test_ ## testnum: \
243 
    li  TESTNUM, testnum; \
244 
  SWSIG (testnum, TESTNUM);\
245 
    li  x4, 0; \
246 
1:  la  x1, base; \
247 
    inst x30, offset(x1); \
248 
    TEST_INSERT_NOPS_ ## nop_cycles \
249 
    addi  x6, x30, 0; \
250 
    li  x29, result; \
251 
    bne x6, x29, fail; \
252 
    addi  x4, x4, 1; \
253 
    li  x5, 2; \
254 
    bne x4, x5, 1b; \
255 
 
256 
#define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
257 
test_ ## testnum: \
258 
    li  TESTNUM, testnum; \
259 
  SWSIG (testnum, TESTNUM);\
260 
    li  x4, 0; \
261 
1:  la  x1, base; \
262 
    TEST_INSERT_NOPS_ ## nop_cycles \
263 
    inst x30, offset(x1); \
264 
    li  x29, result; \
265 
    bne x30, x29, fail; \
266 
    addi  x4, x4, 1; \
267 
    li  x5, 2; \
268 
    bne x4, x5, 1b \
269 
 
270 
#define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
271 
test_ ## testnum: \
272 
    li  TESTNUM, testnum; \
273 
  SWSIG (testnum, TESTNUM);\
274 
    li  x4, 0; \
275 
1:  li  x1, result; \
276 
    TEST_INSERT_NOPS_ ## src1_nops \
277 
    la  x2, base; \
278 
    TEST_INSERT_NOPS_ ## src2_nops \
279 
    store_inst x1, offset(x2); \
280 
    load_inst x30, offset(x2); \
281 
    li  x29, result; \
282 
    bne x30, x29, fail; \
283 
    addi  x4, x4, 1; \
284 
    li  x5, 2; \
285 
    bne x4, x5, 1b \
286 
 
287 
#define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
288 
test_ ## testnum: \
289 
    li  TESTNUM, testnum; \
290 
  SWSIG (testnum, TESTNUM);\
291 
    li  x4, 0; \
292 
1:  la  x2, base; \
293 
    TEST_INSERT_NOPS_ ## src1_nops \
294 
    li  x1, result; \
295 
    TEST_INSERT_NOPS_ ## src2_nops \
296 
    store_inst x1, offset(x2); \
297 
    load_inst x30, offset(x2); \
298 
    li  x29, result; \
299 
    bne x30, x29, fail; \
300 
    addi  x4, x4, 1; \
301 
    li  x5, 2; \
302 
    bne x4, x5, 1b \
303 
 
304 
#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
305 
test_ ## testnum: \
306 
    li  TESTNUM, testnum; \
307 
  SWSIG (testnum, TESTNUM);\
308 
    li  x1, val1; \
309 
    li  x2, val2; \
310 
    inst x1, x2, 2f; \
311 
    bne x0, TESTNUM, fail; \
312 
1:  bne x0, TESTNUM, 3f; \
313 
2:  inst x1, x2, 1b; \
314 
    bne x0, TESTNUM, fail; \
315 
3:
316 
 
317 
#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
318 
test_ ## testnum: \
319 
    li  TESTNUM, testnum; \
320 
  SWSIG (testnum, TESTNUM);\
321 
    li  x1, val1; \
322 
    li  x2, val2; \
323 
    inst x1, x2, 1f; \
324 
    bne x0, TESTNUM, 2f; \
325 
1:  bne x0, TESTNUM, fail; \
326 
2:  inst x1, x2, 1b; \
327 
3:
328 
 
329 
#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
330 
test_ ## testnum: \
331 
    li  TESTNUM, testnum; \
332 
  SWSIG (testnum, TESTNUM);\
333 
    li  x4, 0; \
334 
1:  li  x1, val1; \
335 
    TEST_INSERT_NOPS_ ## src1_nops \
336 
    li  x2, val2; \
337 
    TEST_INSERT_NOPS_ ## src2_nops \
338 
    inst x1, x2, fail; \
339 
    addi  x4, x4, 1; \
340 
    li  x5, 2; \
341 
    bne x4, x5, 1b \
342 
 
343 
#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
344 
test_ ## testnum: \
345 
    li  TESTNUM, testnum; \
346 
  SWSIG (testnum, TESTNUM);\
347 
    li  x4, 0; \
348 
1:  li  x2, val2; \
349 
    TEST_INSERT_NOPS_ ## src1_nops \
350 
    li  x1, val1; \
351 
    TEST_INSERT_NOPS_ ## src2_nops \
352 
    inst x1, x2, fail; \
353 
    addi  x4, x4, 1; \
354 
    li  x5, 2; \
355 
    bne x4, x5, 1b \
356 
 
357 
#-----------------------------------------------------------------------
358 
# Test jump instructions
359 
#-----------------------------------------------------------------------
360 
 
361 
#define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
362 
test_ ## testnum: \
363 
    li  TESTNUM, testnum; \
364 
  SWSIG (testnum, TESTNUM);\
365 
    li  x4, 0; \
366 
1:  la  x6, 2f; \
367 
    TEST_INSERT_NOPS_ ## nop_cycles \
368 
    inst x6; \
369 
    bne x0, TESTNUM, fail; \
370 
2:  addi  x4, x4, 1; \
371 
    li  x5, 2; \
372 
    bne x4, x5, 1b \
373 
 
374 
#define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
375 
test_ ## testnum: \
376 
    li  TESTNUM, testnum; \
377 
  SWSIG (testnum, TESTNUM);\
378 
    li  x4, 0; \
379 
1:  la  x6, 2f; \
380 
    TEST_INSERT_NOPS_ ## nop_cycles \
381 
    inst x19, x6, 0; \
382 
    bne x0, TESTNUM, fail; \
383 
2:  addi  x4, x4, 1; \
384 
    li  x5, 2; \
385 
    bne x4, x5, 1b \
386 
 
387 
 
388 
#-----------------------------------------------------------------------
389 
# RV64UF MACROS
390 
#-----------------------------------------------------------------------
391 
 
392 
#-----------------------------------------------------------------------
393 
# Tests floating-point instructions
394 
#-----------------------------------------------------------------------
395 
 
396 
#define qNaNf 0f:7fc00000
397 
#define sNaNf 0f:7f800001
398 
#define qNaN 0d:7ff8000000000000
399 
#define sNaN 0d:7ff0000000000001
400 
 
401 
#define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
402 
test_ ## testnum: \
403 
  li  TESTNUM, testnum; \
404 
  SWSIG (testnum, TESTNUM);\
405 
  la  a0, test_ ## testnum ## _data ;\
406 
  flw f0, 0(a0); \
407 
  flw f1, 4(a0); \
408 
  flw f2, 8(a0); \
409 
  lw  a3, 12(a0); \
410 
  code; \
411 
  fsflags a1, x0; \
412 
  li a2, flags; \
413 
  bne a0, a3, fail; \
414 
  bne a1, a2, fail; \
415 
  .pushsection .data; \
416 
  .align 2; \
417 
  test_ ## testnum ## _data: \
418 
  .float val1; \
419 
  .float val2; \
420 
  .float val3; \
421 
  .result; \
422 
  .popsection
423 
 
424 
#define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
425 
test_ ## testnum: \
426 
  li  TESTNUM, testnum; \
427 
  SWSIG (testnum, TESTNUM);\
428 
  la  a0, test_ ## testnum ## _data ;\
429 
  fld f0, 0(a0); \
430 
  fld f1, 8(a0); \
431 
  fld f2, 16(a0); \
432 
  ld  a3, 24(a0); \
433 
  code; \
434 
  fsflags a1, x0; \
435 
  li a2, flags; \
436 
  bne a0, a3, fail; \
437 
  bne a1, a2, fail; \
438 
  .pushsection .data; \
439 
  .align 3; \
440 
  test_ ## testnum ## _data: \
441 
  .double val1; \
442 
  .double val2; \
443 
  .double val3; \
444 
  .result; \
445 
  .popsection
446 
 
447 
// TODO: assign a separate mem location for the comparison address?
448 
#define TEST_FP_OP_D32_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
449 
test_ ## testnum: \
450 
  li  TESTNUM, testnum; \
451 
  SWSIG (testnum, TESTNUM);\
452 
  la  a0, test_ ## testnum ## _data ;\
453 
  fld f0, 0(a0); \
454 
  fld f1, 8(a0); \
455 
  fld f2, 16(a0); \
456 
  lw  a3, 24(a0); \
457 
  lw  t1, 28(a0); \
458 
  code; \
459 
  fsflags a1, x0; \
460 
  li a2, flags; \
461 
  bne a0, a3, fail; \
462 
  bne t1, t2, fail; \
463 
  bne a1, a2, fail; \
464 
  .pushsection .data; \
465 
  .align 3; \
466 
  test_ ## testnum ## _data: \
467 
  .double val1; \
468 
  .double val2; \
469 
  .double val3; \
470 
  .result; \
471 
  .popsection
472 
 
473 
#define TEST_FCVT_S_D32( testnum, result, val1 ) \
474 
  TEST_FP_OP_D32_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
475 
                    fcvt.s.d f3, f0; fcvt.d.s f3, f3; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
476 
 
477 
#define TEST_FCVT_S_D( testnum, result, val1 ) \
478 
  TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
479 
                    fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3)
480 
 
481 
#define TEST_FCVT_D_S( testnum, result, val1 ) \
482 
  TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
483 
                    fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
484 
 
485 
#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \
486 
  TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \
487 
                    inst f3, f0; fmv.x.s a0, f3)
488 
 
489 
#define TEST_FP_OP1_D32( testnum, inst, flags, result, val1 ) \
490 
  TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
491 
                    inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
492 
// ^: store computation result in address from a0, load high-word into t2
493 
 
494 
#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \
495 
  TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
496 
                    inst f3, f0; fmv.x.d a0, f3)
497 
 
498 
#define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
499 
  TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
500 
                    inst f3, f0; fmv.x.s a0, f3)
501 
 
502 
#define TEST_FP_OP1_D32_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
503 
  TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
504 
                    inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
505 
// ^: store computation result in address from a0, load high-word into t2
506 
 
507 
#define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
508 
  TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
509 
                    inst f3, f0; fmv.x.d a0, f3)
510 
 
511 
#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
512 
  TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \
513 
                    inst f3, f0, f1; fmv.x.s a0, f3)
514 
 
515 
#define TEST_FP_OP2_D32( testnum, inst, flags, result, val1, val2 ) \
516 
  TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
517 
                    inst f3, f0, f1; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
518 
// ^: store computation result in address from a0, load high-word into t2
519 
 
520 
#define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
521 
  TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
522 
                    inst f3, f0, f1; fmv.x.d a0, f3)
523 
 
524 
#define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
525 
  TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \
526 
                    inst f3, f0, f1, f2; fmv.x.s a0, f3)
527 
 
528 
#define TEST_FP_OP3_D32( testnum, inst, flags, result, val1, val2, val3 ) \
529 
  TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, val3, \
530 
                    inst f3, f0, f1, f2; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
531 
// ^: store computation result in address from a0, load high-word into t2
532 
 
533 
#define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
534 
  TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \
535 
                    inst f3, f0, f1, f2; fmv.x.d a0, f3)
536 
 
537 
#define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
538 
  TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
539 
                    inst a0, f0, rm)
540 
 
541 
#define TEST_FP_INT_OP_D32( testnum, inst, flags, result, val1, rm ) \
542 
  TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
543 
                    inst a0, f0, f1; li t2, 0)
544 
 
545 
#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
546 
  TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
547 
                    inst a0, f0, rm)
548 
 
549 
#define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \
550 
  TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, val2, 0.0, \
551 
                    inst a0, f0, f1)
552 
 
553 
#define TEST_FP_CMP_OP_D32( testnum, inst, flags, result, val1, val2 ) \
554 
  TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \
555 
                    inst a0, f0, f1; li t2, 0)
556 
 
557 
#define TEST_FP_CMP_OP_D( testnum, inst, flags, result, val1, val2 ) \
558 
  TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \
559 
                    inst a0, f0, f1)
560 
 
561 
#define TEST_FCLASS_S(testnum, correct, input) \
562 
  TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x fa0, a0; \
563 
                    fclass.s a0, fa0)
564 
 
565 
#define TEST_FCLASS_D32(testnum, correct, input) \
566 
  TEST_CASE(testnum, a0, correct, \
567 
            la a0, test_ ## testnum ## _data ;\
568 
            fld fa0, 0(a0); \
569 
            fclass.d a0, fa0) \
570 
    .pushsection .data; \
571 
    .align 3; \
572 
    test_ ## testnum ## _data: \
573 
    .dword input; \
574 
    .popsection
575 
 
576 
#define TEST_FCLASS_D(testnum, correct, input) \
577 
  TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \
578 
                    fclass.d a0, fa0)
579 
 
580 
#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
581 
test_ ## testnum: \
582 
  li  TESTNUM, testnum; \
583 
  SWSIG (testnum, TESTNUM);\
584 
  la  a0, test_ ## testnum ## _data ;\
585 
  lw  a3, 0(a0); \
586 
  li  a0, val1; \
587 
  inst f0, a0; \
588 
  fsflags x0; \
589 
  fmv.x.s a0, f0; \
590 
  bne a0, a3, fail; \
591 
  .pushsection .data; \
592 
  .align 2; \
593 
  test_ ## testnum ## _data: \
594 
  .float result; \
595 
  .popsection
596 
 
597 
#define TEST_INT_FP_OP_D32( testnum, inst, result, val1 ) \
598 
test_ ## testnum: \
599 
  li  TESTNUM, testnum; \
600 
  SWSIG (testnum, TESTNUM);\
601 
  la  a0, test_ ## testnum ## _data ;\
602 
  lw  a3, 0(a0); \
603 
  lw  a4, 4(a0); \
604 
  li  a1, val1; \
605 
  inst f0, a1; \
606 
  \
607 
  fsd f0, 0(a0); \
608 
  lw a1, 4(a0); \
609 
  lw a0, 0(a0); \
610 
  \
611 
  fsflags x0; \
612 
  bne a0, a3, fail; \
613 
  bne a1, a4, fail; \
614 
  .pushsection .data; \
615 
  .align 3; \
616 
  test_ ## testnum ## _data: \
617 
  .double result; \
618 
  .popsection
619 
 
620 
#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
621 
test_ ## testnum: \
622 
  li  TESTNUM, testnum; \
623 
  SWSIG (testnum, TESTNUM);\
624 
  la  a0, test_ ## testnum ## _data ;\
625 
  ld  a3, 0(a0); \
626 
  li  a0, val1; \
627 
  inst f0, a0; \
628 
  fsflags x0; \
629 
  fmv.x.d a0, f0; \
630 
  bne a0, a3, fail; \
631 
  .pushsection .data; \
632 
  .align 3; \
633 
  test_ ## testnum ## _data: \
634 
  .double result; \
635 
  .popsection
636 
 
637 
// We need some special handling here to allow 64-bit comparison in 32-bit arch
638 
// TODO: find a better name and clean up when intended for general usage?
639 
#define TEST_CASE_D32( testnum, testreg1, testreg2, correctval, code... ) \
640 
test_ ## testnum: \
641 
    code; \
642 
    la  x31, test_ ## testnum ## _data ; \
643 
    lw  x29, 0(x31); \
644 
    lw  x31, 4(x31); \
645 
    li  TESTNUM, testnum; \
646 
    SWSIG (testnum, TESTNUM);\
647 
    bne testreg1, x29, fail;\
648 
    bne testreg2, x31, fail;\
649 
    .pushsection .data; \
650 
    .align 3; \
651 
    test_ ## testnum ## _data: \
652 
    .dword correctval; \
653 
    .popsection
654 
 
655 
// ^ x30 is used in some other macros, to avoid issues we use x31 for upper word
656 
 
657 
#-----------------------------------------------------------------------
658 
# Pass and fail code (assumes test num is in TESTNUM)
659 
#-----------------------------------------------------------------------
660 
 
661 
#define TEST_PASSFAIL \
662 
        bne x0, TESTNUM, pass; \
663 
fail: \
664 
        RVTEST_FAIL; \
665 
pass: \
666 
        RVTEST_PASS \
667 
 
668 
 
669 
#-----------------------------------------------------------------------
670 
# Test data section
671 
#-----------------------------------------------------------------------
672 
 
673 
#define TEST_DATA
674 
 
675 
#endif

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