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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-env/] [test_macros.h] - Blame information for rev 2

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// RISC-V Compliance IO Test Header File
 
/*
 * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
 * either express or implied.
 *
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 */
 
 
//
// In general the following registers are reserved
// ra, a0, t0, t1
// Additionally on an assertion violation, t1, t2 are overwritten
// x1, x10, x5, x6, x7 respectively
// Floating registers reserved
// f5
//
 
#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
 
#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
 
// Base function for integer operations
#define TEST_CASE(destreg, correctval, swreg, offset, code... ) \
    code; \
    sw destreg, offset(swreg); \
    RVTEST_IO_ASSERT_GPR_EQ(destreg, correctval) \
 
// Base functions for single precision floating point operations
#define TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \
    la  a0, test_ ## test_num ## _data; \
    flw reg1, 0(a0); \
    flw reg2, 4(a0); \
    lw t1, 8(a0); \
    code; \
    fsw destreg, offset(swreg); \
    RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
    .pushsection .data; \
    .align 3; \
    test_ ## test_num ## _data: \
      .float val1; \
      .float val2; \
      .word correctval; \
    .popsection
 
#define TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
    la  a0, test_ ## test_num ## _data; \
    lw t1, 0(a0); \
    code; \
    fsw destreg, offset(swreg); \
    RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
    .pushsection .data; \
    .align 1; \
    test_ ## test_num ## _data: \
      .word correctval; \
    .popsection
 
#define TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
    la  a0, test_ ## test_num ## _data; \
    flw reg, 0(a0); \
    lw t1, 4(a0); \
    code; \
    sw destreg, offset(swreg); \
    RVTEST_IO_ASSERT_GPR_EQ(destreg, correctval) \
    .pushsection .data; \
    .align 2; \
    test_ ## test_num ## _data: \
      .float val; \
      .word correctval; \
    .popsection
 
#define TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \
    la  a0, test_ ## test_num ## _data; \
    flw reg1, 0(a0); \
    flw reg2, 4(a0); \
    flw reg3, 8(a0); \
    lw t1, 12(a0); \
    code; \
    fsw destreg, offset(swreg); \
    RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
    .pushsection .data; \
    .align 4; \
    test_ ## test_num ## _data: \
      .float val1; \
      .float val2; \
      .float val3; \
      .word correctval; \
    .popsection
 
#define TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
    la  a0, test_ ## test_num ## _data; \
    flw reg, 0(a0); \
    code; \
    sw destreg, offset(swreg); \
    RVTEST_IO_ASSERT_GPR_EQ(destreg, correctval) \
    .pushsection .data; \
    .align 1; \
    test_ ## test_num ## _data: \
      .float val; \
    .popsection
 
#define TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, code...) \
    la  a0, test_ ## test_num ## _data; \
    li reg, val; \
    code; \
    fsw destreg, offset(swreg); \
    lw a1, 0(a0); \
    RVTEST_IO_ASSERT_SFPR_EQ(destreg, a1, correctval) \
    .pushsection .data; \
    .align 1; \
    test_ ## test_num ## _data: \
      .word correctval; \
    .popsection
 
// Base functions for double precision floating point operations - rv32d
#define TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \
    la  a0, test_ ## test_num ## _data; \
    fld reg1, 0(a0); \
    fld reg2, 8(a0); \
    code; \
    fsd destreg, offset(swreg); \
    lw t1, 16(a0); \
    lw t2, 20(a0); \
    la a0, store_ ## test_num ## _data; \
    fsd destreg, 0(a0); \
    lw a1, 0(a0); \
    lw a2, 4(a0); \
    RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
    .pushsection .data; \
    .align 3; \
    test_ ## test_num ## _data: \
      .double val1; \
      .double val2; \
      .dword correctval; \
    .popsection; \
    .pushsection .data; \
    store_ ## test_num ## _data: \
      .fill 1, 8, -1; \
    .popsection
 
#define TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
    la  a0, test_ ## test_num ## _data; \
    code; \
    fsd destreg, offset(swreg); \
    lw t1, 0(a0); \
    lw t2, 4(a0); \
    la a0, store_ ## test_num ## _data; \
    fsd destreg, 0(a0); \
    lw a1, 0(a0); \
    lw a2, 4(a0); \
    RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
    .pushsection .data; \
    .align 1; \
    test_ ## test_num ## _data: \
      .dword correctval; \
    .popsection; \
    store_ ## test_num ## _data: \
      .fill 1, 8, -1; \
    .popsection
 
#define TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
    la  a0, test_ ## test_num ## _data; \
    fld reg, 0(a0); \
    lw t1, 8(a0); \
    code; \
    sw destreg, offset(swreg); \
    RVTEST_IO_ASSERT_GPR_EQ(destreg, correctval) \
    .pushsection .data; \
    .align 2; \
    test_ ## test_num ## _data: \
      .double val; \
      .word correctval; \
    .popsection
 
#define TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \
    la  a0, test_ ## test_num ## _data; \
    fld reg1, 0(a0); \
    fld reg2, 8(a0); \
    fld reg3, 16(a0); \
    code; \
    fsd destreg, offset(swreg); \
    lw t1, 24(a0); \
    lw t2, 28(a0); \
    la a0, store_ ## test_num ## _data; \
    fsd destreg, 0(a0); \
    lw a1, 0(a0); \
    lw a2, 4(a0); \
    RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
    .pushsection .data; \
    .align 4; \
    test_ ## test_num ## _data: \
      .double val1; \
      .double val2; \
      .double val3; \
      .dword correctval; \
    .popsection; \
    .pushsection .data; \
    store_ ## test_num ## _data: \
      .fill 1, 8, -1; \
    .popsection
 
//Tests for a instructions with register-register operand
#define TEST_RR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
    TEST_CASE( destreg, correctval, swreg, offset, \
      li  reg1, MASK_XLEN(val1); \
      li  reg2, MASK_XLEN(val2); \
      inst destreg, reg1, reg2; \
    )
 
#define TEST_RR_SRC1( inst, destreg, reg, correctval, val1, val2, swreg, offset) \
    TEST_CASE( destreg, correctval, swreg, offset, \
      li destreg, MASK_XLEN(val1); \
      li reg, MASK_XLEN(val2); \
      inst destreg, destreg, reg; \
    )
 
#define TEST_RR_SRC2( inst, destreg, reg, correctval, val1, val2, swreg, offset) \
    TEST_CASE( destreg, correctval, swreg, offset, \
      li reg, MASK_XLEN(val1); \
      li destreg, MASK_XLEN(val2); \
      inst destreg, reg, destreg; \
    )
 
#define TEST_RR_SRC12( inst, destreg, correctval, val, swreg, offset) \
    TEST_CASE( destreg, correctval, swreg, offset, \
      li destreg, MASK_XLEN(val1); \
      inst destreg, destreg, destreg; \
    )
 
#define TEST_RR_ZERO1( inst, destreg, reg, correctval, val, swreg, offset) \
    TEST_CASE( destreg, correctval, swreg, offset, \
      li reg, MASK_XLEN(val); \
      inst destreg, x0, reg; \
    )
 
#define TEST_RR_ZERO2( inst, destreg, reg, correctval, val, swreg, offset) \
    TEST_CASE( destreg, correctval, swreg, offset, \
      li reg, MASK_XLEN(val); \
      inst destreg, reg, x0; \
    )
 
#define TEST_RR_ZERO12( inst, destreg, correctval, swreg, offset) \
    TEST_CASE( destreg, correctval, swreg, offset, \
      inst destreg, x0, x0; \
    )
 
#define TEST_RR_ZERODEST( inst, reg1, reg2, val1, val2, swreg, offset) \
    TEST_CASE( x0, 0, swreg, offset, \
      li reg1, MASK_XLEN(val1); \
      li reg2, MASK_XLEN(val2); \
      inst x0, reg1, reg2; \
    )
 
//Tests for a instructions with register-immediate operand
#define TEST_IMM_OP( inst, destreg, reg, correctval, val, imm, swreg, offset) \
    TEST_CASE ( destreg, correctval, swreg, offset, \
      li reg, MASK_XLEN(val); \
      inst destreg, reg, SEXT_IMM(imm); \
    )
 
#define TEST_IMM_SRC( inst, destreg, correctval, val, imm, swreg, offset) \
    TEST_CASE ( destreg, correctval, swreg, offset, \
      li destreg, MASK_XLEN(val); \
      inst destreg, destreg, SEXT_IMM(imm); \
    )
 
#define TEST_IMM_ZEROSRC( inst, destreg, correctval, imm, swreg, offset) \
    TEST_CASE ( destreg, correctval, swreg, offset, \
      inst destreg, x0, SEXT_IMM(imm); \
    )
 
#define TEST_IMM_ZERODEST( inst, reg, val, imm, swreg, offset) \
    TEST_CASE ( x0, 0, swreg, offset, \
      li reg, MASK_XLEN(val); \
      inst x0, reg, SEXT_IMM(imm); \
    )
 
#define TEST_IMM_ONEREG( inst, destreg, correctval, imm, swreg, offset) \
    TEST_CASE ( destreg, correctval, swreg, offset, \
      inst destreg, SEXT_IMM(imm); \
      )
 
#define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset) \
    TEST_CASE ( destreg, correctval, swreg, offset, \
      1: \
      inst destreg, SEXT_IMM(imm); \
      la swreg, 1b; \
      sub destreg, destreg, swreg; \
      )
 
//Tests for a compressed instruction
#define TEST_CR_OP( inst, destreg, reg, correctval, val1, val2, swreg, offset) \
    TEST_CASE ( destreg, correctval, swreg, offset, \
      li reg, MASK_XLEN(val1); \
      li destreg, MASK_XLEN(val2); \
      inst destreg, reg; \
      )
 
#define TEST_CI_OP( inst, destreg, correctval, val, imm, swreg, offset) \
    TEST_CASE( destreg, correctval, swreg, offset, \
      li destreg, MASK_XLEN(val); \
      inst destreg, imm; \
      )
 
#define TEST_CI_OP_NOREG(inst, correctval, imm, swreg, offset) \
    TEST_CASE (x0, correctval, swreg, offset, \
      inst imm; \
      )
 
//Tests for floating point instructions - single precision
#define TEST_FP_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
      TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \
        inst destreg, reg1, reg2; \
        )
 
#define TEST_FP_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
      TEST_CASE_FP(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \
        inst destreg, reg; \
        )
 
#define TEST_FP_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \
      TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \
        inst destreg, reg1, reg2, reg3; \
        )
 
#define TEST_FP_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
      TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, \
        li reg, MASK_XLEN(val); \
        inst destreg, reg; \
        )
 
#define TEST_FP_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
      TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, \
        inst destreg, reg; \
        )
 
//Tests for floating point instructions - double precision
#define TEST_FPD_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
      TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \
        inst destreg, reg1, reg2; \
        )
 
#define TEST_FPD_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
      TEST_CASE_FPD(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \
        inst destreg, reg; \
        )
 
#define TEST_FPD_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \
      TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \
        inst destreg, reg1, reg2, reg3; \
        )
 
#define TEST_FPD_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
      TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, \
        li reg, MASK_XLEN(val); \
        inst destreg, reg; \
        )
 
#define TEST_FPD_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
      TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, \
        inst destreg, reg; \
        )
 
//Temporary macros for certain instructions which are not implemented yet
#define TEST_CADDI16SP(correctval, imm, swreg, offset) \
      TEST_CASE(x2, correctval, swreg, offset, \
      addi x2, x2, imm; \
      )
 
#define TEST_CADDI4SPN(destreg, correctval, imm, swreg, offset) \
      TEST_CASE(destreg, correctval, swreg, offset, \
        addi destreg, x2, SEXT_IMM(imm); \
        )
 
#define TEST_CJL(inst, reg, val, swreg, offset) \
      li x10, val; \
      la reg, 1f; \
      inst reg; \
      li x10, 0x123ab; \
1: \
      sw reg, offset(swreg); \
      RVTEST_IO_ASSERT_GPR_EQ(x10, val); \
 
#define ABS(x) ((x >> 11) ^ x) - (x >> 11)
 
#define TEST_CJ(inst, reg, val, swreg, offset) \
      li reg, val; \
      inst 1f; \
      li reg, 0x123ab; \
1: \
      sw reg, offset(swreg); \
      RVTEST_IO_ASSERT_GPR_EQ(reg, val); \
 
#define TEST_CL(inst, reg, imm, swreg, offset) \
      la reg, test_data; \
      inst reg, imm(reg); \
      sw reg, offset(swreg); \
 
#define TEST_CLWSP(reg, imm, swreg, offset) \
      la x2, test_data; \
      lw reg, imm(x2); \
      sw reg, offset(swreg); \
 
#define TEST_CSW(test_data, inst, reg1, reg2, val, imm, swreg, offset) \
      li reg1, val; \
      la reg2, test_data; \
      inst reg1, imm(reg2); \
      lw reg1, imm(reg2); \
      sw reg1, offset(swreg); \
      RVTEST_IO_ASSERT_GPR_EQ(reg1, val); \
 
#define TEST_CSWSP(test_data, reg, val, imm, swreg, offset) \
      la x2, test_data; \
      li reg, val; \
      sw reg, imm(x2); \
      lw reg, imm(x2); \
      sw reg, offset(swreg); \
      RVTEST_IO_ASSERT_GPR_EQ(reg, val); \
 
#define TEST_CBEQZ(reg, val, swreg, offset) \
      li reg, val; \
      c.sub reg, reg; \
      c.beqz reg, 3f; \
      li reg, 0x123ab; \
3: \
      sw reg, offset(swreg); \
      RVTEST_IO_ASSERT_GPR_EQ(reg, 0x0); \
 
#define TEST_CBNEZ(reg, val, swreg, offset) \
      li reg, val; \
      c.bnez reg, 4f; \
      li reg, 0x0; \
4: \
      sw reg, offset(swreg); \
      RVTEST_IO_ASSERT_GPR_EQ(reg, val); \
 
#define TEST_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset) \
      TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, \
        fmv.x.s destreg, reg; \
        )
 
#define TEST_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset) \
      TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, \
        fmv.s.x destreg, reg; \
        )
 
#define SWSIG(a,b)
 

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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-env/] [test_macros.h] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	mballance	`// RISC-V Compliance IO Test Header File`
2
3			`/*`
4			`* Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com`
5			`*`
6			`* Licensed under the Apache License, Version 2.0 (the "License");`
7			`* you may not use this file except in compliance with the License.`
8			`* You may obtain a copy of the License at`
9			`*`
10			`* http://www.apache.org/licenses/LICENSE-2.0`
11			`*`
12			`* Unless required by applicable law or agreed to in writing, software`
13			`* distributed under the License is distributed on an "AS IS" BASIS,`
14			`* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,`
15			`* either express or implied.`
16			`*`
17			`* See the License for the specific language governing permissions and`
18			`* limitations under the License.`
19			`*`
20			`*/`
21
22
23			`//`
24			`// In general the following registers are reserved`
25			`// ra, a0, t0, t1`
26			`// Additionally on an assertion violation, t1, t2 are overwritten`
27			`// x1, x10, x5, x6, x7 respectively`
28			`// Floating registers reserved`
29			`// f5`
30			`//`
31
32			`#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))`
33
34			`#define SEXT_IMM(x) ((x) \| (-(((x) >> 11) & 1) << 11))`
35
36			`// Base function for integer operations`
37			`#define TEST_CASE(destreg, correctval, swreg, offset, code... ) \`
38			`code; \`
39			`sw destreg, offset(swreg); \`
40			`RVTEST_IO_ASSERT_GPR_EQ(destreg, correctval) \`
41
42			`// Base functions for single precision floating point operations`
43			`#define TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \`
44			`la a0, test_ ## test_num ## _data; \`
45			`flw reg1, 0(a0); \`
46			`flw reg2, 4(a0); \`
47			`lw t1, 8(a0); \`
48			`code; \`
49			`fsw destreg, offset(swreg); \`
50			`RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \`
51			`.pushsection .data; \`
52			`.align 3; \`
53			`test_ ## test_num ## _data: \`
54			`.float val1; \`
55			`.float val2; \`
56			`.word correctval; \`
57			`.popsection`
58
59			`#define TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \`
60			`la a0, test_ ## test_num ## _data; \`
61			`lw t1, 0(a0); \`
62			`code; \`
63			`fsw destreg, offset(swreg); \`
64			`RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \`
65			`.pushsection .data; \`
66			`.align 1; \`
67			`test_ ## test_num ## _data: \`
68			`.word correctval; \`
69			`.popsection`
70
71			`#define TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \`
72			`la a0, test_ ## test_num ## _data; \`
73			`flw reg, 0(a0); \`
74			`lw t1, 4(a0); \`
75			`code; \`
76			`sw destreg, offset(swreg); \`
77			`RVTEST_IO_ASSERT_GPR_EQ(destreg, correctval) \`
78			`.pushsection .data; \`
79			`.align 2; \`
80			`test_ ## test_num ## _data: \`
81			`.float val; \`
82			`.word correctval; \`
83			`.popsection`
84
85			`#define TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \`
86			`la a0, test_ ## test_num ## _data; \`
87			`flw reg1, 0(a0); \`
88			`flw reg2, 4(a0); \`
89			`flw reg3, 8(a0); \`
90			`lw t1, 12(a0); \`
91			`code; \`
92			`fsw destreg, offset(swreg); \`
93			`RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \`
94			`.pushsection .data; \`
95			`.align 4; \`
96			`test_ ## test_num ## _data: \`
97			`.float val1; \`
98			`.float val2; \`
99			`.float val3; \`
100			`.word correctval; \`
101			`.popsection`
102
103			`#define TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \`
104			`la a0, test_ ## test_num ## _data; \`
105			`flw reg, 0(a0); \`
106			`code; \`
107			`sw destreg, offset(swreg); \`
108			`RVTEST_IO_ASSERT_GPR_EQ(destreg, correctval) \`
109			`.pushsection .data; \`
110			`.align 1; \`
111			`test_ ## test_num ## _data: \`
112			`.float val; \`
113			`.popsection`
114
115			`#define TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, code...) \`
116			`la a0, test_ ## test_num ## _data; \`
117			`li reg, val; \`
118			`code; \`
119			`fsw destreg, offset(swreg); \`
120			`lw a1, 0(a0); \`
121			`RVTEST_IO_ASSERT_SFPR_EQ(destreg, a1, correctval) \`
122			`.pushsection .data; \`
123			`.align 1; \`
124			`test_ ## test_num ## _data: \`
125			`.word correctval; \`
126			`.popsection`
127
128			`// Base functions for double precision floating point operations - rv32d`
129			`#define TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \`
130			`la a0, test_ ## test_num ## _data; \`
131			`fld reg1, 0(a0); \`
132			`fld reg2, 8(a0); \`
133			`code; \`
134			`fsd destreg, offset(swreg); \`
135			`lw t1, 16(a0); \`
136			`lw t2, 20(a0); \`
137			`la a0, store_ ## test_num ## _data; \`
138			`fsd destreg, 0(a0); \`
139			`lw a1, 0(a0); \`
140			`lw a2, 4(a0); \`
141			`RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \`
142			`.pushsection .data; \`
143			`.align 3; \`
144			`test_ ## test_num ## _data: \`
145			`.double val1; \`
146			`.double val2; \`
147			`.dword correctval; \`
148			`.popsection; \`
149			`.pushsection .data; \`
150			`store_ ## test_num ## _data: \`
151			`.fill 1, 8, -1; \`
152			`.popsection`
153
154			`#define TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \`
155			`la a0, test_ ## test_num ## _data; \`
156			`code; \`
157			`fsd destreg, offset(swreg); \`
158			`lw t1, 0(a0); \`
159			`lw t2, 4(a0); \`
160			`la a0, store_ ## test_num ## _data; \`
161			`fsd destreg, 0(a0); \`
162			`lw a1, 0(a0); \`
163			`lw a2, 4(a0); \`
164			`RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \`
165			`.pushsection .data; \`
166			`.align 1; \`
167			`test_ ## test_num ## _data: \`
168			`.dword correctval; \`
169			`.popsection; \`
170			`store_ ## test_num ## _data: \`
171			`.fill 1, 8, -1; \`
172			`.popsection`
173
174			`#define TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \`
175			`la a0, test_ ## test_num ## _data; \`
176			`fld reg, 0(a0); \`
177			`lw t1, 8(a0); \`
178			`code; \`
179			`sw destreg, offset(swreg); \`
180			`RVTEST_IO_ASSERT_GPR_EQ(destreg, correctval) \`
181			`.pushsection .data; \`
182			`.align 2; \`
183			`test_ ## test_num ## _data: \`
184			`.double val; \`
185			`.word correctval; \`
186			`.popsection`
187
188			`#define TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \`
189			`la a0, test_ ## test_num ## _data; \`
190			`fld reg1, 0(a0); \`
191			`fld reg2, 8(a0); \`
192			`fld reg3, 16(a0); \`
193			`code; \`
194			`fsd destreg, offset(swreg); \`
195			`lw t1, 24(a0); \`
196			`lw t2, 28(a0); \`
197			`la a0, store_ ## test_num ## _data; \`
198			`fsd destreg, 0(a0); \`
199			`lw a1, 0(a0); \`
200			`lw a2, 4(a0); \`
201			`RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \`
202			`.pushsection .data; \`
203			`.align 4; \`
204			`test_ ## test_num ## _data: \`
205			`.double val1; \`
206			`.double val2; \`
207			`.double val3; \`
208			`.dword correctval; \`
209			`.popsection; \`
210			`.pushsection .data; \`
211			`store_ ## test_num ## _data: \`
212			`.fill 1, 8, -1; \`
213			`.popsection`
214
215			`//Tests for a instructions with register-register operand`
216			`#define TEST_RR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \`
217			`TEST_CASE( destreg, correctval, swreg, offset, \`
218			`li reg1, MASK_XLEN(val1); \`
219			`li reg2, MASK_XLEN(val2); \`
220			`inst destreg, reg1, reg2; \`
221			`)`
222
223			`#define TEST_RR_SRC1( inst, destreg, reg, correctval, val1, val2, swreg, offset) \`
224			`TEST_CASE( destreg, correctval, swreg, offset, \`
225			`li destreg, MASK_XLEN(val1); \`
226			`li reg, MASK_XLEN(val2); \`
227			`inst destreg, destreg, reg; \`
228			`)`
229
230			`#define TEST_RR_SRC2( inst, destreg, reg, correctval, val1, val2, swreg, offset) \`
231			`TEST_CASE( destreg, correctval, swreg, offset, \`
232			`li reg, MASK_XLEN(val1); \`
233			`li destreg, MASK_XLEN(val2); \`
234			`inst destreg, reg, destreg; \`
235			`)`
236
237			`#define TEST_RR_SRC12( inst, destreg, correctval, val, swreg, offset) \`
238			`TEST_CASE( destreg, correctval, swreg, offset, \`
239			`li destreg, MASK_XLEN(val1); \`
240			`inst destreg, destreg, destreg; \`
241			`)`
242
243			`#define TEST_RR_ZERO1( inst, destreg, reg, correctval, val, swreg, offset) \`
244			`TEST_CASE( destreg, correctval, swreg, offset, \`
245			`li reg, MASK_XLEN(val); \`
246			`inst destreg, x0, reg; \`
247			`)`
248
249			`#define TEST_RR_ZERO2( inst, destreg, reg, correctval, val, swreg, offset) \`
250			`TEST_CASE( destreg, correctval, swreg, offset, \`
251			`li reg, MASK_XLEN(val); \`
252			`inst destreg, reg, x0; \`
253			`)`
254
255			`#define TEST_RR_ZERO12( inst, destreg, correctval, swreg, offset) \`
256			`TEST_CASE( destreg, correctval, swreg, offset, \`
257			`inst destreg, x0, x0; \`
258			`)`
259
260			`#define TEST_RR_ZERODEST( inst, reg1, reg2, val1, val2, swreg, offset) \`
261			`TEST_CASE( x0, 0, swreg, offset, \`
262			`li reg1, MASK_XLEN(val1); \`
263			`li reg2, MASK_XLEN(val2); \`
264			`inst x0, reg1, reg2; \`
265			`)`
266
267			`//Tests for a instructions with register-immediate operand`
268			`#define TEST_IMM_OP( inst, destreg, reg, correctval, val, imm, swreg, offset) \`
269			`TEST_CASE ( destreg, correctval, swreg, offset, \`
270			`li reg, MASK_XLEN(val); \`
271			`inst destreg, reg, SEXT_IMM(imm); \`
272			`)`
273
274			`#define TEST_IMM_SRC( inst, destreg, correctval, val, imm, swreg, offset) \`
275			`TEST_CASE ( destreg, correctval, swreg, offset, \`
276			`li destreg, MASK_XLEN(val); \`
277			`inst destreg, destreg, SEXT_IMM(imm); \`
278			`)`
279
280			`#define TEST_IMM_ZEROSRC( inst, destreg, correctval, imm, swreg, offset) \`
281			`TEST_CASE ( destreg, correctval, swreg, offset, \`
282			`inst destreg, x0, SEXT_IMM(imm); \`
283			`)`
284
285			`#define TEST_IMM_ZERODEST( inst, reg, val, imm, swreg, offset) \`
286			`TEST_CASE ( x0, 0, swreg, offset, \`
287			`li reg, MASK_XLEN(val); \`
288			`inst x0, reg, SEXT_IMM(imm); \`
289			`)`
290
291			`#define TEST_IMM_ONEREG( inst, destreg, correctval, imm, swreg, offset) \`
292			`TEST_CASE ( destreg, correctval, swreg, offset, \`
293			`inst destreg, SEXT_IMM(imm); \`
294			`)`
295
296			`#define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset) \`
297			`TEST_CASE ( destreg, correctval, swreg, offset, \`
298			`1: \`
299			`inst destreg, SEXT_IMM(imm); \`
300			`la swreg, 1b; \`
301			`sub destreg, destreg, swreg; \`
302			`)`
303
304			`//Tests for a compressed instruction`
305			`#define TEST_CR_OP( inst, destreg, reg, correctval, val1, val2, swreg, offset) \`
306			`TEST_CASE ( destreg, correctval, swreg, offset, \`
307			`li reg, MASK_XLEN(val1); \`
308			`li destreg, MASK_XLEN(val2); \`
309			`inst destreg, reg; \`
310			`)`
311
312			`#define TEST_CI_OP( inst, destreg, correctval, val, imm, swreg, offset) \`
313			`TEST_CASE( destreg, correctval, swreg, offset, \`
314			`li destreg, MASK_XLEN(val); \`
315			`inst destreg, imm; \`
316			`)`
317
318			`#define TEST_CI_OP_NOREG(inst, correctval, imm, swreg, offset) \`
319			`TEST_CASE (x0, correctval, swreg, offset, \`
320			`inst imm; \`
321			`)`
322
323			`//Tests for floating point instructions - single precision`
324			`#define TEST_FP_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \`
325			`TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \`
326			`inst destreg, reg1, reg2; \`
327			`)`
328
329			`#define TEST_FP_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \`
330			`TEST_CASE_FP(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \`
331			`inst destreg, reg; \`
332			`)`
333
334			`#define TEST_FP_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \`
335			`TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \`
336			`inst destreg, reg1, reg2, reg3; \`
337			`)`
338
339			`#define TEST_FP_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \`
340			`TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, \`
341			`li reg, MASK_XLEN(val); \`
342			`inst destreg, reg; \`
343			`)`
344
345			`#define TEST_FP_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \`
346			`TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, \`
347			`inst destreg, reg; \`
348			`)`
349
350			`//Tests for floating point instructions - double precision`
351			`#define TEST_FPD_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \`
352			`TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \`
353			`inst destreg, reg1, reg2; \`
354			`)`
355
356			`#define TEST_FPD_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \`
357			`TEST_CASE_FPD(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \`
358			`inst destreg, reg; \`
359			`)`
360
361			`#define TEST_FPD_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \`
362			`TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \`
363			`inst destreg, reg1, reg2, reg3; \`
364			`)`
365
366			`#define TEST_FPD_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \`
367			`TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, \`
368			`li reg, MASK_XLEN(val); \`
369			`inst destreg, reg; \`
370			`)`
371
372			`#define TEST_FPD_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \`
373			`TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, \`
374			`inst destreg, reg; \`
375			`)`
376
377			`//Temporary macros for certain instructions which are not implemented yet`
378			`#define TEST_CADDI16SP(correctval, imm, swreg, offset) \`
379			`TEST_CASE(x2, correctval, swreg, offset, \`
380			`addi x2, x2, imm; \`
381			`)`
382
383			`#define TEST_CADDI4SPN(destreg, correctval, imm, swreg, offset) \`
384			`TEST_CASE(destreg, correctval, swreg, offset, \`
385			`addi destreg, x2, SEXT_IMM(imm); \`
386			`)`
387
388			`#define TEST_CJL(inst, reg, val, swreg, offset) \`
389			`li x10, val; \`
390			`la reg, 1f; \`
391			`inst reg; \`
392			`li x10, 0x123ab; \`
393			`1: \`
394			`sw reg, offset(swreg); \`
395			`RVTEST_IO_ASSERT_GPR_EQ(x10, val); \`
396
397			`#define ABS(x) ((x >> 11) ^ x) - (x >> 11)`
398
399			`#define TEST_CJ(inst, reg, val, swreg, offset) \`
400			`li reg, val; \`
401			`inst 1f; \`
402			`li reg, 0x123ab; \`
403			`1: \`
404			`sw reg, offset(swreg); \`
405			`RVTEST_IO_ASSERT_GPR_EQ(reg, val); \`
406
407			`#define TEST_CL(inst, reg, imm, swreg, offset) \`
408			`la reg, test_data; \`
409			`inst reg, imm(reg); \`
410			`sw reg, offset(swreg); \`
411
412			`#define TEST_CLWSP(reg, imm, swreg, offset) \`
413			`la x2, test_data; \`
414			`lw reg, imm(x2); \`
415			`sw reg, offset(swreg); \`
416
417			`#define TEST_CSW(test_data, inst, reg1, reg2, val, imm, swreg, offset) \`
418			`li reg1, val; \`
419			`la reg2, test_data; \`
420			`inst reg1, imm(reg2); \`
421			`lw reg1, imm(reg2); \`
422			`sw reg1, offset(swreg); \`
423			`RVTEST_IO_ASSERT_GPR_EQ(reg1, val); \`
424
425			`#define TEST_CSWSP(test_data, reg, val, imm, swreg, offset) \`
426			`la x2, test_data; \`
427			`li reg, val; \`
428			`sw reg, imm(x2); \`
429			`lw reg, imm(x2); \`
430			`sw reg, offset(swreg); \`
431			`RVTEST_IO_ASSERT_GPR_EQ(reg, val); \`
432
433			`#define TEST_CBEQZ(reg, val, swreg, offset) \`
434			`li reg, val; \`
435			`c.sub reg, reg; \`
436			`c.beqz reg, 3f; \`
437			`li reg, 0x123ab; \`
438			`3: \`
439			`sw reg, offset(swreg); \`
440			`RVTEST_IO_ASSERT_GPR_EQ(reg, 0x0); \`
441
442			`#define TEST_CBNEZ(reg, val, swreg, offset) \`
443			`li reg, val; \`
444			`c.bnez reg, 4f; \`
445			`li reg, 0x0; \`
446			`4: \`
447			`sw reg, offset(swreg); \`
448			`RVTEST_IO_ASSERT_GPR_EQ(reg, val); \`
449
450			`#define TEST_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset) \`
451			`TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, \`
452			`fmv.x.s destreg, reg; \`
453			`)`
454
455			`#define TEST_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset) \`
456			`TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, \`
457			`fmv.s.x destreg, reg; \`
458			`)`
459
460			`#define SWSIG(a,b)`
461