URL https://opencores.org/ocsvn/fwrisc/fwrisc/trunk

Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-ADD-01.S] - Blame information for rev 2

Details | Compare with Previous | View Log


# RISC-V Compliance Test I-ADD-01
#
# Copyright (c) 2017, Codasip Ltd.
# Copyright (c) 2018, Imperas Software Ltd. Additions
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#      * Redistributions of source code must retain the above copyright
#        notice, this list of conditions and the following disclaimer.
#      * Redistributions in binary form must reproduce the above copyright
#        notice, this list of conditions and the following disclaimer in the
#        documentation and/or other materials provided with the distribution.
#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
#        names of its contributors may be used to endorse or promote products
#        derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Specification: RV32I Base Integer Instruction Set, Version 2.0
# Description: Testing instruction ADD.
 
#include "compliance_test.h"
#include "compliance_io.h"
#include "test_macros.h"
 
# Test Virtual Machine (TVM) used by program.
RV_COMPLIANCE_RV32M
 
# Test code region.
RV_COMPLIANCE_CODE_BEGIN
 
    RVTEST_IO_INIT
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n");
 
    # Addresses for test data and results
    la      x1, test_A1_data
    la      x2, test_A1_res
 
    # Load testdata
    lw      x3, 0(x1)
 
    # Register initialization
    li      x4, 0
    li      x5, 1
    li      x6, -1
    li      x7, 0x7FFFFFFF
    li      x8, 0x80000000
 
    # Test
    add     x4, x3, x4
    add     x5, x3, x5
    add     x6, x3, x6
    add     x7, x3, x7
    add     x8, x3, x8
 
    # Store results
    sw      x3, 0(x2)
    sw      x4, 4(x2)
    sw      x5, 8(x2)
    sw      x6, 12(x2)
    sw      x7, 16(x2)
    sw      x8, 20(x2)
 
    //
    // Assert
    //
    RVTEST_IO_CHECK()
    RVTEST_IO_ASSERT_GPR_EQ(x3, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x4, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x5, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x6, 0xFFFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x7, 0x7FFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x8, 0x80000000)
 
    RVTEST_IO_WRITE_STR("# Test part A1  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n");
 
    # Addresses for test data and results
    la      x1, test_A2_data
    la      x2, test_A2_res
 
    # Load testdata
    lw      x8, 0(x1)
 
    # Register initialization
    li      x9, 0
    li      x10, 1
    li      x11, -1
    li      x12, 0x7FFFFFFF
    li      x13, 0x80000000
 
    # Test
    add     x9, x8, x9
    add     x10, x8, x10
    add     x11, x8, x11
    add     x12, x8, x12
    add     x13, x8, x13
 
    # Store results
    sw      x8, 0(x2)
    sw      x9, 4(x2)
    sw      x10, 8(x2)
    sw      x11, 12(x2)
    sw      x12, 16(x2)
    sw      x13, 20(x2)
 
    RVTEST_IO_ASSERT_GPR_EQ(x8, 0x00000001)
    RVTEST_IO_ASSERT_GPR_EQ(x9, 0x00000001)
    #RVTEST_IO_ASSERT_GPR_EQ(x10, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x11, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x12, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x13, 0x80000001)
 
    RVTEST_IO_WRITE_STR("# Test part A2  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n");
 
    # Addresses for test data and results
    la      x1, test_A3_data
    la      x2, test_A3_res
 
    # Load testdata
    lw      x13, 0(x1)
 
    # Register initialization
    li      x14, 0
    li      x15, 1
    li      x16, -1
    li      x17, 0x7FFFFFFF
    li      x18, 0x80000000
 
    # Test
    add     x14, x13, x14
    add     x15, x13, x15
    add     x16, x13, x16
    add     x17, x13, x17
    add     x18, x13, x18
 
    # Store results
    sw      x13, 0(x2)
    sw      x14, 4(x2)
    sw      x15, 8(x2)
    sw      x16, 12(x2)
    sw      x17, 16(x2)
    sw      x18, 20(x2)
 
    RVTEST_IO_ASSERT_GPR_EQ(x13, 0xFFFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x14, 0xFFFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x15, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x16, 0xFFFFFFFE)
    RVTEST_IO_ASSERT_GPR_EQ(x17, 0x7FFFFFFE)
    RVTEST_IO_ASSERT_GPR_EQ(x18, 0x7FFFFFFF)
 
    RVTEST_IO_WRITE_STR("# Test part A3  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n");
 
    # Addresses for test data and results
    la      x1, test_A4_data
    la      x2, test_A4_res
 
    # Load testdata
    lw      x18, 0(x1)
 
    # Register initialization
    li      x19, 0
    li      x20, 1
    li      x21, -1
    li      x22, 0x7FFFFFFF
    li      x23, 0x80000000
 
    # Test execution
    add     x19, x18, x19
    add     x20, x18, x20
    add     x21, x18, x21
    add     x22, x18, x22
    add     x23, x18, x23
 
    # Store results
    sw      x18, 0(x2)
    sw      x19, 4(x2)
    sw      x20, 8(x2)
    sw      x21, 12(x2)
    sw      x22, 16(x2)
    sw      x23, 20(x2)
 
    RVTEST_IO_ASSERT_GPR_EQ(x18, 0x7FFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x19, 0x7FFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x20, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x21, 0x7FFFFFFE)
    RVTEST_IO_ASSERT_GPR_EQ(x22, 0xFFFFFFFE)
    RVTEST_IO_ASSERT_GPR_EQ(x23, 0xFFFFFFFF)
 
    RVTEST_IO_WRITE_STR("# Test part A4  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n");
 
    # Addresses for test data and results
    la      x1, test_A5_data
    la      x2, test_A5_res
 
    # Load testdata
    lw      x23, 0(x1)
 
    # Register initialization
    li      x24, 0
    li      x25, 1
    li      x26, -1
    li      x27, 0x7FFFFFFF
    li      x28, 0x80000000
 
    # Test
    add     x24, x23, x24
    add     x25, x23, x25
    add     x26, x23, x26
    add     x27, x23, x27
    add     x28, x23, x28
 
    # Store results
    sw      x23, 0(x2)
    sw      x24, 4(x2)
    sw      x25, 8(x2)
    sw      x26, 12(x2)
    sw      x27, 16(x2)
    sw      x28, 20(x2)
 
    RVTEST_IO_ASSERT_GPR_EQ(x23, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x24, 0x80000000)
    RVTEST_IO_ASSERT_GPR_EQ(x25, 0x80000001)
    RVTEST_IO_ASSERT_GPR_EQ(x26, 0x7FFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x27, 0xFFFFFFFF)
    RVTEST_IO_ASSERT_GPR_EQ(x28, 0x00000000)
 
    RVTEST_IO_WRITE_STR("# Test part A5  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part B - testing forwarding between instructions\n");
 
    # Addresses for test data and results
    la      x25, test_B_data
    la      x26, test_B_res
 
    # Load testdata
    lw      x28, 0(x25)
 
    # Register initialization
    li      x27, 0x1
 
    # Test
    add     x29, x28, x27
    add     x30, x29, x27
    add     x31, x30, x27
    add     x1, x31, x27
    add     x2, x1, x27
    add     x3, x2, x27
 
    # store results
    sw      x27, 0(x26)
    sw      x28, 4(x26)
    sw      x29, 8(x26)
    sw      x30, 12(x26)
    sw      x31, 16(x26)
    sw      x1, 20(x26)
    sw      x2, 24(x26)
    sw      x3, 28(x26)
 
    RVTEST_IO_ASSERT_GPR_EQ(x27, 0x00000001)
    RVTEST_IO_ASSERT_GPR_EQ(x28, 0x0000ABCD)
    RVTEST_IO_ASSERT_GPR_EQ(x29, 0x0000ABCE)
    RVTEST_IO_ASSERT_GPR_EQ(x30, 0x0000ABCF)
    RVTEST_IO_ASSERT_GPR_EQ(x31, 0x0000ABD0)
    #RVTEST_IO_ASSERT_GPR_EQ(x1, 0x80001A18)
    RVTEST_IO_ASSERT_GPR_EQ(x2, 0x0000ABD2)
    RVTEST_IO_ASSERT_GPR_EQ(x3, 0x0000ABD3)
 
    RVTEST_IO_WRITE_STR("# Test part B  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part C - testing writing to x0\n");
 
    # Addresses for test data and results
    la      x1, test_C_data
    la      x2, test_C_res
 
    # Load testdata
    lw      x28, 0(x1)
 
    # Register initialization
    li      x27, 0xF7FF8818
 
    # Test
    add     x0, x28, x27
 
    # store results
    sw      x0, 0(x2)
 
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
 
    RVTEST_IO_WRITE_STR("# Test part C  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part D - testing forwarding throught x0\n");
 
    # Addresses for test data and results
    la      x1, test_D_data
    la      x2, test_D_res
 
    # Load testdata
    lw      x28, 0(x1)
 
    # Register initialization
    li      x27, 0xF7FF8818
 
    # Test
    add     x0, x28, x27
    add     x5, x0, x0
 
    # store results
    sw      x0, 0(x2)
    sw      x5, 4(x2)
 
 
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    RVTEST_IO_ASSERT_GPR_EQ(x5, 0x00000000)
 
    RVTEST_IO_WRITE_STR("# Test part D  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part E - testing moving (add with x0)\n");
 
    # Addresses for test data and results
    la      x1, test_E_data
    la      x2, test_E_res
 
    # Load testdata
    lw      x3, 0(x1)
 
    # Test
    add     x4, x3, x0
    add     x5, x4, x0
    add     x6, x0, x5
    add     x14, x6, x0
    add     x15, x14, x0
    add     x16, x15, x0
    add     x25, x0, x16
    add     x26, x0, x25
    add     x27, x26, x0
 
    # Store results
    sw      x4, 0(x2)
    sw      x26, 4(x2)
    sw      x27, 8(x2)
 
    RVTEST_IO_ASSERT_GPR_EQ(x4, 0x36925814)
    RVTEST_IO_ASSERT_GPR_EQ(x26, 0x36925814)
    RVTEST_IO_ASSERT_GPR_EQ(x27, 0x36925814)
 
    RVTEST_IO_WRITE_STR("# Test part E  - Complete\n");
 
    RVTEST_IO_WRITE_STR("# Test End\n")
 
 # ---------------------------------------------------------------------------------------------
    # HALT
    RV_COMPLIANCE_HALT
 
RV_COMPLIANCE_CODE_END
 
# Input data section.
    .data
 
test_A1_data:
    .word 0
test_A2_data:
    .word 1
test_A3_data:
    .word -1
test_A4_data:
    .word 0x7FFFFFFF
test_A5_data:
    .word 0x80000000
test_B_data:
    .word 0x0000ABCD
test_C_data:
    .word 0x12345678
test_D_data:
    .word 0xFEDCBA98
test_E_data:
    .word 0x36925814
 
# Output data section.
RV_COMPLIANCE_DATA_BEGIN
 
test_A1_res:
    .fill 6, 4, -1
test_A2_res:
    .fill 6, 4, -1
test_A3_res:
    .fill 6, 4, -1
test_A4_res:
    .fill 6, 4, -1
test_A5_res:
    .fill 6, 4, -1
test_B_res:
    .fill 8, 4, -1
test_C_res:
    .fill 1, 4, -1
test_D_res:
    .fill 2, 4, -1
test_E_res:
    .fill 3, 4, -1
 
RV_COMPLIANCE_DATA_END

Browse

Tools

Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-ADD-01.S] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	mballance	`# RISC-V Compliance Test I-ADD-01`
2			`#`
3			`# Copyright (c) 2017, Codasip Ltd.`
4			`# Copyright (c) 2018, Imperas Software Ltd. Additions`
5			`# All rights reserved.`
6			`#`
7			`# Redistribution and use in source and binary forms, with or without`
8			`# modification, are permitted provided that the following conditions are met:`
9			`# * Redistributions of source code must retain the above copyright`
10			`# notice, this list of conditions and the following disclaimer.`
11			`# * Redistributions in binary form must reproduce the above copyright`
12			`# notice, this list of conditions and the following disclaimer in the`
13			`# documentation and/or other materials provided with the distribution.`
14			`# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the`
15			`# names of its contributors may be used to endorse or promote products`
16			`# derived from this software without specific prior written permission.`
17			`#`
18			`# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS`
19			`# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
20			`# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR`
21			`# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.`
22			`# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
23			`# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;`
24			`# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND`
25			`# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT`
26			`# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF`
27			`# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
28			`#`
29			`# Specification: RV32I Base Integer Instruction Set, Version 2.0`
30			`# Description: Testing instruction ADD.`
31
32			`#include "compliance_test.h"`
33			`#include "compliance_io.h"`
34			`#include "test_macros.h"`
35
36			`# Test Virtual Machine (TVM) used by program.`
37			`RV_COMPLIANCE_RV32M`
38
39			`# Test code region.`
40			`RV_COMPLIANCE_CODE_BEGIN`
41
42			`RVTEST_IO_INIT`
43			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
44			`RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")`
45
46			`# ---------------------------------------------------------------------------------------------`
47			`RVTEST_IO_WRITE_STR("# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n");`
48
49			`# Addresses for test data and results`
50			`la x1, test_A1_data`
51			`la x2, test_A1_res`
52
53			`# Load testdata`
54			`lw x3, 0(x1)`
55
56			`# Register initialization`
57			`li x4, 0`
58			`li x5, 1`
59			`li x6, -1`
60			`li x7, 0x7FFFFFFF`
61			`li x8, 0x80000000`
62
63			`# Test`
64			`add x4, x3, x4`
65			`add x5, x3, x5`
66			`add x6, x3, x6`
67			`add x7, x3, x7`
68			`add x8, x3, x8`
69
70			`# Store results`
71			`sw x3, 0(x2)`
72			`sw x4, 4(x2)`
73			`sw x5, 8(x2)`
74			`sw x6, 12(x2)`
75			`sw x7, 16(x2)`
76			`sw x8, 20(x2)`
77
78			`//`
79			`// Assert`
80			`//`
81			`RVTEST_IO_CHECK()`
82			`RVTEST_IO_ASSERT_GPR_EQ(x3, 0x00000000)`
83			`RVTEST_IO_ASSERT_GPR_EQ(x4, 0x00000000)`
84			`RVTEST_IO_ASSERT_GPR_EQ(x5, 0x00000000)`
85			`RVTEST_IO_ASSERT_GPR_EQ(x6, 0xFFFFFFFF)`
86			`RVTEST_IO_ASSERT_GPR_EQ(x7, 0x7FFFFFFF)`
87			`RVTEST_IO_ASSERT_GPR_EQ(x8, 0x80000000)`
88
89			`RVTEST_IO_WRITE_STR("# Test part A1 - Complete\n");`
90
91			`# ---------------------------------------------------------------------------------------------`
92			`RVTEST_IO_WRITE_STR("# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n");`
93
94			`# Addresses for test data and results`
95			`la x1, test_A2_data`
96			`la x2, test_A2_res`
97
98			`# Load testdata`
99			`lw x8, 0(x1)`
100
101			`# Register initialization`
102			`li x9, 0`
103			`li x10, 1`
104			`li x11, -1`
105			`li x12, 0x7FFFFFFF`
106			`li x13, 0x80000000`
107
108			`# Test`
109			`add x9, x8, x9`
110			`add x10, x8, x10`
111			`add x11, x8, x11`
112			`add x12, x8, x12`
113			`add x13, x8, x13`
114
115			`# Store results`
116			`sw x8, 0(x2)`
117			`sw x9, 4(x2)`
118			`sw x10, 8(x2)`
119			`sw x11, 12(x2)`
120			`sw x12, 16(x2)`
121			`sw x13, 20(x2)`
122
123			`RVTEST_IO_ASSERT_GPR_EQ(x8, 0x00000001)`
124			`RVTEST_IO_ASSERT_GPR_EQ(x9, 0x00000001)`
125			`#RVTEST_IO_ASSERT_GPR_EQ(x10, 0x00000000)`
126			`RVTEST_IO_ASSERT_GPR_EQ(x11, 0x00000000)`
127			`RVTEST_IO_ASSERT_GPR_EQ(x12, 0x80000000)`
128			`RVTEST_IO_ASSERT_GPR_EQ(x13, 0x80000001)`
129
130			`RVTEST_IO_WRITE_STR("# Test part A2 - Complete\n");`
131
132			`# ---------------------------------------------------------------------------------------------`
133			`RVTEST_IO_WRITE_STR("# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n");`
134
135			`# Addresses for test data and results`
136			`la x1, test_A3_data`
137			`la x2, test_A3_res`
138
139			`# Load testdata`
140			`lw x13, 0(x1)`
141
142			`# Register initialization`
143			`li x14, 0`
144			`li x15, 1`
145			`li x16, -1`
146			`li x17, 0x7FFFFFFF`
147			`li x18, 0x80000000`
148
149			`# Test`
150			`add x14, x13, x14`
151			`add x15, x13, x15`
152			`add x16, x13, x16`
153			`add x17, x13, x17`
154			`add x18, x13, x18`
155
156			`# Store results`
157			`sw x13, 0(x2)`
158			`sw x14, 4(x2)`
159			`sw x15, 8(x2)`
160			`sw x16, 12(x2)`
161			`sw x17, 16(x2)`
162			`sw x18, 20(x2)`
163
164			`RVTEST_IO_ASSERT_GPR_EQ(x13, 0xFFFFFFFF)`
165			`RVTEST_IO_ASSERT_GPR_EQ(x14, 0xFFFFFFFF)`
166			`RVTEST_IO_ASSERT_GPR_EQ(x15, 0x00000000)`
167			`RVTEST_IO_ASSERT_GPR_EQ(x16, 0xFFFFFFFE)`
168			`RVTEST_IO_ASSERT_GPR_EQ(x17, 0x7FFFFFFE)`
169			`RVTEST_IO_ASSERT_GPR_EQ(x18, 0x7FFFFFFF)`
170
171			`RVTEST_IO_WRITE_STR("# Test part A3 - Complete\n");`
172
173			`# ---------------------------------------------------------------------------------------------`
174			`RVTEST_IO_WRITE_STR("# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n");`
175
176			`# Addresses for test data and results`
177			`la x1, test_A4_data`
178			`la x2, test_A4_res`
179
180			`# Load testdata`
181			`lw x18, 0(x1)`
182
183			`# Register initialization`
184			`li x19, 0`
185			`li x20, 1`
186			`li x21, -1`
187			`li x22, 0x7FFFFFFF`
188			`li x23, 0x80000000`
189
190			`# Test execution`
191			`add x19, x18, x19`
192			`add x20, x18, x20`
193			`add x21, x18, x21`
194			`add x22, x18, x22`
195			`add x23, x18, x23`
196
197			`# Store results`
198			`sw x18, 0(x2)`
199			`sw x19, 4(x2)`
200			`sw x20, 8(x2)`
201			`sw x21, 12(x2)`
202			`sw x22, 16(x2)`
203			`sw x23, 20(x2)`
204
205			`RVTEST_IO_ASSERT_GPR_EQ(x18, 0x7FFFFFFF)`
206			`RVTEST_IO_ASSERT_GPR_EQ(x19, 0x7FFFFFFF)`
207			`RVTEST_IO_ASSERT_GPR_EQ(x20, 0x80000000)`
208			`RVTEST_IO_ASSERT_GPR_EQ(x21, 0x7FFFFFFE)`
209			`RVTEST_IO_ASSERT_GPR_EQ(x22, 0xFFFFFFFE)`
210			`RVTEST_IO_ASSERT_GPR_EQ(x23, 0xFFFFFFFF)`
211
212			`RVTEST_IO_WRITE_STR("# Test part A4 - Complete\n");`
213
214			`# ---------------------------------------------------------------------------------------------`
215			`RVTEST_IO_WRITE_STR("# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n");`
216
217			`# Addresses for test data and results`
218			`la x1, test_A5_data`
219			`la x2, test_A5_res`
220
221			`# Load testdata`
222			`lw x23, 0(x1)`
223
224			`# Register initialization`
225			`li x24, 0`
226			`li x25, 1`
227			`li x26, -1`
228			`li x27, 0x7FFFFFFF`
229			`li x28, 0x80000000`
230
231			`# Test`
232			`add x24, x23, x24`
233			`add x25, x23, x25`
234			`add x26, x23, x26`
235			`add x27, x23, x27`
236			`add x28, x23, x28`
237
238			`# Store results`
239			`sw x23, 0(x2)`
240			`sw x24, 4(x2)`
241			`sw x25, 8(x2)`
242			`sw x26, 12(x2)`
243			`sw x27, 16(x2)`
244			`sw x28, 20(x2)`
245
246			`RVTEST_IO_ASSERT_GPR_EQ(x23, 0x80000000)`
247			`RVTEST_IO_ASSERT_GPR_EQ(x24, 0x80000000)`
248			`RVTEST_IO_ASSERT_GPR_EQ(x25, 0x80000001)`
249			`RVTEST_IO_ASSERT_GPR_EQ(x26, 0x7FFFFFFF)`
250			`RVTEST_IO_ASSERT_GPR_EQ(x27, 0xFFFFFFFF)`
251			`RVTEST_IO_ASSERT_GPR_EQ(x28, 0x00000000)`
252
253			`RVTEST_IO_WRITE_STR("# Test part A5 - Complete\n");`
254
255			`# ---------------------------------------------------------------------------------------------`
256			`RVTEST_IO_WRITE_STR("# Test part B - testing forwarding between instructions\n");`
257
258			`# Addresses for test data and results`
259			`la x25, test_B_data`
260			`la x26, test_B_res`
261
262			`# Load testdata`
263			`lw x28, 0(x25)`
264
265			`# Register initialization`
266			`li x27, 0x1`
267
268			`# Test`
269			`add x29, x28, x27`
270			`add x30, x29, x27`
271			`add x31, x30, x27`
272			`add x1, x31, x27`
273			`add x2, x1, x27`
274			`add x3, x2, x27`
275
276			`# store results`
277			`sw x27, 0(x26)`
278			`sw x28, 4(x26)`
279			`sw x29, 8(x26)`
280			`sw x30, 12(x26)`
281			`sw x31, 16(x26)`
282			`sw x1, 20(x26)`
283			`sw x2, 24(x26)`
284			`sw x3, 28(x26)`
285
286			`RVTEST_IO_ASSERT_GPR_EQ(x27, 0x00000001)`
287			`RVTEST_IO_ASSERT_GPR_EQ(x28, 0x0000ABCD)`
288			`RVTEST_IO_ASSERT_GPR_EQ(x29, 0x0000ABCE)`
289			`RVTEST_IO_ASSERT_GPR_EQ(x30, 0x0000ABCF)`
290			`RVTEST_IO_ASSERT_GPR_EQ(x31, 0x0000ABD0)`
291			`#RVTEST_IO_ASSERT_GPR_EQ(x1, 0x80001A18)`
292			`RVTEST_IO_ASSERT_GPR_EQ(x2, 0x0000ABD2)`
293			`RVTEST_IO_ASSERT_GPR_EQ(x3, 0x0000ABD3)`
294
295			`RVTEST_IO_WRITE_STR("# Test part B - Complete\n");`
296
297			`# ---------------------------------------------------------------------------------------------`
298			`RVTEST_IO_WRITE_STR("# Test part C - testing writing to x0\n");`
299
300			`# Addresses for test data and results`
301			`la x1, test_C_data`
302			`la x2, test_C_res`
303
304			`# Load testdata`
305			`lw x28, 0(x1)`
306
307			`# Register initialization`
308			`li x27, 0xF7FF8818`
309
310			`# Test`
311			`add x0, x28, x27`
312
313			`# store results`
314			`sw x0, 0(x2)`
315
316			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
317
318			`RVTEST_IO_WRITE_STR("# Test part C - Complete\n");`
319
320			`# ---------------------------------------------------------------------------------------------`
321			`RVTEST_IO_WRITE_STR("# Test part D - testing forwarding throught x0\n");`
322
323			`# Addresses for test data and results`
324			`la x1, test_D_data`
325			`la x2, test_D_res`
326
327			`# Load testdata`
328			`lw x28, 0(x1)`
329
330			`# Register initialization`
331			`li x27, 0xF7FF8818`
332
333			`# Test`
334			`add x0, x28, x27`
335			`add x5, x0, x0`
336
337			`# store results`
338			`sw x0, 0(x2)`
339			`sw x5, 4(x2)`
340
341
342			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
343			`RVTEST_IO_ASSERT_GPR_EQ(x5, 0x00000000)`
344
345			`RVTEST_IO_WRITE_STR("# Test part D - Complete\n");`
346
347			`# ---------------------------------------------------------------------------------------------`
348			`RVTEST_IO_WRITE_STR("# Test part E - testing moving (add with x0)\n");`
349
350			`# Addresses for test data and results`
351			`la x1, test_E_data`
352			`la x2, test_E_res`
353
354			`# Load testdata`
355			`lw x3, 0(x1)`
356
357			`# Test`
358			`add x4, x3, x0`
359			`add x5, x4, x0`
360			`add x6, x0, x5`
361			`add x14, x6, x0`
362			`add x15, x14, x0`
363			`add x16, x15, x0`
364			`add x25, x0, x16`
365			`add x26, x0, x25`
366			`add x27, x26, x0`
367
368			`# Store results`
369			`sw x4, 0(x2)`
370			`sw x26, 4(x2)`
371			`sw x27, 8(x2)`
372
373			`RVTEST_IO_ASSERT_GPR_EQ(x4, 0x36925814)`
374			`RVTEST_IO_ASSERT_GPR_EQ(x26, 0x36925814)`
375			`RVTEST_IO_ASSERT_GPR_EQ(x27, 0x36925814)`
376
377			`RVTEST_IO_WRITE_STR("# Test part E - Complete\n");`
378
379			`RVTEST_IO_WRITE_STR("# Test End\n")`
380
381			`# ---------------------------------------------------------------------------------------------`
382			`# HALT`
383			`RV_COMPLIANCE_HALT`
384
385			`RV_COMPLIANCE_CODE_END`
386
387			`# Input data section.`
388			`.data`
389
390			`test_A1_data:`
391			`.word 0`
392			`test_A2_data:`
393			`.word 1`
394			`test_A3_data:`
395			`.word -1`
396			`test_A4_data:`
397			`.word 0x7FFFFFFF`
398			`test_A5_data:`
399			`.word 0x80000000`
400			`test_B_data:`
401			`.word 0x0000ABCD`
402			`test_C_data:`
403			`.word 0x12345678`
404			`test_D_data:`
405			`.word 0xFEDCBA98`
406			`test_E_data:`
407			`.word 0x36925814`
408
409			`# Output data section.`
410			`RV_COMPLIANCE_DATA_BEGIN`
411
412			`test_A1_res:`
413			`.fill 6, 4, -1`
414			`test_A2_res:`
415			`.fill 6, 4, -1`
416			`test_A3_res:`
417			`.fill 6, 4, -1`
418			`test_A4_res:`
419			`.fill 6, 4, -1`
420			`test_A5_res:`
421			`.fill 6, 4, -1`
422			`test_B_res:`
423			`.fill 8, 4, -1`
424			`test_C_res:`
425			`.fill 1, 4, -1`
426			`test_D_res:`
427			`.fill 2, 4, -1`
428			`test_E_res:`
429			`.fill 3, 4, -1`
430
431			`RV_COMPLIANCE_DATA_END`