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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-MISALIGN_JMP-01.S] - Blame information for rev 2

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# RISC-V Compliance Test I-MISALIGN_JMP-01
#
# Copyright (c) 2017, Codasip Ltd.
# Copyright (c) 2018, Imperas Software Ltd. Additions
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#      * Redistributions of source code must retain the above copyright
#        notice, this list of conditions and the following disclaimer.
#      * Redistributions in binary form must reproduce the above copyright
#        notice, this list of conditions and the following disclaimer in the
#        documentation and/or other materials provided with the distribution.
#      * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the
#        names of its contributors may be used to endorse or promote products
#        derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.
# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Specification: RV32I Base Integer Instruction Set, Version 2.0
# Description: Testing MISALIGNED JUMP exception.
 
#include "compliance_test.h"
#include "compliance_io.h"
#include "test_macros.h"
 
# Test Virtual Machine (TVM) used by program.
RV_COMPLIANCE_RV32M
 
# Test code region
RV_COMPLIANCE_CODE_BEGIN
 
    RVTEST_IO_INIT
    RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)
    RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")
 
    # Save and set trap handler address
    la x1, _trap_handler
    csrrw x31, mtvec, x1
 
    # switch off C
    csrrci   x0, misa, 4
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A1 - test JAL\n");
 
    # Address for test results
    la      x1, test_A1_res_exc
 
    # Test
    li      x2, 0x11111111
    jal     x0, 1f + 2
    li      x2, 0
1:
 
    //
    // Assert
    //
    RVTEST_IO_CHECK()
    RVTEST_IO_WRITE_STR("# Test part A1  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A2 - test JALR - NOT causing the exception\n");
 
    # Address for test results
    la      x1, test_A2_res
 
    # Test
    li      x2, 0x22222222
    la      x4, 1f + 1
    jalr    x0, x4, 0
    li      x2, 0
1:
    sw      x2, 0(x1)
    addi    x1, x1, 4
 
    li      x2, 0x33333333
    la      x4, 1f
    jalr    x0, x4, 1
    li      x2, 0
1:
    sw      x2, 0(x1)
    addi    x1, x1, 4
 
    li      x2, 0x44444444
    la      x4, 1f
    jalr    x0, x4, -3
    li      x2, 0
 
    sw      x2, 0(x1)
1:
    addi    x1, x1, 4
 
    RVTEST_IO_WRITE_STR("# Test part A2  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part A3 - test JALR - causing the exception\n");
 
    # Address for test results
    la      x1, test_A3_res_exc
 
    # Test
    li      x2, 0x55555555
    la      x4, 1f + 2
    jalr    x0, x4, 0
    li      x2, 0
1:
 
    li      x2, 0x66666666
    la      x4, 1f + 3
    jalr    x0, x4, 0
    li      x2, 0
1:
 
    # Test
    li      x2, 0x77777777
    la      x4, 1f
    jalr    x0, x4, 2
    li      x2, 0
1:
 
    li      x2, 0x88888888
    la      x4, 1f
    jalr    x0, x4, 3
    li      x2, 0
1:
 
    RVTEST_IO_WRITE_STR("# Test part A3  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part B1 - test BEQ\n");
 
    # Address for test results
    la      x1, test_B1_res_exc
 
    # Register initialization
    li      x5, 5
    li      x6, 6
 
    # Test
    beq     x5, x6, 1f + 2
    li      x2, 0x99999999
1:
    nop
    nop
    beq     x5, x5, 1f + 2
    li      x2, 0
1:
 
    RVTEST_IO_WRITE_STR("# Test part A4  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part B2 - test BNE\n");
 
    # Address for test results
    la      x1, test_B2_res_exc
 
    # Register initialization
    li      x5, 5
    li      x6, 6
 
    # Test
    bne     x5, x5, 1f + 2
    li      x2, 0xAAAAAAAA
1:
    nop
    nop
    bne     x5, x6, 1f + 2
    li      x2, 0
1:
 
    RVTEST_IO_WRITE_STR("# Test part A5  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part B3 - test BLT\n");
 
    # Address for test results
    la      x1, test_B3_res_exc
 
    # Register initialization
    li      x5, 5
    li      x6, 6
 
    # Test
    blt     x6, x5, 1f + 2
    li      x2, 0xBBBBBBBB
1:
    nop
    nop
    blt     x5, x6, 1f + 2
    li      x2, 0
1:
 
    RVTEST_IO_WRITE_STR("# Test part B  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part B4 - test BLTU\n");
 
    # Address for test results
    la      x1, test_B4_res_exc
 
    # Register initialization
    li      x5, 5
    li      x6, 6
 
    # Test
    bltu    x6, x5, 1f + 2
    li      x2, 0xCCCCCCCC
1:
    nop
    nop
    bltu    x5, x6, 1f + 2
    li      x2, 0
1:
 
    RVTEST_IO_WRITE_STR("# Test part C  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part B5 - test BGE\n");
 
    # Address for test results
    la      x1, test_B5_res_exc
 
    # Register initialization
    li      x5, 5
    li      x6, 6
 
    # Test
    bge     x5, x6, 1f + 2
    li      x2, 0xDDDDDDDD
1:
    nop
    nop
    bge     x6, x5, 1f + 2
    li      x2, 0
1:
 
    RVTEST_IO_WRITE_STR("# Test part D  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    RVTEST_IO_WRITE_STR("# Test part B6 - test BGEU\n");
 
    # Address for test results
    la      x1, test_B6_res_exc
 
    # Register initialization
    li      x5, 5
    li      x6, 6
 
    # Test
    bgeu    x5, x6, 1f + 2
    li      x2, 0xEEEEEEEE
1:
    nop
    nop
    bgeu    x6, x5, 1f + 2
    li      x2, 0
1:
 
    RVTEST_IO_WRITE_STR("# Test part E  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    # restore mtvec and jump to the end
    csrw mtvec, x31
    jal x0, test_end
 
    RVTEST_IO_WRITE_STR("# Test part A1  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
    # Exception handler
_trap_handler:
    # increment return address
    csrr    x30, mbadaddr
    addi    x30, x30, -2
    csrw    mepc, x30
 
    # store low bits of MBADADDR
    csrr    x30, mbadaddr
    andi    x30, x30, 3
    sw      x30, 0(x1)
 
    # Store MCAUSE
    csrr    x30, mcause
    sw      x30, 4(x1)
 
    # Store data from test
    sw      x2, 8(x1)
 
    # increment data_exc address
    addi    x1, x1, 12
 
    # return
    mret
    RVTEST_IO_WRITE_STR("# Test part A2  - Complete\n");
 
    # ---------------------------------------------------------------------------------------------
 
test_end:
    RVTEST_IO_WRITE_STR("# Test part A3  - Complete\n");
 
    RVTEST_IO_WRITE_STR("# Test End\n")
 
 # ---------------------------------------------------------------------------------------------
    # HALT
    RV_COMPLIANCE_HALT
 
RV_COMPLIANCE_CODE_END
 
# Input data section.
    .data
    .align 4
 
 
# Output data section.
RV_COMPLIANCE_DATA_BEGIN
    .align 4
 
test_A1_res_exc:
    .fill 3, 4, -1
test_A2_res:
    .fill 3, 4, -1
test_A3_res_exc:
    .fill 12, 4, -1
test_B1_res_exc:
    .fill 3, 4, -1
test_B2_res_exc:
    .fill 3, 4, -1
test_B3_res_exc:
    .fill 3, 4, -1
test_B4_res_exc:
    .fill 3, 4, -1
test_B5_res_exc:
    .fill 3, 4, -1
test_B6_res_exc:
    .fill 3, 4, -1
 
RV_COMPLIANCE_DATA_END

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Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32i/] [src/] [I-MISALIGN_JMP-01.S] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	mballance	`# RISC-V Compliance Test I-MISALIGN_JMP-01`
2			`#`
3			`# Copyright (c) 2017, Codasip Ltd.`
4			`# Copyright (c) 2018, Imperas Software Ltd. Additions`
5			`# All rights reserved.`
6			`#`
7			`# Redistribution and use in source and binary forms, with or without`
8			`# modification, are permitted provided that the following conditions are met:`
9			`# * Redistributions of source code must retain the above copyright`
10			`# notice, this list of conditions and the following disclaimer.`
11			`# * Redistributions in binary form must reproduce the above copyright`
12			`# notice, this list of conditions and the following disclaimer in the`
13			`# documentation and/or other materials provided with the distribution.`
14			`# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the`
15			`# names of its contributors may be used to endorse or promote products`
16			`# derived from this software without specific prior written permission.`
17			`#`
18			`# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS`
19			`# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
20			`# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR`
21			`# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd.`
22			`# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
23			`# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;`
24			`# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND`
25			`# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT`
26			`# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF`
27			`# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
28			`#`
29			`# Specification: RV32I Base Integer Instruction Set, Version 2.0`
30			`# Description: Testing MISALIGNED JUMP exception.`
31
32			`#include "compliance_test.h"`
33			`#include "compliance_io.h"`
34			`#include "test_macros.h"`
35
36			`# Test Virtual Machine (TVM) used by program.`
37			`RV_COMPLIANCE_RV32M`
38
39			`# Test code region`
40			`RV_COMPLIANCE_CODE_BEGIN`
41
42			`RVTEST_IO_INIT`
43			`RVTEST_IO_ASSERT_GPR_EQ(x0, 0x00000000)`
44			`RVTEST_IO_WRITE_STR("# Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n")`
45
46			`# Save and set trap handler address`
47			`la x1, _trap_handler`
48			`csrrw x31, mtvec, x1`
49
50			`# switch off C`
51			`csrrci x0, misa, 4`
52
53			`# ---------------------------------------------------------------------------------------------`
54			`RVTEST_IO_WRITE_STR("# Test part A1 - test JAL\n");`
55
56			`# Address for test results`
57			`la x1, test_A1_res_exc`
58
59			`# Test`
60			`li x2, 0x11111111`
61			`jal x0, 1f + 2`
62			`li x2, 0`
63			`1:`
64
65			`//`
66			`// Assert`
67			`//`
68			`RVTEST_IO_CHECK()`
69			`RVTEST_IO_WRITE_STR("# Test part A1 - Complete\n");`
70
71			`# ---------------------------------------------------------------------------------------------`
72			`RVTEST_IO_WRITE_STR("# Test part A2 - test JALR - NOT causing the exception\n");`
73
74			`# Address for test results`
75			`la x1, test_A2_res`
76
77			`# Test`
78			`li x2, 0x22222222`
79			`la x4, 1f + 1`
80			`jalr x0, x4, 0`
81			`li x2, 0`
82			`1:`
83			`sw x2, 0(x1)`
84			`addi x1, x1, 4`
85
86			`li x2, 0x33333333`
87			`la x4, 1f`
88			`jalr x0, x4, 1`
89			`li x2, 0`
90			`1:`
91			`sw x2, 0(x1)`
92			`addi x1, x1, 4`
93
94			`li x2, 0x44444444`
95			`la x4, 1f`
96			`jalr x0, x4, -3`
97			`li x2, 0`
98
99			`sw x2, 0(x1)`
100			`1:`
101			`addi x1, x1, 4`
102
103			`RVTEST_IO_WRITE_STR("# Test part A2 - Complete\n");`
104
105			`# ---------------------------------------------------------------------------------------------`
106			`RVTEST_IO_WRITE_STR("# Test part A3 - test JALR - causing the exception\n");`
107
108			`# Address for test results`
109			`la x1, test_A3_res_exc`
110
111			`# Test`
112			`li x2, 0x55555555`
113			`la x4, 1f + 2`
114			`jalr x0, x4, 0`
115			`li x2, 0`
116			`1:`
117
118			`li x2, 0x66666666`
119			`la x4, 1f + 3`
120			`jalr x0, x4, 0`
121			`li x2, 0`
122			`1:`
123
124			`# Test`
125			`li x2, 0x77777777`
126			`la x4, 1f`
127			`jalr x0, x4, 2`
128			`li x2, 0`
129			`1:`
130
131			`li x2, 0x88888888`
132			`la x4, 1f`
133			`jalr x0, x4, 3`
134			`li x2, 0`
135			`1:`
136
137			`RVTEST_IO_WRITE_STR("# Test part A3 - Complete\n");`
138
139			`# ---------------------------------------------------------------------------------------------`
140			`RVTEST_IO_WRITE_STR("# Test part B1 - test BEQ\n");`
141
142			`# Address for test results`
143			`la x1, test_B1_res_exc`
144
145			`# Register initialization`
146			`li x5, 5`
147			`li x6, 6`
148
149			`# Test`
150			`beq x5, x6, 1f + 2`
151			`li x2, 0x99999999`
152			`1:`
153			`nop`
154			`nop`
155			`beq x5, x5, 1f + 2`
156			`li x2, 0`
157			`1:`
158
159			`RVTEST_IO_WRITE_STR("# Test part A4 - Complete\n");`
160
161			`# ---------------------------------------------------------------------------------------------`
162			`RVTEST_IO_WRITE_STR("# Test part B2 - test BNE\n");`
163
164			`# Address for test results`
165			`la x1, test_B2_res_exc`
166
167			`# Register initialization`
168			`li x5, 5`
169			`li x6, 6`
170
171			`# Test`
172			`bne x5, x5, 1f + 2`
173			`li x2, 0xAAAAAAAA`
174			`1:`
175			`nop`
176			`nop`
177			`bne x5, x6, 1f + 2`
178			`li x2, 0`
179			`1:`
180
181			`RVTEST_IO_WRITE_STR("# Test part A5 - Complete\n");`
182
183			`# ---------------------------------------------------------------------------------------------`
184			`RVTEST_IO_WRITE_STR("# Test part B3 - test BLT\n");`
185
186			`# Address for test results`
187			`la x1, test_B3_res_exc`
188
189			`# Register initialization`
190			`li x5, 5`
191			`li x6, 6`
192
193			`# Test`
194			`blt x6, x5, 1f + 2`
195			`li x2, 0xBBBBBBBB`
196			`1:`
197			`nop`
198			`nop`
199			`blt x5, x6, 1f + 2`
200			`li x2, 0`
201			`1:`
202
203			`RVTEST_IO_WRITE_STR("# Test part B - Complete\n");`
204
205			`# ---------------------------------------------------------------------------------------------`
206			`RVTEST_IO_WRITE_STR("# Test part B4 - test BLTU\n");`
207
208			`# Address for test results`
209			`la x1, test_B4_res_exc`
210
211			`# Register initialization`
212			`li x5, 5`
213			`li x6, 6`
214
215			`# Test`
216			`bltu x6, x5, 1f + 2`
217			`li x2, 0xCCCCCCCC`
218			`1:`
219			`nop`
220			`nop`
221			`bltu x5, x6, 1f + 2`
222			`li x2, 0`
223			`1:`
224
225			`RVTEST_IO_WRITE_STR("# Test part C - Complete\n");`
226
227			`# ---------------------------------------------------------------------------------------------`
228			`RVTEST_IO_WRITE_STR("# Test part B5 - test BGE\n");`
229
230			`# Address for test results`
231			`la x1, test_B5_res_exc`
232
233			`# Register initialization`
234			`li x5, 5`
235			`li x6, 6`
236
237			`# Test`
238			`bge x5, x6, 1f + 2`
239			`li x2, 0xDDDDDDDD`
240			`1:`
241			`nop`
242			`nop`
243			`bge x6, x5, 1f + 2`
244			`li x2, 0`
245			`1:`
246
247			`RVTEST_IO_WRITE_STR("# Test part D - Complete\n");`
248
249			`# ---------------------------------------------------------------------------------------------`
250			`RVTEST_IO_WRITE_STR("# Test part B6 - test BGEU\n");`
251
252			`# Address for test results`
253			`la x1, test_B6_res_exc`
254
255			`# Register initialization`
256			`li x5, 5`
257			`li x6, 6`
258
259			`# Test`
260			`bgeu x5, x6, 1f + 2`
261			`li x2, 0xEEEEEEEE`
262			`1:`
263			`nop`
264			`nop`
265			`bgeu x6, x5, 1f + 2`
266			`li x2, 0`
267			`1:`
268
269			`RVTEST_IO_WRITE_STR("# Test part E - Complete\n");`
270
271			`# ---------------------------------------------------------------------------------------------`
272			`# restore mtvec and jump to the end`
273			`csrw mtvec, x31`
274			`jal x0, test_end`
275
276			`RVTEST_IO_WRITE_STR("# Test part A1 - Complete\n");`
277
278			`# ---------------------------------------------------------------------------------------------`
279			`# Exception handler`
280			`_trap_handler:`
281			`# increment return address`
282			`csrr x30, mbadaddr`
283			`addi x30, x30, -2`
284			`csrw mepc, x30`
285
286			`# store low bits of MBADADDR`
287			`csrr x30, mbadaddr`
288			`andi x30, x30, 3`
289			`sw x30, 0(x1)`
290
291			`# Store MCAUSE`
292			`csrr x30, mcause`
293			`sw x30, 4(x1)`
294
295			`# Store data from test`
296			`sw x2, 8(x1)`
297
298			`# increment data_exc address`
299			`addi x1, x1, 12`
300
301			`# return`
302			`mret`
303			`RVTEST_IO_WRITE_STR("# Test part A2 - Complete\n");`
304
305			`# ---------------------------------------------------------------------------------------------`
306
307			`test_end:`
308			`RVTEST_IO_WRITE_STR("# Test part A3 - Complete\n");`
309
310			`RVTEST_IO_WRITE_STR("# Test End\n")`
311
312			`# ---------------------------------------------------------------------------------------------`
313			`# HALT`
314			`RV_COMPLIANCE_HALT`
315
316			`RV_COMPLIANCE_CODE_END`
317
318			`# Input data section.`
319			`.data`
320			`.align 4`
321
322
323			`# Output data section.`
324			`RV_COMPLIANCE_DATA_BEGIN`
325			`.align 4`
326
327			`test_A1_res_exc:`
328			`.fill 3, 4, -1`
329			`test_A2_res:`
330			`.fill 3, 4, -1`
331			`test_A3_res_exc:`
332			`.fill 12, 4, -1`
333			`test_B1_res_exc:`
334			`.fill 3, 4, -1`
335			`test_B2_res_exc:`
336			`.fill 3, 4, -1`
337			`test_B3_res_exc:`
338			`.fill 3, 4, -1`
339			`test_B4_res_exc:`
340			`.fill 3, 4, -1`
341			`test_B5_res_exc:`
342			`.fill 3, 4, -1`
343			`test_B6_res_exc:`
344			`.fill 3, 4, -1`
345
346			`RV_COMPLIANCE_DATA_END`