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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32mi/] [rv64mi/] [ma_addr.S] - Blame information for rev 2

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# See LICENSE for license details.
 
#*****************************************************************************
# ma_addr.S
#-----------------------------------------------------------------------------
#
# Test misaligned ld/st trap.
#
 
#include "riscv_test.h"
#include "compliance_test.h"
#include "compliance_io.h"
#include "aw_test_macros.h"
 
 
RVTEST_RV64M
RVTEST_CODE_BEGIN
 
  .align 2
  .option norvc
 
  la s0, data
 
  # indicate it's a load test
  li s1, CAUSE_MISALIGNED_LOAD
 
#define SEXT(x, n) ((-((x) >> ((n)-1)) << (n)) | ((x) & ((1 << (n))-1)))
 
/* Check that a misaligned load either writes the correct value, or
   takes an exception and performs no writeback.  */
#define MISALIGNED_LOAD_TEST(testnum, insn, base, offset, res) \
  li TESTNUM, testnum; \
  SWSIG(testnum, TESTNUM) \
  la t2, 1f; \
  addi t1, base, offset; \
  insn t1, offset(base); \
  li t2, res; \
  bne t1, t2, fail; \
1:
 
  MISALIGNED_LOAD_TEST(2,  lh,  s0, 1, SEXT(0xbbcc, 16))
  MISALIGNED_LOAD_TEST(3,  lhu, s0, 1, 0xbbcc)
  MISALIGNED_LOAD_TEST(4,  lw,  s0, 1, SEXT(0x99aabbcc, 32))
  MISALIGNED_LOAD_TEST(5,  lw,  s0, 2, SEXT(0x8899aabb, 32))
  MISALIGNED_LOAD_TEST(6,  lw,  s0, 3, SEXT(0x778899aa, 32))
 
#if __riscv_xlen == 64
  MISALIGNED_LOAD_TEST(7,  lwu, s0, 1, 0x99aabbcc)
  MISALIGNED_LOAD_TEST(8,  lwu, s0, 2, 0x8899aabb)
  MISALIGNED_LOAD_TEST(9,  lwu, s0, 3, 0x778899aa)
 
  MISALIGNED_LOAD_TEST(10, ld, s0, 1, 0x5566778899aabbcc)
  MISALIGNED_LOAD_TEST(11, ld, s0, 2, 0x445566778899aabb)
  MISALIGNED_LOAD_TEST(12, ld, s0, 3, 0x33445566778899aa)
  MISALIGNED_LOAD_TEST(13, ld, s0, 4, 0x2233445566778899)
  MISALIGNED_LOAD_TEST(14, ld, s0, 5, 0x1122334455667788)
  MISALIGNED_LOAD_TEST(15, ld, s0, 6, 0xee11223344556677)
  MISALIGNED_LOAD_TEST(16, ld, s0, 7, 0xffee112233445566)
#endif
 
  # indicate it's a store test
  li s1, CAUSE_MISALIGNED_STORE
 
/* Check that a misaligned store has some effect and takes no exception,
   or takes no effect and generates an exception.  This is not very
   thorough.  */
#define MISALIGNED_STORE_TEST(testnum, insn, base, offset, size) \
  li TESTNUM, testnum; \
  la t2, 1f; \
  addi t1, base, offset; \
  insn x0, offset(base); \
  lb t1, (offset - 1)(base); \
  beqz t1, fail; \
  lb t1, (offset + size)(base); \
  beqz t1, fail; \
  lb t1, (offset + 0)(base); \
  bnez t1, fail; \
  lb t1, (offset + size - 1)(base); \
  bnez t1, fail; \
1:
 
  MISALIGNED_STORE_TEST(22,  sh,  s0, 1, 2)
  MISALIGNED_STORE_TEST(23,  sw,  s0, 5, 4)
  MISALIGNED_STORE_TEST(24,  sw,  s0, 10, 4)
  MISALIGNED_STORE_TEST(25,  sw,  s0, 15, 4)
 
#if __riscv_xlen == 64
  MISALIGNED_STORE_TEST(26, sd, s0, 25, 8)
  MISALIGNED_STORE_TEST(27, sd, s0, 34, 8)
  MISALIGNED_STORE_TEST(28, sd, s0, 43, 8)
  MISALIGNED_STORE_TEST(29, sd, s0, 52, 8)
  MISALIGNED_STORE_TEST(30, sd, s0, 61, 8)
  MISALIGNED_STORE_TEST(31, sd, s0, 70, 8)
  MISALIGNED_STORE_TEST(32, sd, s0, 79, 8)
#endif
 
  TEST_PASSFAIL
 
  .align 3
  .global mtvec_handler
mtvec_handler:
  csrr t0, mcause
  bne t0, s1, fail
 
  csrr t0, mbadaddr
  bne t0, t1, fail
 
  lb t0, (t0)
  beqz t0, fail
 
  csrw mepc, t2
  mret
 
RVTEST_CODE_END
 
  .data
 
data:
  .align 3
.word 0xaabbccdd
.word 0x66778899
.word 0x22334455
.word 0xeeffee11
.fill 0xff, 1, 80
 
RV_COMPLIANCE_DATA_BEGIN
test_res:
    .fill 40, 4, -1
RV_COMPLIANCE_DATA_END
 

Line No.	Rev	Author	Line
1	2	mballance	`# See LICENSE for license details.`
2
3			`#*****************************************************************************`
4			`# ma_addr.S`
5			`#-----------------------------------------------------------------------------`
6			`#`
7			`# Test misaligned ld/st trap.`
8			`#`
9
10			`#include "riscv_test.h"`
11			`#include "compliance_test.h"`
12			`#include "compliance_io.h"`
13			`#include "aw_test_macros.h"`
14
15
16			`RVTEST_RV64M`
17			`RVTEST_CODE_BEGIN`
18
19			`.align 2`
20			`.option norvc`
21
22			`la s0, data`
23
24			`# indicate it's a load test`
25			`li s1, CAUSE_MISALIGNED_LOAD`
26
27			`#define SEXT(x, n) ((-((x) >> ((n)-1)) << (n)) \| ((x) & ((1 << (n))-1)))`
28
29			`/* Check that a misaligned load either writes the correct value, or`
30			`takes an exception and performs no writeback. */`
31			`#define MISALIGNED_LOAD_TEST(testnum, insn, base, offset, res) \`
32			`li TESTNUM, testnum; \`
33			`SWSIG(testnum, TESTNUM) \`
34			`la t2, 1f; \`
35			`addi t1, base, offset; \`
36			`insn t1, offset(base); \`
37			`li t2, res; \`
38			`bne t1, t2, fail; \`
39			`1:`
40
41			`MISALIGNED_LOAD_TEST(2, lh, s0, 1, SEXT(0xbbcc, 16))`
42			`MISALIGNED_LOAD_TEST(3, lhu, s0, 1, 0xbbcc)`
43			`MISALIGNED_LOAD_TEST(4, lw, s0, 1, SEXT(0x99aabbcc, 32))`
44			`MISALIGNED_LOAD_TEST(5, lw, s0, 2, SEXT(0x8899aabb, 32))`
45			`MISALIGNED_LOAD_TEST(6, lw, s0, 3, SEXT(0x778899aa, 32))`
46
47			`#if __riscv_xlen == 64`
48			`MISALIGNED_LOAD_TEST(7, lwu, s0, 1, 0x99aabbcc)`
49			`MISALIGNED_LOAD_TEST(8, lwu, s0, 2, 0x8899aabb)`
50			`MISALIGNED_LOAD_TEST(9, lwu, s0, 3, 0x778899aa)`
51
52			`MISALIGNED_LOAD_TEST(10, ld, s0, 1, 0x5566778899aabbcc)`
53			`MISALIGNED_LOAD_TEST(11, ld, s0, 2, 0x445566778899aabb)`
54			`MISALIGNED_LOAD_TEST(12, ld, s0, 3, 0x33445566778899aa)`
55			`MISALIGNED_LOAD_TEST(13, ld, s0, 4, 0x2233445566778899)`
56			`MISALIGNED_LOAD_TEST(14, ld, s0, 5, 0x1122334455667788)`
57			`MISALIGNED_LOAD_TEST(15, ld, s0, 6, 0xee11223344556677)`
58			`MISALIGNED_LOAD_TEST(16, ld, s0, 7, 0xffee112233445566)`
59			`#endif`
60
61			`# indicate it's a store test`
62			`li s1, CAUSE_MISALIGNED_STORE`
63
64			`/* Check that a misaligned store has some effect and takes no exception,`
65			`or takes no effect and generates an exception. This is not very`
66			`thorough. */`
67			`#define MISALIGNED_STORE_TEST(testnum, insn, base, offset, size) \`
68			`li TESTNUM, testnum; \`
69			`la t2, 1f; \`
70			`addi t1, base, offset; \`
71			`insn x0, offset(base); \`
72			`lb t1, (offset - 1)(base); \`
73			`beqz t1, fail; \`
74			`lb t1, (offset + size)(base); \`
75			`beqz t1, fail; \`
76			`lb t1, (offset + 0)(base); \`
77			`bnez t1, fail; \`
78			`lb t1, (offset + size - 1)(base); \`
79			`bnez t1, fail; \`
80			`1:`
81
82			`MISALIGNED_STORE_TEST(22, sh, s0, 1, 2)`
83			`MISALIGNED_STORE_TEST(23, sw, s0, 5, 4)`
84			`MISALIGNED_STORE_TEST(24, sw, s0, 10, 4)`
85			`MISALIGNED_STORE_TEST(25, sw, s0, 15, 4)`
86
87			`#if __riscv_xlen == 64`
88			`MISALIGNED_STORE_TEST(26, sd, s0, 25, 8)`
89			`MISALIGNED_STORE_TEST(27, sd, s0, 34, 8)`
90			`MISALIGNED_STORE_TEST(28, sd, s0, 43, 8)`
91			`MISALIGNED_STORE_TEST(29, sd, s0, 52, 8)`
92			`MISALIGNED_STORE_TEST(30, sd, s0, 61, 8)`
93			`MISALIGNED_STORE_TEST(31, sd, s0, 70, 8)`
94			`MISALIGNED_STORE_TEST(32, sd, s0, 79, 8)`
95			`#endif`
96
97			`TEST_PASSFAIL`
98
99			`.align 3`
100			`.global mtvec_handler`
101			`mtvec_handler:`
102			`csrr t0, mcause`
103			`bne t0, s1, fail`
104
105			`csrr t0, mbadaddr`
106			`bne t0, t1, fail`
107
108			`lb t0, (t0)`
109			`beqz t0, fail`
110
111			`csrw mepc, t2`
112			`mret`
113
114			`RVTEST_CODE_END`
115
116			`.data`
117
118			`data:`
119			`.align 3`
120			`.word 0xaabbccdd`
121			`.word 0x66778899`
122			`.word 0x22334455`
123			`.word 0xeeffee11`
124			`.fill 0xff, 1, 80`
125
126			`RV_COMPLIANCE_DATA_BEGIN`
127			`test_res:`
128			`.fill 40, 4, -1`
129			`RV_COMPLIANCE_DATA_END`
130

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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32mi/] [rv64mi/] [ma_addr.S] - Blame information for rev 2