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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32si/] [rv64si/] [dirty.S] - Blame information for rev 2

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# See LICENSE for license details.
 
#*****************************************************************************
# dirty.S
#-----------------------------------------------------------------------------
#
# Test VM referenced and dirty bits.
#
 
#include "riscv_test.h"
#include "compliance_test.h"
#include "compliance_io.h"
#include "aw_test_macros.h"
 
 
RVTEST_RV64M
RVTEST_CODE_BEGIN
 
  # Turn on VM
  li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39
  la a1, page_table_1
  srl a1, a1, RISCV_PGSHIFT
  or a1, a1, a0
  csrw sptbr, a1
  sfence.vma
 
  # Set up MPRV with MPP=S, so loads and stores use S-mode
  li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV
  csrs mstatus, a1
 
  # Try a faulting store to make sure dirty bit is not set
  li TESTNUM, 2
  li t2, 1
  sw t2, dummy - DRAM_BASE, a0
 
  # Set SUM=1 so user memory access is permitted
  li TESTNUM, 3
  li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM
  csrs mstatus, a1
 
  # Make sure SUM=1 works
  lw t0, dummy - DRAM_BASE
  bnez t0, die
 
  # Try a non-faulting store to make sure dirty bit is set
  sw t2, dummy - DRAM_BASE, a0
 
  # Make sure it succeeded
  lw t0, dummy - DRAM_BASE
  bne t0, t2, die
 
  # Leave MPRV
  li t0, MSTATUS_MPRV
  csrc mstatus, t0
 
  # Make sure D bit is set
  lw t0, page_table_1
  li a0, PTE_A | PTE_D
  and t0, t0, a0
  bne t0, a0, die
 
  # Enter MPRV again
  li t0, MSTATUS_MPRV
  csrs mstatus, t0
 
  # Make sure that superpage entries trap when PPN LSBs are set.
  li TESTNUM, 4
  lw a0, page_table_1 - DRAM_BASE
  or a0, a0, 1 << PTE_PPN_SHIFT
  sw a0, page_table_1 - DRAM_BASE, t0
  sfence.vma
  sw a0, page_table_1 - DRAM_BASE, t0
  j die
 
  RVTEST_PASS
 
  TEST_PASSFAIL
 
  .align 2
  .global mtvec_handler
mtvec_handler:
  csrr t0, mcause
  add t0, t0, -CAUSE_STORE_PAGE_FAULT
  bnez t0, die
 
  li t1, 2
  bne TESTNUM, t1, 1f
  # Make sure D bit is clear
  lw t0, page_table_1
  and t1, t0, PTE_D
  bnez t1, die
skip:
  csrr t0, mepc
  add t0, t0, 4
  csrw mepc, t0
  mret
 
1:
  li t1, 3
  bne TESTNUM, t1, 1f
  # The implementation doesn't appear to set D bits in HW.
  # Make sure the D bit really is clear.
  lw t0, page_table_1
  and t1, t0, PTE_D
  bnez t1, die
  # Set the D bit.
  or t0, t0, PTE_D
  sw t0, page_table_1, t1
  sfence.vma
  mret
 
1:
  li t1, 4
  bne TESTNUM, t1, 1f
  j pass
 
1:
die:
  RVTEST_FAIL
 
RVTEST_CODE_END
 
  .data
  TEST_DATA
 
.align 12
page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A
dummy: .dword 0
 
RV_COMPLIANCE_DATA_BEGIN
test_res:
    .fill 40, 4, -1
RV_COMPLIANCE_DATA_END
 

Line No.	Rev	Author	Line
1	2	mballance	`# See LICENSE for license details.`
2
3			`#*****************************************************************************`
4			`# dirty.S`
5			`#-----------------------------------------------------------------------------`
6			`#`
7			`# Test VM referenced and dirty bits.`
8			`#`
9
10			`#include "riscv_test.h"`
11			`#include "compliance_test.h"`
12			`#include "compliance_io.h"`
13			`#include "aw_test_macros.h"`
14
15
16			`RVTEST_RV64M`
17			`RVTEST_CODE_BEGIN`
18
19			`# Turn on VM`
20			`li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39`
21			`la a1, page_table_1`
22			`srl a1, a1, RISCV_PGSHIFT`
23			`or a1, a1, a0`
24			`csrw sptbr, a1`
25			`sfence.vma`
26
27			`# Set up MPRV with MPP=S, so loads and stores use S-mode`
28			`li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) \| MSTATUS_MPRV`
29			`csrs mstatus, a1`
30
31			`# Try a faulting store to make sure dirty bit is not set`
32			`li TESTNUM, 2`
33			`li t2, 1`
34			`sw t2, dummy - DRAM_BASE, a0`
35
36			`# Set SUM=1 so user memory access is permitted`
37			`li TESTNUM, 3`
38			`li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) \| MSTATUS_SUM`
39			`csrs mstatus, a1`
40
41			`# Make sure SUM=1 works`
42			`lw t0, dummy - DRAM_BASE`
43			`bnez t0, die`
44
45			`# Try a non-faulting store to make sure dirty bit is set`
46			`sw t2, dummy - DRAM_BASE, a0`
47
48			`# Make sure it succeeded`
49			`lw t0, dummy - DRAM_BASE`
50			`bne t0, t2, die`
51
52			`# Leave MPRV`
53			`li t0, MSTATUS_MPRV`
54			`csrc mstatus, t0`
55
56			`# Make sure D bit is set`
57			`lw t0, page_table_1`
58			`li a0, PTE_A \| PTE_D`
59			`and t0, t0, a0`
60			`bne t0, a0, die`
61
62			`# Enter MPRV again`
63			`li t0, MSTATUS_MPRV`
64			`csrs mstatus, t0`
65
66			`# Make sure that superpage entries trap when PPN LSBs are set.`
67			`li TESTNUM, 4`
68			`lw a0, page_table_1 - DRAM_BASE`
69			`or a0, a0, 1 << PTE_PPN_SHIFT`
70			`sw a0, page_table_1 - DRAM_BASE, t0`
71			`sfence.vma`
72			`sw a0, page_table_1 - DRAM_BASE, t0`
73			`j die`
74
75			`RVTEST_PASS`
76
77			`TEST_PASSFAIL`
78
79			`.align 2`
80			`.global mtvec_handler`
81			`mtvec_handler:`
82			`csrr t0, mcause`
83			`add t0, t0, -CAUSE_STORE_PAGE_FAULT`
84			`bnez t0, die`
85
86			`li t1, 2`
87			`bne TESTNUM, t1, 1f`
88			`# Make sure D bit is clear`
89			`lw t0, page_table_1`
90			`and t1, t0, PTE_D`
91			`bnez t1, die`
92			`skip:`
93			`csrr t0, mepc`
94			`add t0, t0, 4`
95			`csrw mepc, t0`
96			`mret`
97
98			`1:`
99			`li t1, 3`
100			`bne TESTNUM, t1, 1f`
101			`# The implementation doesn't appear to set D bits in HW.`
102			`# Make sure the D bit really is clear.`
103			`lw t0, page_table_1`
104			`and t1, t0, PTE_D`
105			`bnez t1, die`
106			`# Set the D bit.`
107			`or t0, t0, PTE_D`
108			`sw t0, page_table_1, t1`
109			`sfence.vma`
110			`mret`
111
112			`1:`
113			`li t1, 4`
114			`bne TESTNUM, t1, 1f`
115			`j pass`
116
117			`1:`
118			`die:`
119			`RVTEST_FAIL`
120
121			`RVTEST_CODE_END`
122
123			`.data`
124			`TEST_DATA`
125
126			`.align 12`
127			`page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) \| PTE_V \| PTE_U \| PTE_R \| PTE_W \| PTE_X \| PTE_A`
128			`dummy: .dword 0`
129
130			`RV_COMPLIANCE_DATA_BEGIN`
131			`test_res:`
132			`.fill 40, 4, -1`
133			`RV_COMPLIANCE_DATA_END`
134

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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32si/] [rv64si/] [dirty.S] - Blame information for rev 2