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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32ud/] [rv64ud/] [fcmp.S] - Blame information for rev 2

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Line No. Rev Author Line
1 2 mballance
# See LICENSE for license details.
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#*****************************************************************************
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# fcmp.S
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#-----------------------------------------------------------------------------
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#
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# Test f{eq|lt|le}.d instructions.
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#
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#include "riscv_test.h"
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#include "compliance_test.h"
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#include "compliance_io.h"
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#include "aw_test_macros.h"
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RVTEST_RV64UF
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RVTEST_CODE_BEGIN
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  #-------------------------------------------------------------
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  # Arithmetic tests
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  #-------------------------------------------------------------
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#if __riscv_xlen == 32
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    # Replace the function with the 32-bit variant defined in test_macros.h
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    #undef TEST_FP_CMP_OP_D
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    #define TEST_FP_CMP_OP_D TEST_FP_CMP_OP_D32
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#endif
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  TEST_FP_CMP_OP_D( 2, feq.d, 0x00, 1, -1.36, -1.36)
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  TEST_FP_CMP_OP_D( 3, fle.d, 0x00, 1, -1.36, -1.36)
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  TEST_FP_CMP_OP_D( 4, flt.d, 0x00, 0, -1.36, -1.36)
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  TEST_FP_CMP_OP_D( 5, feq.d, 0x00, 0, -1.37, -1.36)
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  TEST_FP_CMP_OP_D( 6, fle.d, 0x00, 1, -1.37, -1.36)
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  TEST_FP_CMP_OP_D( 7, flt.d, 0x00, 1, -1.37, -1.36)
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  # Only sNaN should signal invalid for feq.
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  TEST_FP_CMP_OP_D( 8, feq.d, 0x00, 0, NaN, 0)
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  TEST_FP_CMP_OP_D( 9, feq.d, 0x00, 0, NaN, NaN)
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  TEST_FP_CMP_OP_D(10, feq.d, 0x10, 0, sNaN, 0)
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  # qNaN should signal invalid for fle/flt.
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  TEST_FP_CMP_OP_D(11, flt.d, 0x10, 0, NaN, 0)
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  TEST_FP_CMP_OP_D(12, flt.d, 0x10, 0, NaN, NaN)
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  TEST_FP_CMP_OP_D(13, flt.d, 0x10, 0, sNaN, 0)
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  TEST_FP_CMP_OP_D(14, fle.d, 0x10, 0, NaN, 0)
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  TEST_FP_CMP_OP_D(15, fle.d, 0x10, 0, NaN, NaN)
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  TEST_FP_CMP_OP_D(16, fle.d, 0x10, 0, sNaN, 0)
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  # show finished.
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  li  TESTNUM, 17;
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  SWSIG (17, TESTNUM);
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  TEST_PASSFAIL
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RVTEST_CODE_END
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  .data
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RV_COMPLIANCE_DATA_BEGIN
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test_res:
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    .fill 40, 4, -1
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RV_COMPLIANCE_DATA_END
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