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Subversion Repositories fwrisc

[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32ui/] [rv64ui/] [beq.S] - Blame information for rev 2

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Line No.	Rev	Author	Line
1	2	mballance	`# See LICENSE for license details.`
2
3			`#*****************************************************************************`
4			`# beq.S`
5			`#-----------------------------------------------------------------------------`
6			`#`
7			`# Test beq instruction.`
8			`#`
9
10			`#include "riscv_test.h"`
11			`#include "compliance_test.h"`
12			`#include "compliance_io.h"`
13			`#include "aw_test_macros.h"`
14
15			`RVTEST_RV64U`
16			`RVTEST_CODE_BEGIN`
17
18			`#-------------------------------------------------------------`
19			`# Branch tests`
20			`#-------------------------------------------------------------`
21
22			`# Each test checks both forward and backward branches`
23
24			`TEST_BR2_OP_TAKEN( 2, beq, 0, 0 );`
25			`TEST_BR2_OP_TAKEN( 3, beq, 1, 1 );`
26			`TEST_BR2_OP_TAKEN( 4, beq, -1, -1 );`
27
28			`TEST_BR2_OP_NOTTAKEN( 5, beq, 0, 1 );`
29			`TEST_BR2_OP_NOTTAKEN( 6, beq, 1, 0 );`
30			`TEST_BR2_OP_NOTTAKEN( 7, beq, -1, 1 );`
31			`TEST_BR2_OP_NOTTAKEN( 8, beq, 1, -1 );`
32
33			`#-------------------------------------------------------------`
34			`# Bypassing tests`
35			`#-------------------------------------------------------------`
36
37			`TEST_BR2_SRC12_BYPASS( 9, 0, 0, beq, 0, -1 );`
38			`TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 );`
39			`TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 );`
40			`TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 );`
41			`TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 );`
42			`TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 );`
43
44			`TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 );`
45			`TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 );`
46			`TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 );`
47			`TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 );`
48			`TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 );`
49			`TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 );`
50
51			`#-------------------------------------------------------------`
52			`# Test delay slot instructions not executed nor bypassed`
53			`#-------------------------------------------------------------`
54
55			`TEST_CASE( 21, x1, 3, \`
56			`li x1, 1; \`
57			`beq x0, x0, 1f; \`
58			`addi x1, x1, 1; \`
59			`addi x1, x1, 1; \`
60			`addi x1, x1, 1; \`
61			`addi x1, x1, 1; \`
62			`1: addi x1, x1, 1; \`
63			`addi x1, x1, 1; \`
64			`)`
65
66			`TEST_PASSFAIL`
67
68			`RVTEST_CODE_END`
69
70			`.data`
71			`RV_COMPLIANCE_DATA_BEGIN`
72			`test_res:`
73			`.fill 30, 4, -1`
74			`RV_COMPLIANCE_DATA_END`
75

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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32ui/] [rv64ui/] [beq.S] - Blame information for rev 2