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[/] [fwrisc/] [trunk/] [ve/] [fwrisc/] [tests/] [riscv-compliance/] [riscv-test-suite/] [rv32ui/] [rv64ui/] [slti.S] - Blame information for rev 2

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Line No. Rev Author Line
1 2 mballance
# See LICENSE for license details.
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#*****************************************************************************
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# slti.S
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#-----------------------------------------------------------------------------
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#
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# Test slti instruction.
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#
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#include "riscv_test.h"
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#include "compliance_test.h"
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#include "compliance_io.h"
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#include "aw_test_macros.h"
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RVTEST_RV64U
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RVTEST_CODE_BEGIN
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  #-------------------------------------------------------------
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  # Arithmetic tests
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  #-------------------------------------------------------------
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  TEST_IMM_OP( 2,  slti, 0, 0x0000000000000000, 0x000 );
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  TEST_IMM_OP( 3,  slti, 0, 0x0000000000000001, 0x001 );
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  TEST_IMM_OP( 4,  slti, 1, 0x0000000000000003, 0x007 );
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  TEST_IMM_OP( 5,  slti, 0, 0x0000000000000007, 0x003 );
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  TEST_IMM_OP( 6,  slti, 0, 0x0000000000000000, 0x800 );
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  TEST_IMM_OP( 7,  slti, 1, 0xffffffff80000000, 0x000 );
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  TEST_IMM_OP( 8,  slti, 1, 0xffffffff80000000, 0x800 );
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  TEST_IMM_OP( 9,  slti, 1, 0x0000000000000000, 0x7ff );
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  TEST_IMM_OP( 10, slti, 0, 0x000000007fffffff, 0x000 );
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  TEST_IMM_OP( 11, slti, 0, 0x000000007fffffff, 0x7ff );
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  TEST_IMM_OP( 12, slti, 1, 0xffffffff80000000, 0x7ff );
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  TEST_IMM_OP( 13, slti, 0, 0x000000007fffffff, 0x800 );
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  TEST_IMM_OP( 14, slti, 0, 0x0000000000000000, 0xfff );
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  TEST_IMM_OP( 15, slti, 1, 0xffffffffffffffff, 0x001 );
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  TEST_IMM_OP( 16, slti, 0, 0xffffffffffffffff, 0xfff );
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  #-------------------------------------------------------------
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  # Source/Destination tests
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  #-------------------------------------------------------------
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  TEST_IMM_SRC1_EQ_DEST( 17, slti, 1, 11, 13 );
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  #-------------------------------------------------------------
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  # Bypassing tests
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  #-------------------------------------------------------------
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  TEST_IMM_DEST_BYPASS( 18, 0, slti, 0, 15, 10 );
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  TEST_IMM_DEST_BYPASS( 19, 1, slti, 1, 10, 16 );
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  TEST_IMM_DEST_BYPASS( 20, 2, slti, 0, 16,  9 );
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  TEST_IMM_SRC1_BYPASS( 21, 0, slti, 1, 11, 15 );
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  TEST_IMM_SRC1_BYPASS( 22, 1, slti, 0, 17,  8 );
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  TEST_IMM_SRC1_BYPASS( 23, 2, slti, 1, 12, 14 );
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  TEST_IMM_ZEROSRC1( 24, slti, 0, 0xfff );
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  TEST_IMM_ZERODEST( 25, slti, 0x00ff00ff, 0xfff );
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  TEST_PASSFAIL
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RVTEST_CODE_END
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  .data
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RV_COMPLIANCE_DATA_BEGIN
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test_res:
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    .fill 40, 4, -1
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RV_COMPLIANCE_DATA_END
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