| 1 |
2 |
mballance |
# See LICENSE for license details.
|
| 2 |
|
|
|
| 3 |
|
|
#*****************************************************************************
|
| 4 |
|
|
# srl.S
|
| 5 |
|
|
#-----------------------------------------------------------------------------
|
| 6 |
|
|
#
|
| 7 |
|
|
# Test srl instruction.
|
| 8 |
|
|
#
|
| 9 |
|
|
|
| 10 |
|
|
#include "riscv_test.h"
|
| 11 |
|
|
#include "compliance_test.h"
|
| 12 |
|
|
#include "compliance_io.h"
|
| 13 |
|
|
#include "aw_test_macros.h"
|
| 14 |
|
|
|
| 15 |
|
|
RVTEST_RV64U
|
| 16 |
|
|
RVTEST_CODE_BEGIN
|
| 17 |
|
|
|
| 18 |
|
|
#-------------------------------------------------------------
|
| 19 |
|
|
# Arithmetic tests
|
| 20 |
|
|
#-------------------------------------------------------------
|
| 21 |
|
|
|
| 22 |
|
|
#define TEST_SRL(n, v, a) \
|
| 23 |
|
|
TEST_RR_OP(n, srl, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a)
|
| 24 |
|
|
|
| 25 |
|
|
TEST_SRL( 2, 0xffffffff80000000, 0 );
|
| 26 |
|
|
TEST_SRL( 3, 0xffffffff80000000, 1 );
|
| 27 |
|
|
TEST_SRL( 4, 0xffffffff80000000, 7 );
|
| 28 |
|
|
TEST_SRL( 5, 0xffffffff80000000, 14 );
|
| 29 |
|
|
TEST_SRL( 6, 0xffffffff80000001, 31 );
|
| 30 |
|
|
|
| 31 |
|
|
TEST_SRL( 7, 0xffffffffffffffff, 0 );
|
| 32 |
|
|
TEST_SRL( 8, 0xffffffffffffffff, 1 );
|
| 33 |
|
|
TEST_SRL( 9, 0xffffffffffffffff, 7 );
|
| 34 |
|
|
TEST_SRL( 10, 0xffffffffffffffff, 14 );
|
| 35 |
|
|
TEST_SRL( 11, 0xffffffffffffffff, 31 );
|
| 36 |
|
|
|
| 37 |
|
|
TEST_SRL( 12, 0x0000000021212121, 0 );
|
| 38 |
|
|
TEST_SRL( 13, 0x0000000021212121, 1 );
|
| 39 |
|
|
TEST_SRL( 14, 0x0000000021212121, 7 );
|
| 40 |
|
|
TEST_SRL( 15, 0x0000000021212121, 14 );
|
| 41 |
|
|
TEST_SRL( 16, 0x0000000021212121, 31 );
|
| 42 |
|
|
|
| 43 |
|
|
# Verify that shifts only use bottom five bits
|
| 44 |
|
|
|
| 45 |
|
|
TEST_RR_OP( 17, srl, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 );
|
| 46 |
|
|
TEST_RR_OP( 18, srl, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffc1 );
|
| 47 |
|
|
TEST_RR_OP( 19, srl, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffc7 );
|
| 48 |
|
|
TEST_RR_OP( 20, srl, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffce );
|
| 49 |
|
|
TEST_RR_OP( 21, srl, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff );
|
| 50 |
|
|
|
| 51 |
|
|
#-------------------------------------------------------------
|
| 52 |
|
|
# Source/Destination tests
|
| 53 |
|
|
#-------------------------------------------------------------
|
| 54 |
|
|
|
| 55 |
|
|
TEST_RR_SRC1_EQ_DEST( 22, srl, 0x01000000, 0x80000000, 7 );
|
| 56 |
|
|
TEST_RR_SRC2_EQ_DEST( 23, srl, 0x00020000, 0x80000000, 14 );
|
| 57 |
|
|
TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 );
|
| 58 |
|
|
|
| 59 |
|
|
#-------------------------------------------------------------
|
| 60 |
|
|
# Bypassing tests
|
| 61 |
|
|
#-------------------------------------------------------------
|
| 62 |
|
|
|
| 63 |
|
|
TEST_RR_DEST_BYPASS( 25, 0, srl, 0x01000000, 0x80000000, 7 );
|
| 64 |
|
|
TEST_RR_DEST_BYPASS( 26, 1, srl, 0x00020000, 0x80000000, 14 );
|
| 65 |
|
|
TEST_RR_DEST_BYPASS( 27, 2, srl, 0x00000001, 0x80000000, 31 );
|
| 66 |
|
|
|
| 67 |
|
|
TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x01000000, 0x80000000, 7 );
|
| 68 |
|
|
TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x00020000, 0x80000000, 14 );
|
| 69 |
|
|
TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x00000001, 0x80000000, 31 );
|
| 70 |
|
|
TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x01000000, 0x80000000, 7 );
|
| 71 |
|
|
TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x00020000, 0x80000000, 14 );
|
| 72 |
|
|
TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x00000001, 0x80000000, 31 );
|
| 73 |
|
|
|
| 74 |
|
|
TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x01000000, 0x80000000, 7 );
|
| 75 |
|
|
TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x00020000, 0x80000000, 14 );
|
| 76 |
|
|
TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x00000001, 0x80000000, 31 );
|
| 77 |
|
|
TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x01000000, 0x80000000, 7 );
|
| 78 |
|
|
TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x00020000, 0x80000000, 14 );
|
| 79 |
|
|
TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x00000001, 0x80000000, 31 );
|
| 80 |
|
|
|
| 81 |
|
|
TEST_RR_ZEROSRC1( 40, srl, 0, 15 );
|
| 82 |
|
|
TEST_RR_ZEROSRC2( 41, srl, 32, 32 );
|
| 83 |
|
|
TEST_RR_ZEROSRC12( 42, srl, 0 );
|
| 84 |
|
|
TEST_RR_ZERODEST( 43, srl, 1024, 2048 );
|
| 85 |
|
|
|
| 86 |
|
|
TEST_PASSFAIL
|
| 87 |
|
|
|
| 88 |
|
|
RVTEST_CODE_END
|
| 89 |
|
|
|
| 90 |
|
|
.data
|
| 91 |
|
|
RV_COMPLIANCE_DATA_BEGIN
|
| 92 |
|
|
test_res:
|
| 93 |
|
|
.fill 60, 4, -1
|
| 94 |
|
|
RV_COMPLIANCE_DATA_END
|
| 95 |
|
|
|
