| 1 |
2 |
daniel.kho |
/*
|
| 2 |
|
|
This file is part of the Galois Linear Feedback Shift Register
|
| 3 |
|
|
(galois_lfsr) project:
|
| 4 |
|
|
http://www.opencores.org/project,galois_lfsr
|
| 5 |
|
|
|
| 6 |
|
|
Description
|
| 7 |
|
|
Synthesisable use case for Galois LFSR.
|
| 8 |
|
|
This example is a CRC generator that uses a Galois LFSR.
|
| 9 |
|
|
|
| 10 |
|
|
ToDo:
|
| 11 |
|
|
|
| 12 |
|
|
Author(s):
|
| 13 |
|
|
- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
|
| 14 |
|
|
|
| 15 |
|
|
Copyright (C) 2012-2013 Authors and OPENCORES.ORG
|
| 16 |
|
|
|
| 17 |
|
|
This source file may be used and distributed without
|
| 18 |
|
|
restriction provided that this copyright statement is not
|
| 19 |
|
|
removed from the file and that any derivative work contains
|
| 20 |
|
|
the original copyright notice and the associated disclaimer.
|
| 21 |
|
|
|
| 22 |
|
|
This source file is free software; you can redistribute it
|
| 23 |
|
|
and/or modify it under the terms of the GNU Lesser General
|
| 24 |
|
|
Public License as published by the Free Software Foundation;
|
| 25 |
|
|
either version 2.1 of the License, or (at your option) any
|
| 26 |
|
|
later version.
|
| 27 |
|
|
|
| 28 |
|
|
This source is distributed in the hope that it will be
|
| 29 |
|
|
useful, but WITHOUT ANY WARRANTY; without even the implied
|
| 30 |
|
|
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
| 31 |
|
|
PURPOSE. See the GNU Lesser General Public License for more
|
| 32 |
|
|
details.
|
| 33 |
|
|
|
| 34 |
|
|
You should have received a copy of the GNU Lesser General
|
| 35 |
|
|
Public License along with this source; if not, download it
|
| 36 |
|
|
from http://www.opencores.org/lgpl.shtml.
|
| 37 |
|
|
*/
|
| 38 |
|
|
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
|
| 39 |
|
|
--use work.types.all;
|
| 40 |
|
|
|
| 41 |
|
|
entity user is
|
| 42 |
|
|
generic(
|
| 43 |
|
|
parallelLoad:boolean:=false;
|
| 44 |
|
|
tapVector:boolean_vector:=(
|
| 45 |
|
|
/* Example polynomial from Wikipedia. */
|
| 46 |
|
|
0|1|2|8=>true, 7 downto 3=>false
|
| 47 |
|
|
)
|
| 48 |
|
|
);
|
| 49 |
|
|
port(
|
| 50 |
|
|
/* Comment-out for simulation. */
|
| 51 |
|
|
--clk,reset:in std_ulogic;
|
| 52 |
|
|
msg:in unsigned(tapVector'length-1 downto 0):=9x"57"; -- Should be (tapVector'length downto 0). TODO report ModelSim bug.
|
| 53 |
|
|
crc32:out unsigned(31 downto 0):=(others=>'0')
|
| 54 |
|
|
);
|
| 55 |
|
|
end entity user;
|
| 56 |
|
|
|
| 57 |
|
|
architecture rtl of user is
|
| 58 |
|
|
signal n,c:natural;
|
| 59 |
|
|
|
| 60 |
|
|
/* Tester signals. */
|
| 61 |
|
|
signal d:std_ulogic;
|
| 62 |
|
|
/* synthesis translate_off */
|
| 63 |
|
|
signal clk,reset:std_ulogic:='0';
|
| 64 |
|
|
/* synthesis translate_on */
|
| 65 |
|
|
|
| 66 |
|
|
signal loadEn,computeClk:std_ulogic; -- clock gating.
|
| 67 |
|
|
signal loaded,i_loaded:boolean;
|
| 68 |
|
|
signal computed,i_computed:boolean;
|
| 69 |
|
|
|
| 70 |
|
|
begin
|
| 71 |
|
|
/* Simulation Tester. */
|
| 72 |
|
|
/* synthesis translate_off */
|
| 73 |
|
|
clk<=not clk after 10 ps;
|
| 74 |
|
|
|
| 75 |
|
|
process is begin
|
| 76 |
|
|
reset<='0'; wait for 1 ps;
|
| 77 |
|
|
reset<='1'; wait for 500 ps;
|
| 78 |
|
|
reset<='0';
|
| 79 |
|
|
wait;
|
| 80 |
|
|
end process;
|
| 81 |
|
|
/* synthesis translate_on */
|
| 82 |
|
|
|
| 83 |
|
|
loadEn<=clk when reset='0' and not i_computed else '0';
|
| 84 |
|
|
computeClk<=clk when reset='0' and i_loaded and not i_computed else '0';
|
| 85 |
|
|
|
| 86 |
3 |
daniel.kho |
/* Galois LFSR instance. */
|
| 87 |
2 |
daniel.kho |
i_lfsr: entity work.lfsr(rtl)
|
| 88 |
|
|
generic map(taps=>tapVector)
|
| 89 |
|
|
/*generic map(taps => (
|
| 90 |
|
|
0|1|2|8=>true,
|
| 91 |
|
|
7 downto 3=>false
|
| 92 |
|
|
))*/
|
| 93 |
|
|
port map(nReset=>not reset, clk=>loadEn,
|
| 94 |
|
|
load=>parallelLoad,
|
| 95 |
|
|
seed=>msg,
|
| 96 |
|
|
d=>d,
|
| 97 |
|
|
q=>crc32(msg'range)
|
| 98 |
|
|
);
|
| 99 |
|
|
|
| 100 |
|
|
/* Load message into LFSR. */
|
| 101 |
|
|
process(reset,loadEn) is begin
|
| 102 |
|
|
if reset then loaded<=false; n<=msg'length-1; d<='0';
|
| 103 |
|
|
elsif rising_edge(loadEn) then
|
| 104 |
|
|
d<='0';
|
| 105 |
|
|
|
| 106 |
|
|
/* for parallel mode, LFSR automatically loads the seed in parallel. */
|
| 107 |
|
|
if parallelLoad then d<='0'; loaded<=true;
|
| 108 |
|
|
else
|
| 109 |
|
|
if not loaded then d<=msg(n); end if;
|
| 110 |
|
|
|
| 111 |
|
|
if n>0 then n<=n-1;
|
| 112 |
|
|
else loaded<=true;
|
| 113 |
|
|
end if;
|
| 114 |
|
|
end if;
|
| 115 |
|
|
end if;
|
| 116 |
|
|
end process;
|
| 117 |
|
|
|
| 118 |
|
|
/* Shift zeroes into LFSR after message has been loaded completely. */
|
| 119 |
|
|
process(reset,loaded,computeClk) is begin
|
| 120 |
|
|
if reset='1' or not loaded then computed<=false; c<=msg'length-1;
|
| 121 |
|
|
elsif rising_edge(computeClk) then
|
| 122 |
|
|
if c>0 then c<=c-1;
|
| 123 |
|
|
else computed<=true;
|
| 124 |
|
|
end if;
|
| 125 |
|
|
end if;
|
| 126 |
|
|
end process;
|
| 127 |
|
|
|
| 128 |
|
|
/* Register pipelines. */
|
| 129 |
|
|
process(clk) is begin
|
| 130 |
|
|
if falling_edge(clk) then
|
| 131 |
|
|
i_loaded<=loaded;
|
| 132 |
|
|
i_computed<=computed;
|
| 133 |
|
|
end if;
|
| 134 |
|
|
end process;
|
| 135 |
|
|
end architecture rtl;
|
