OpenCores
URL https://opencores.org/ocsvn/gecko3/gecko3/trunk

Subversion Repositories gecko3

[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [coregenerator/] [coregenerator_fifo_send.vho] - Blame information for rev 24

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 nussgipfel
--------------------------------------------------------------------------------
2
--     This file is owned and controlled by Xilinx and must be used           --
3
--     solely for design, simulation, implementation and creation of          --
4
--     design files limited to Xilinx devices or technologies. Use            --
5
--     with non-Xilinx devices or technologies is expressly prohibited        --
6
--     and immediately terminates your license.                               --
7
--                                                                            --
8
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
9
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
10
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
11
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
12
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
13
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
14
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
15
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
16
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
17
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
18
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
19
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
20
--     FOR A PARTICULAR PURPOSE.                                              --
21
--                                                                            --
22
--     Xilinx products are not intended for use in life support               --
23
--     appliances, devices, or systems. Use in such applications are          --
24
--     expressly prohibited.                                                  --
25
--                                                                            --
26
--     (c) Copyright 1995-2009 Xilinx, Inc.                                   --
27
--     All rights reserved.                                                   --
28
--------------------------------------------------------------------------------
29
-- The following code must appear in the VHDL architecture header:
30
 
31
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
32
component coregenerator_fifo_send
33
        port (
34
        din: IN std_logic_VECTOR(31 downto 0);
35
        rd_clk: IN std_logic;
36
        rd_en: IN std_logic;
37
        rst: IN std_logic;
38
        wr_clk: IN std_logic;
39
        wr_en: IN std_logic;
40
        almost_empty: OUT std_logic;
41
        almost_full: OUT std_logic;
42
        dout: OUT std_logic_VECTOR(15 downto 0);
43
        empty: OUT std_logic;
44
        full: OUT std_logic);
45
end component;
46
 
47
-- Synplicity black box declaration
48
attribute syn_black_box : boolean;
49
attribute syn_black_box of coregenerator_fifo_send: component is true;
50
 
51
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
52
 
53
-- The following code must appear in the VHDL architecture
54
-- body. Substitute your own instance name and net names.
55
 
56
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
57
your_instance_name : coregenerator_fifo_send
58
                port map (
59
                        din => din,
60
                        rd_clk => rd_clk,
61
                        rd_en => rd_en,
62
                        rst => rst,
63
                        wr_clk => wr_clk,
64
                        wr_en => wr_en,
65
                        almost_empty => almost_empty,
66
                        almost_full => almost_full,
67
                        dout => dout,
68
                        empty => empty,
69
                        full => full);
70
-- INST_TAG_END ------ End INSTANTIATION Template ------------
71
 
72
-- You must compile the wrapper file coregenerator_fifo_send.vhd when simulating
73
-- the core, coregenerator_fifo_send. When compiling the wrapper file, be sure to
74
-- reference the XilinxCoreLib VHDL simulation library. For detailed
75
-- instructions, please refer to the "CORE Generator Help".
76
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.