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ktt1 |
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-- _ _ __ ____ --
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-- / / | | / _| | __| --
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-- | |_| | _ _ / / | |_ --
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-- | _ | | | | | | | | _| --
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-- | | | | | |_| | \ \_ | |__ --
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-- |_| |_| \_____| \__| |____| microLab --
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-- --
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-- Bern University of Applied Sciences (BFH) --
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-- Quellgasse 21 --
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-- Room HG 4.33 --
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-- 2501 Biel/Bienne --
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-- Switzerland --
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-- --
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-- http://www.microlab.ch --
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--------------------------------------------------------------------------------
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-- GECKO4com
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--
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-- 2010/2011 Dr. Theo Kluter
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--
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-- This VHDL code is free code: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This VHDL code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with these sources. If not, see <http://www.gnu.org/licenses/>.
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--
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-- The unisim library is used for simulation of the xilinx specific components
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-- For generic usage please use:
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-- LIBRARY work;
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-- USE work.xilinx_generic.all;
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-- And use the xilinx generic package found in the xilinx generic module
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LIBRARY unisim;
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USE unisim.all;
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ARCHITECTURE xilinx OF flash_if IS
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COMPONENT FDE
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GENERIC ( INIT : bit );
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PORT ( Q : OUT std_logic;
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C : IN std_logic;
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CE : IN std_logic;
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D : IN std_logic );
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END COMPONENT;
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COMPONENT FDE_1
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GENERIC ( INIT : bit );
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PORT ( Q : OUT std_logic;
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C : IN std_logic;
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CE : IN std_logic;
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D : IN std_logic );
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END COMPONENT;
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COMPONENT FD
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GENERIC ( INIT : bit );
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PORT ( Q : OUT std_logic;
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C : IN std_logic;
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D : IN std_logic );
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END COMPONENT;
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COMPONENT FD_1
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GENERIC ( INIT : bit );
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PORT ( Q : OUT std_logic;
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C : IN std_logic;
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D : IN std_logic );
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END COMPONENT;
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COMPONENT fifo_2kb
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PORT ( clock : IN std_logic;
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reset : IN std_logic;
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-- push port
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push : IN std_logic;
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push_data : IN std_logic_vector( 7 DOWNTO 0 );
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push_size : IN std_logic;
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-- pop port
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pop : IN std_logic;
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pop_data : OUT std_logic_vector( 7 DOWNTO 0 );
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pop_size : OUT std_logic;
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-- control port
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fifo_full : OUT std_logic;
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fifo_empty : OUT std_logic );
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END COMPONENT;
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COMPONENT RAMB16_S9_S18
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PORT ( DOA : OUT std_logic_vector( 7 DOWNTO 0 );
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DOPA : OUT std_logic_vector( 0 DOWNTO 0 );
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ADDRA : IN std_logic_vector(10 DOWNTO 0 );
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CLKA : IN std_logic;
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DIA : IN std_logic_vector( 7 DOWNTO 0 );
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DIPA : IN std_logic_vector( 0 DOWNTO 0 );
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ENA : IN std_logic;
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SSRA : IN std_logic;
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WEA : IN std_logic;
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DOB : OUT std_logic_vector(15 DOWNTO 0 );
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DOPB : OUT std_logic_vector( 1 DOWNTO 0 );
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ADDRB : IN std_logic_vector( 9 DOWNTO 0 );
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CLKB : IN std_logic;
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DIB : IN std_logic_vector(15 DOWNTO 0 );
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DIPB : IN std_logic_vector( 1 DOWNTO 0 );
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ENB : IN std_logic;
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SSRB : IN std_logic;
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WEB : IN std_logic );
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END COMPONENT;
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TYPE FLASH_STATE_TYPE IS (RESET_STATE , SET_AUTOSELECT , READ_ID , IDLE ,
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CHECK_ID , AUTO_NOP , RESET_AUTO , RESET_NOP ,
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READ_HW , CHECK_HW , SIGNAL_DONE , INIT_ERASE_S1 ,
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ERASE_S1 , WAIT_BUSY_LO , WAIT_BUSY_HI , NOP_READ,
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INIT_READ , COPY_PAYLOAD , CHECK_SIZE , PLAY_WRITE ,
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SIGNAL_ERROR , RESET_FIFO , INIT_WRITE , DO_WRITE ,
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WAIT_READY_LO , WAIT_READY_HI , WRITE_UPDATE ,
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INIT_CHECK_EMPTY , CHECK_EMPTY , DO_PUD_WRITE ,
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SET_PUD_SIZE_1 , SET_PUD_SIZE_2 , DO_PUD_READ ,
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COPY_PUD_DATA , NEXT_SECTOR , SIGNAL_INIT );
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CONSTANT c_vga_offset : std_logic_vector( 4 DOWNTO 0 ) := "10010";
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SIGNAL s_flash_state_reg : FLASH_STATE_TYPE;
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SIGNAL s_delay_counter_reg : std_logic_vector( 2 DOWNTO 0 );
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SIGNAL s_player_count_reg : std_logic_vector( 2 DOWNTO 0 );
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SIGNAL s_command_byte : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_byte_address : std_logic_vector(20 DOWNTO 0 );
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SIGNAL s_flash_data_in : std_logic_vector(15 DOWNTO 0 );
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SIGNAL s_data_out_next : std_logic_vector(15 DOWNTO 0 );
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SIGNAL s_tri_data_out : std_logic;
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SIGNAL s_flash_n_ce : std_logic;
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SIGNAL s_flash_n_oe : std_logic;
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SIGNAL s_flash_n_we : std_logic;
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SIGNAL s_state_tick : std_logic;
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SIGNAL s_sector_address_reg : std_logic_vector(20 DOWNTO 16);
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SIGNAL s_pud_sector_address : std_logic_vector(20 DOWNTO 16);
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SIGNAL s_in_sector_address_reg : std_logic_vector(15 DOWNTO 1);
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SIGNAL s_flash_mounted_reg : std_logic;
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SIGNAL s_flash_top_boot_reg : std_logic;
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SIGNAL s_flash_sec1_empty_reg : std_logic;
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SIGNAL s_next_address : std_logic;
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SIGNAL s_next_in_sector_addr : std_logic_vector(16 DOWNTO 1);
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SIGNAL s_word_data_reg : std_logic_vector(15 DOWNTO 0);
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SIGNAL s_word_bytes_valid_reg : std_logic_vector( 1 DOWNTO 0);
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SIGNAL s_latch_read_data : std_logic;
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SIGNAL s_fifo_read_info_reg : std_logic_vector( 2 DOWNTO 0);
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SIGNAL s_push_lo : std_logic;
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SIGNAL s_push_hi : std_logic;
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SIGNAL s_payload_size_cnt_reg : std_logic_vector(21 DOWNTO 0);
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SIGNAL s_payload_size_cnt_next : std_logic_vector(21 DOWNTO 0);
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SIGNAL s_fifo_empty : std_logic;
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SIGNAL s_fifo_pop : std_logic;
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SIGNAL s_fifo_pop_data : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_fifo_pop_last : std_logic;
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SIGNAL s_fifo_word_reg : std_logic_vector(15 DOWNTO 0 );
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SIGNAL s_fifo_word_valid_reg : std_logic_vector( 1 DOWNTO 0 );
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SIGNAL s_invalid_size : std_logic;
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SIGNAL s_last_byte_reg : std_logic;
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SIGNAL s_fifo_reset : std_logic;
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SIGNAL s_write_idx_reg : std_logic_vector( 1 DOWNTO 0 );
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SIGNAL s_write_data_reg : std_logic_vector(15 DOWNTO 0 );
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SIGNAL s_write_size : std_logic;
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SIGNAL s_write_data : std_logic;
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SIGNAL s_done_reg : std_logic;
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SIGNAL s_write_done_reg : std_logic;
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SIGNAL s_empty_cnt_reg : std_logic_vector( 2 DOWNTO 0 );
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SIGNAL s_write_empty : std_logic;
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SIGNAL s_empty_size : std_logic;
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SIGNAL s_empty_data : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_start_pud_write : std_logic;
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SIGNAL s_start_pud_read : std_logic;
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SIGNAL s_is_pud_action_reg : std_logic;
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SIGNAL s_pud_word : std_logic_vector(15 DOWNTO 0 );
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SIGNAL s_write_pud : std_logic;
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SIGNAL s_we_pud_byte : std_logic;
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SIGNAL s_ena_pud_byte : std_logic;
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SIGNAL s_pud_byte_addr_reg : std_logic_vector(11 DOWNTO 0 );
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SIGNAL s_ena_pud_word_read : std_logic;
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SIGNAL s_scpi_push : std_logic;
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SIGNAL s_scpi_n_reset : std_logic;
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SIGNAL s_pud_byte : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_pud_size_value : std_logic_vector( 7 DOWNTO 0 );
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SIGNAL s_pud_word_address_reg : std_logic_vector( 9 DOWNTO 0 );
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SIGNAL s_we_pud_payload : std_logic;
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SIGNAL s_busy_pipe_reg : std_logic_vector( 3 DOWNTO 0 );
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SIGNAL s_we_vga : std_logic;
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SIGNAL s_we_addr : std_logic_vector(10 DOWNTO 0);
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SIGNAL s_we_data : std_logic_vector( 7 DOWNTO 0);
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SIGNAL s_pud_hi_reg : std_logic;
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SIGNAL s_time_out_cnt_reg : std_logic_vector( 3 DOWNTO 0 );
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BEGIN
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--------------------------------------------------------------------------------
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--- Here the outputs are defined ---
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--------------------------------------------------------------------------------
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flash_n_byte <= '1';
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flash_idle <= '1' WHEN s_flash_state_reg = IDLE ELSE '0';
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flash_n_busy <= '0' WHEN s_flash_state_reg = INIT_CHECK_EMPTY OR
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s_flash_state_reg = CHECK_EMPTY OR
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s_flash_state_reg = INIT_ERASE_S1 OR
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s_flash_state_reg = ERASE_S1 OR
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s_flash_state_reg = WAIT_BUSY_LO OR
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s_flash_state_reg = WAIT_BUSY_HI OR
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s_flash_state_reg = NEXT_SECTOR OR
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s_flash_state_reg = INIT_WRITE OR
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s_flash_state_reg = PLAY_WRITE OR
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s_flash_state_reg = DO_WRITE OR
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s_flash_state_reg = WAIT_READY_LO OR
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s_flash_state_reg = WAIT_READY_HI OR
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s_flash_state_reg = WRITE_UPDATE OR
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reset = '1' ELSE '1';
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done <= '1' WHEN s_flash_state_reg = SIGNAL_DONE OR
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s_done_reg = '1' ELSE '0';
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flash_present <= s_flash_mounted_reg;
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flash_s1_empty <= s_flash_sec1_empty_reg;
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push <= ((s_push_lo OR s_push_hi) AND
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NOT(s_payload_size_cnt_reg(21))) OR s_write_empty;
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push_data <= s_word_data_reg( 7 DOWNTO 0 ) WHEN s_push_lo = '1' ELSE
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s_word_data_reg(15 DOWNTO 8 ) WHEN s_push_hi = '1' ELSE
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s_empty_data;
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push_last <= (s_push_lo OR s_push_hi) AND s_payload_size_cnt_next(21);
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push_size <= (NOT(s_fifo_read_info_reg(2)) AND
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(s_push_lo OR s_push_hi)) OR s_empty_size;
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size_error <= '1' WHEN s_flash_state_reg = SIGNAL_ERROR ELSE '0';
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s_fifo_reset <= '1' WHEN reset = '1' OR
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s_flash_state_reg = RESET_FIFO ELSE '0';
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scpi_pop <= s_we_pud_byte;
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scpi_push_data <= s_pud_size_value OR s_pud_byte;
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start_config <= '0';
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--------------------------------------------------------------------------------
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--- Here the control signals are defined ---
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--------------------------------------------------------------------------------
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s_flash_n_ce <= '1' WHEN reset = '1' OR
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s_flash_state_reg = IDLE OR
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s_flash_state_reg = SIGNAL_DONE ELSE '0';
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s_flash_n_oe <= '0' WHEN s_flash_state_reg = READ_ID OR
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s_flash_state_reg = RESET_NOP OR
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s_flash_state_reg = READ_HW OR
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s_flash_state_reg = NOP_READ OR
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s_flash_state_reg = INIT_READ OR
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s_flash_state_reg = CHECK_HW OR
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s_flash_state_reg = COPY_PAYLOAD OR
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s_flash_state_reg = INIT_CHECK_EMPTY OR
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s_flash_state_reg = CHECK_EMPTY OR
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s_flash_state_reg = COPY_PUD_DATA ELSE '1';
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s_tri_data_out <= '0' WHEN s_flash_state_reg = SET_AUTOSELECT OR
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s_flash_state_reg = RESET_AUTO OR
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s_flash_state_reg = ERASE_S1 OR
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s_flash_state_reg = PLAY_WRITE OR
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s_flash_state_reg = DO_WRITE ELSE '1';
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s_flash_n_we <= '0' WHEN (s_delay_counter_reg(1 DOWNTO 0) = "01" OR
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s_delay_counter_reg(1 DOWNTO 0) = "10") AND
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(s_flash_state_reg = SET_AUTOSELECT OR
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s_flash_state_reg = RESET_AUTO OR
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s_flash_state_reg = ERASE_S1 OR
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s_flash_state_reg = PLAY_WRITE OR
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s_flash_state_reg = DO_WRITE) ELSE '1';
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s_state_tick <= s_delay_counter_reg(1) AND s_delay_counter_reg(0);
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s_next_address <= '1' WHEN (s_delay_counter_reg = "011" AND
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((s_word_bytes_valid_reg = "00" AND
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s_flash_state_reg = COPY_PAYLOAD) OR
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s_flash_state_reg = CHECK_HW OR
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s_flash_state_reg = COPY_PUD_DATA OR
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s_flash_state_reg = CHECK_EMPTY)) OR
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s_flash_state_reg = WRITE_UPDATE ELSE '0';
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s_latch_read_data <= '1' WHEN s_word_bytes_valid_reg = "00" AND
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s_delay_counter_reg(2) = '1' AND
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s_flash_state_reg = COPY_PAYLOAD ELSE '0';
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s_next_in_sector_addr <= unsigned("0"&s_in_sector_address_reg) + 1;
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s_invalid_size <= '1' WHEN bitfile_size(31 DOWNTO 21) /= "000"&X"00" OR
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bitfile_size(20 DOWNTO 16) = "11111" ELSE '0';
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|
|
make_addr_data : PROCESS( s_player_count_reg , s_command_byte ,
|
| 283 |
|
|
s_sector_address_reg , s_in_sector_address_reg ,
|
| 284 |
|
|
s_write_data_reg )
|
| 285 |
|
|
BEGIN
|
| 286 |
|
|
CASE (s_player_count_reg) IS
|
| 287 |
|
|
WHEN "001" |
|
| 288 |
|
|
"101" => s_byte_address <= "0"&X"00AAA";
|
| 289 |
|
|
s_data_out_next <= X"00AA";
|
| 290 |
|
|
WHEN "010" |
|
| 291 |
|
|
"110" => s_byte_address <= "0"&X"00555";
|
| 292 |
|
|
s_data_out_next <= X"0055";
|
| 293 |
|
|
WHEN "011" => s_byte_address <= "0"&X"00AAA";
|
| 294 |
|
|
s_data_out_next <= X"00"&s_command_byte;
|
| 295 |
|
|
WHEN "111" => s_byte_address <= s_sector_address_reg&X"0000";
|
| 296 |
|
|
s_data_out_next <= X"00"&s_command_byte;
|
| 297 |
|
|
WHEN OTHERS => s_byte_address <= s_sector_address_reg&
|
| 298 |
|
|
s_in_sector_address_reg&"0";
|
| 299 |
|
|
s_data_out_next <= s_write_data_reg;
|
| 300 |
|
|
END CASE;
|
| 301 |
|
|
END PROCESS make_addr_data;
|
| 302 |
|
|
|
| 303 |
|
|
make_done_reg : PROCESS( clock , start_read )
|
| 304 |
|
|
BEGIN
|
| 305 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 306 |
|
|
s_done_reg <= start_read;
|
| 307 |
|
|
END IF;
|
| 308 |
|
|
END PROCESS make_done_reg;
|
| 309 |
|
|
|
| 310 |
|
|
--------------------------------------------------------------------------------
|
| 311 |
|
|
--- Here the empty message is defined ---
|
| 312 |
|
|
--------------------------------------------------------------------------------
|
| 313 |
|
|
s_write_empty <= '0' WHEN fifo_full = '1' OR
|
| 314 |
|
|
s_empty_cnt_reg = "000" ELSE '1';
|
| 315 |
|
|
s_empty_size <= '1' WHEN s_empty_cnt_reg = "111" ELSE '0';
|
| 316 |
|
|
|
| 317 |
|
|
make_empty_data : PROCESS(s_empty_cnt_reg)
|
| 318 |
|
|
BEGIN
|
| 319 |
|
|
CASE (s_empty_cnt_reg) IS
|
| 320 |
|
|
WHEN "111" => s_empty_data <= X"06";
|
| 321 |
|
|
WHEN "110" => s_empty_data <= X"45";
|
| 322 |
|
|
WHEN "101" => s_empty_data <= X"4D";
|
| 323 |
|
|
WHEN "100" => s_empty_data <= X"50";
|
| 324 |
|
|
WHEN "011" => s_empty_data <= X"54";
|
| 325 |
|
|
WHEN "010" => s_empty_data <= X"59";
|
| 326 |
|
|
WHEN "001" => s_empty_data <= X"0A";
|
| 327 |
|
|
WHEN OTHERS => s_empty_data <= X"00";
|
| 328 |
|
|
END CASE;
|
| 329 |
|
|
END PROCESS make_empty_data;
|
| 330 |
|
|
|
| 331 |
|
|
make_empty_cnt_reg : PROCESS( clock , reset , start_read , s_write_empty ,
|
| 332 |
|
|
s_empty_cnt_reg , s_flash_state_reg )
|
| 333 |
|
|
BEGIN
|
| 334 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 335 |
|
|
IF (reset = '1') THEN s_empty_cnt_reg <= "000";
|
| 336 |
|
|
ELSIF (start_read = '1' AND
|
| 337 |
|
|
s_flash_sec1_empty_reg = '1' AND
|
| 338 |
|
|
s_flash_state_reg = IDLE) THEN
|
| 339 |
|
|
s_empty_cnt_reg <= "111";
|
| 340 |
|
|
ELSIF (s_write_empty = '1') THEN
|
| 341 |
|
|
s_empty_cnt_reg <= unsigned(s_empty_cnt_reg) - 1;
|
| 342 |
|
|
END IF;
|
| 343 |
|
|
END IF;
|
| 344 |
|
|
END PROCESS make_empty_cnt_reg;
|
| 345 |
|
|
|
| 346 |
|
|
--------------------------------------------------------------------------------
|
| 347 |
|
|
--- Here the state machine is defined ---
|
| 348 |
|
|
--------------------------------------------------------------------------------
|
| 349 |
|
|
make_state_machine : PROCESS( clock , reset , s_flash_state_reg ,
|
| 350 |
|
|
s_state_tick , s_player_count_reg , start_erase,
|
| 351 |
|
|
s_flash_sec1_empty_reg )
|
| 352 |
|
|
VARIABLE v_next_state : FLASH_STATE_TYPE;
|
| 353 |
|
|
BEGIN
|
| 354 |
|
|
CASE (s_flash_state_reg) IS
|
| 355 |
|
|
WHEN RESET_STATE => IF (s_state_tick = '1') THEN
|
| 356 |
|
|
v_next_state := SET_AUTOSELECT;
|
| 357 |
|
|
ELSE
|
| 358 |
|
|
v_next_state := RESET_STATE;
|
| 359 |
|
|
END IF;
|
| 360 |
|
|
WHEN SET_AUTOSELECT => IF (s_player_count_reg = "000" AND
|
| 361 |
|
|
s_state_tick = '1') THEN
|
| 362 |
|
|
v_next_state := AUTO_NOP;
|
| 363 |
|
|
ELSE
|
| 364 |
|
|
v_next_state := SET_AUTOSELECT;
|
| 365 |
|
|
END IF;
|
| 366 |
|
|
WHEN AUTO_NOP => IF (s_state_tick = '1') THEN
|
| 367 |
|
|
v_next_state := READ_ID;
|
| 368 |
|
|
ELSE
|
| 369 |
|
|
v_next_state := AUTO_NOP;
|
| 370 |
|
|
END IF;
|
| 371 |
|
|
WHEN READ_ID => IF (s_state_tick = '1') THEN
|
| 372 |
|
|
v_next_state := CHECK_ID;
|
| 373 |
|
|
ELSE
|
| 374 |
|
|
v_next_state := READ_ID;
|
| 375 |
|
|
END IF;
|
| 376 |
|
|
WHEN CHECK_ID => IF (s_state_tick = '1') THEN
|
| 377 |
|
|
v_next_state := RESET_AUTO;
|
| 378 |
|
|
ELSE
|
| 379 |
|
|
v_next_state := CHECK_ID;
|
| 380 |
|
|
END IF;
|
| 381 |
|
|
WHEN RESET_AUTO => IF (s_state_tick = '1') THEN
|
| 382 |
|
|
v_next_state := RESET_NOP;
|
| 383 |
|
|
ELSE
|
| 384 |
|
|
v_next_state := RESET_AUTO;
|
| 385 |
|
|
END IF;
|
| 386 |
|
|
WHEN RESET_NOP => IF (s_state_tick = '1') THEN
|
| 387 |
|
|
v_next_state := READ_HW;
|
| 388 |
|
|
ELSE
|
| 389 |
|
|
v_next_state := RESET_NOP;
|
| 390 |
|
|
END IF;
|
| 391 |
|
|
WHEN READ_HW => IF (s_state_tick = '1') THEN
|
| 392 |
|
|
v_next_state := CHECK_HW;
|
| 393 |
|
|
ELSE
|
| 394 |
|
|
v_next_state := READ_HW;
|
| 395 |
|
|
END IF;
|
| 396 |
|
|
WHEN CHECK_HW => IF (s_state_tick = '1') THEN
|
| 397 |
|
|
IF (s_flash_mounted_reg = '1') THEN
|
| 398 |
|
|
v_next_state := COPY_PUD_DATA;
|
| 399 |
|
|
ELSE
|
| 400 |
|
|
v_next_state := IDLE;
|
| 401 |
|
|
END IF;
|
| 402 |
|
|
ELSE
|
| 403 |
|
|
v_next_state := CHECK_HW;
|
| 404 |
|
|
END IF;
|
| 405 |
|
|
WHEN COPY_PUD_DATA => IF (s_state_tick = '1' AND
|
| 406 |
|
|
s_in_sector_address_reg(11) = '1') THEN
|
| 407 |
|
|
v_next_state := IDLE;
|
| 408 |
|
|
ELSE
|
| 409 |
|
|
v_next_state := COPY_PUD_DATA;
|
| 410 |
|
|
END IF;
|
| 411 |
|
|
WHEN IDLE => IF (s_start_pud_write = '1') THEN
|
| 412 |
|
|
v_next_state := DO_PUD_WRITE;
|
| 413 |
|
|
ELSIF (s_start_pud_read = '1') THEN
|
| 414 |
|
|
v_next_state := SET_PUD_SIZE_1;
|
| 415 |
|
|
ELSIF (start_erase = '1') THEN
|
| 416 |
|
|
IF (s_flash_sec1_empty_reg = '1') THEN
|
| 417 |
|
|
v_next_state := SIGNAL_DONE;
|
| 418 |
|
|
ELSE
|
| 419 |
|
|
v_next_state := INIT_CHECK_EMPTY;
|
| 420 |
|
|
END IF;
|
| 421 |
|
|
ELSIF (start_read = '1' AND
|
| 422 |
|
|
s_flash_sec1_empty_reg = '0') THEN
|
| 423 |
|
|
v_next_state := NOP_READ;
|
| 424 |
|
|
ELSIF (start_write = '1') THEN
|
| 425 |
|
|
IF (s_flash_sec1_empty_reg = '0') THEN
|
| 426 |
|
|
v_next_state := SIGNAL_ERROR;
|
| 427 |
|
|
ELSE
|
| 428 |
|
|
v_next_state := CHECK_SIZE;
|
| 429 |
|
|
END IF;
|
| 430 |
|
|
ELSE
|
| 431 |
|
|
v_next_state := IDLE;
|
| 432 |
|
|
END IF;
|
| 433 |
|
|
WHEN INIT_CHECK_EMPTY => IF (s_delay_counter_reg(2) = '1') THEN
|
| 434 |
|
|
v_next_state := CHECK_EMPTY;
|
| 435 |
|
|
ELSE
|
| 436 |
|
|
v_next_state := INIT_CHECK_EMPTY;
|
| 437 |
|
|
END IF;
|
| 438 |
|
|
WHEN CHECK_EMPTY => IF (s_state_tick = '1') THEN
|
| 439 |
|
|
IF (s_sector_address_reg =
|
| 440 |
|
|
s_pud_sector_address) THEN
|
| 441 |
|
|
v_next_state := SIGNAL_DONE;
|
| 442 |
|
|
ELSIF (s_flash_data_in = X"FFFF") THEN
|
| 443 |
|
|
v_next_state := CHECK_EMPTY;
|
| 444 |
|
|
ELSE
|
| 445 |
|
|
v_next_state := INIT_ERASE_S1;
|
| 446 |
|
|
END IF;
|
| 447 |
|
|
ELSE
|
| 448 |
|
|
v_next_state := CHECK_EMPTY;
|
| 449 |
|
|
END IF;
|
| 450 |
|
|
WHEN INIT_ERASE_S1 => IF (s_state_tick = '1') THEN
|
| 451 |
|
|
v_next_state := ERASE_S1;
|
| 452 |
|
|
ELSE
|
| 453 |
|
|
v_next_state := INIT_ERASE_S1;
|
| 454 |
|
|
END IF;
|
| 455 |
|
|
WHEN ERASE_S1 => IF (s_player_count_reg = "000" AND
|
| 456 |
|
|
s_state_tick = '1') THEN
|
| 457 |
|
|
v_next_state := WAIT_BUSY_LO;
|
| 458 |
|
|
ELSE
|
| 459 |
|
|
v_next_state := ERASE_S1;
|
| 460 |
|
|
END IF;
|
| 461 |
|
|
WHEN WAIT_BUSY_LO => IF (s_time_out_cnt_reg(3) = '1') THEN
|
| 462 |
|
|
v_next_state := INIT_ERASE_S1;
|
| 463 |
|
|
ELSIF (s_busy_pipe_reg(3) = '0') THEN
|
| 464 |
|
|
v_next_state := WAIT_BUSY_HI;
|
| 465 |
|
|
ELSE
|
| 466 |
|
|
v_next_state := WAIT_BUSY_LO;
|
| 467 |
|
|
END IF;
|
| 468 |
|
|
WHEN WAIT_BUSY_HI => IF (s_busy_pipe_reg(3) = '1') THEN
|
| 469 |
|
|
IF (s_is_pud_action_reg = '1') THEN
|
| 470 |
|
|
v_next_state := INIT_WRITE;
|
| 471 |
|
|
ELSE
|
| 472 |
|
|
v_next_state := NEXT_SECTOR;
|
| 473 |
|
|
END IF;
|
| 474 |
|
|
ELSE
|
| 475 |
|
|
v_next_state := WAIT_BUSY_HI;
|
| 476 |
|
|
END IF;
|
| 477 |
|
|
WHEN NEXT_SECTOR => v_next_state := INIT_CHECK_EMPTY;
|
| 478 |
|
|
WHEN NOP_READ => IF (s_delay_counter_reg(2) = '1') THEN
|
| 479 |
|
|
v_next_state := INIT_READ;
|
| 480 |
|
|
ELSE
|
| 481 |
|
|
v_next_state := NOP_READ;
|
| 482 |
|
|
END IF;
|
| 483 |
|
|
WHEN INIT_READ => IF (s_delay_counter_reg(2) = '1') THEN
|
| 484 |
|
|
v_next_state := COPY_PAYLOAD;
|
| 485 |
|
|
ELSE
|
| 486 |
|
|
v_next_state := INIT_READ;
|
| 487 |
|
|
END IF;
|
| 488 |
|
|
WHEN COPY_PAYLOAD => IF (s_payload_size_cnt_reg(21) = '1' AND
|
| 489 |
|
|
s_delay_counter_reg = "011") THEN
|
| 490 |
|
|
v_next_state := IDLE;
|
| 491 |
|
|
ELSE
|
| 492 |
|
|
v_next_state := COPY_PAYLOAD;
|
| 493 |
|
|
END IF;
|
| 494 |
|
|
WHEN CHECK_SIZE => IF (s_invalid_size = '1') THEN
|
| 495 |
|
|
v_next_state := SIGNAL_ERROR;
|
| 496 |
|
|
ELSE
|
| 497 |
|
|
v_next_state := INIT_WRITE;
|
| 498 |
|
|
END IF;
|
| 499 |
|
|
WHEN INIT_WRITE => IF (s_write_size = '1' OR
|
| 500 |
|
|
s_write_data = '1' OR
|
| 501 |
|
|
s_write_pud = '1') THEN
|
| 502 |
|
|
v_next_state := PLAY_WRITE;
|
| 503 |
|
|
ELSE
|
| 504 |
|
|
v_next_state := INIT_WRITE;
|
| 505 |
|
|
END IF;
|
| 506 |
|
|
WHEN PLAY_WRITE => IF (s_player_count_reg = "000" AND
|
| 507 |
|
|
s_state_tick = '1') THEN
|
| 508 |
|
|
v_next_state := DO_WRITE;
|
| 509 |
|
|
ELSE
|
| 510 |
|
|
v_next_state := PLAY_WRITE;
|
| 511 |
|
|
END IF;
|
| 512 |
|
|
WHEN DO_WRITE => IF (s_state_tick = '1') THEN
|
| 513 |
|
|
v_next_state := WAIT_READY_LO;
|
| 514 |
|
|
ELSE
|
| 515 |
|
|
v_next_state := DO_WRITE;
|
| 516 |
|
|
END IF;
|
| 517 |
|
|
WHEN WAIT_READY_LO => IF (s_busy_pipe_reg(3) = '0') THEN
|
| 518 |
|
|
v_next_state := WAIT_READY_HI;
|
| 519 |
|
|
ELSE
|
| 520 |
|
|
v_next_state := WAIT_READY_LO;
|
| 521 |
|
|
END IF;
|
| 522 |
|
|
WHEN WAIT_READY_HI => IF (s_busy_pipe_reg(3) = '1') THEN
|
| 523 |
|
|
v_next_state := WRITE_UPDATE;
|
| 524 |
|
|
ELSE
|
| 525 |
|
|
v_next_state := WAIT_READY_HI;
|
| 526 |
|
|
END IF;
|
| 527 |
|
|
WHEN WRITE_UPDATE => IF (s_write_done_reg = '1') THEN
|
| 528 |
|
|
IF (s_is_pud_action_reg = '1') THEN
|
| 529 |
|
|
v_next_state := SIGNAL_DONE;
|
| 530 |
|
|
ELSE
|
| 531 |
|
|
v_next_state := SIGNAL_INIT;
|
| 532 |
|
|
END IF;
|
| 533 |
|
|
ELSE
|
| 534 |
|
|
v_next_state := INIT_WRITE;
|
| 535 |
|
|
END IF;
|
| 536 |
|
|
WHEN SIGNAL_ERROR => v_next_state := RESET_FIFO;
|
| 537 |
|
|
WHEN DO_PUD_WRITE => IF (s_we_pud_byte = '1' AND
|
| 538 |
|
|
scpi_pop_last = '1') THEN
|
| 539 |
|
|
IF (s_flash_mounted_reg = '1') THEN
|
| 540 |
|
|
v_next_state := INIT_ERASE_S1;
|
| 541 |
|
|
ELSE
|
| 542 |
|
|
v_next_state := SIGNAL_DONE;
|
| 543 |
|
|
END IF;
|
| 544 |
|
|
ELSE
|
| 545 |
|
|
v_next_state := DO_PUD_WRITE;
|
| 546 |
|
|
END IF;
|
| 547 |
|
|
WHEN SET_PUD_SIZE_1 => IF (s_scpi_push = '1') THEN
|
| 548 |
|
|
v_next_state := SET_PUD_SIZE_2;
|
| 549 |
|
|
ELSE
|
| 550 |
|
|
v_next_state := SET_PUD_SIZE_1;
|
| 551 |
|
|
END IF;
|
| 552 |
|
|
WHEN SET_PUD_SIZE_2 => IF (s_scpi_push = '1') THEN
|
| 553 |
|
|
v_next_state := DO_PUD_READ;
|
| 554 |
|
|
ELSE
|
| 555 |
|
|
v_next_state := SET_PUD_SIZE_2;
|
| 556 |
|
|
END IF;
|
| 557 |
|
|
WHEN DO_PUD_READ => IF (s_pud_byte_addr_reg(11) = '1') THEN
|
| 558 |
|
|
v_next_state := SIGNAL_DONE;
|
| 559 |
|
|
ELSE
|
| 560 |
|
|
v_next_state := DO_PUD_READ;
|
| 561 |
|
|
END IF;
|
| 562 |
|
|
WHEN SIGNAL_INIT => v_next_state := SIGNAL_DONE;
|
| 563 |
|
|
WHEN OTHERS => v_next_state := IDLE;
|
| 564 |
|
|
END CASE;
|
| 565 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 566 |
|
|
IF (reset = '1') THEN s_flash_state_reg <= RESET_STATE;
|
| 567 |
|
|
ELSE s_flash_state_reg <= v_next_state;
|
| 568 |
|
|
END IF;
|
| 569 |
|
|
END IF;
|
| 570 |
|
|
END PROCESS make_state_machine;
|
| 571 |
|
|
|
| 572 |
|
|
make_time_out_cnt_reg : PROCESS( clock , reset , s_flash_state_reg ,
|
| 573 |
|
|
msec_tick )
|
| 574 |
|
|
BEGIN
|
| 575 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 576 |
|
|
IF (reset = '1') THEN s_time_out_cnt_reg <= X"F";
|
| 577 |
|
|
ELSIF (s_flash_state_reg = ERASE_S1) THEN
|
| 578 |
|
|
s_time_out_cnt_reg <= X"7";
|
| 579 |
|
|
ELSIF (s_time_out_cnt_reg(3) = '0' AND
|
| 580 |
|
|
msec_tick = '1') THEN
|
| 581 |
|
|
s_time_out_cnt_reg <= unsigned(s_time_out_cnt_reg) - 1;
|
| 582 |
|
|
END IF;
|
| 583 |
|
|
END IF;
|
| 584 |
|
|
END PROCESS make_time_out_cnt_reg;
|
| 585 |
|
|
|
| 586 |
|
|
--------------------------------------------------------------------------------
|
| 587 |
|
|
--- Here the word to byte handling is defined ---
|
| 588 |
|
|
--------------------------------------------------------------------------------
|
| 589 |
|
|
s_push_lo <= '1' WHEN fifo_full = '0' AND
|
| 590 |
|
|
s_word_bytes_valid_reg(0) = '1' AND
|
| 591 |
|
|
s_delay_counter_reg = "000" ELSE '0';
|
| 592 |
|
|
s_push_hi <= '1' WHEN fifo_full = '0' AND
|
| 593 |
|
|
s_word_bytes_valid_reg = "10" AND
|
| 594 |
|
|
s_delay_counter_reg = "010" ELSE '0';
|
| 595 |
|
|
s_payload_size_cnt_next <= unsigned(s_payload_size_cnt_reg) - 1;
|
| 596 |
|
|
|
| 597 |
|
|
make_word_regs : PROCESS( clock , s_flash_state_reg , s_latch_read_data )
|
| 598 |
|
|
BEGIN
|
| 599 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 600 |
|
|
IF (s_flash_state_reg = IDLE) THEN
|
| 601 |
|
|
s_word_data_reg <= (OTHERS => '0');
|
| 602 |
|
|
s_word_bytes_valid_reg <= (OTHERS => '0');
|
| 603 |
|
|
ELSIF (s_latch_read_data = '1') THEN
|
| 604 |
|
|
s_word_data_reg <= s_flash_data_in;
|
| 605 |
|
|
s_word_bytes_valid_reg <= "11";
|
| 606 |
|
|
ELSIF (s_push_lo = '1') THEN
|
| 607 |
|
|
s_word_bytes_valid_reg(0) <= '0';
|
| 608 |
|
|
ELSIF (s_push_hi = '1') THEN
|
| 609 |
|
|
s_word_bytes_valid_reg(1) <= '0';
|
| 610 |
|
|
END IF;
|
| 611 |
|
|
END IF;
|
| 612 |
|
|
END PROCESS make_word_regs;
|
| 613 |
|
|
|
| 614 |
|
|
make_fifo_read_info_reg : PROCESS( clock , s_flash_state_reg , reset ,
|
| 615 |
|
|
s_push_lo , s_push_hi )
|
| 616 |
|
|
BEGIN
|
| 617 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 618 |
|
|
IF (s_flash_state_reg = IDLE OR
|
| 619 |
|
|
reset = '1') THEN s_fifo_read_info_reg <= "000";
|
| 620 |
|
|
ELSIF ((s_push_lo = '1' OR
|
| 621 |
|
|
s_push_hi = '1') AND
|
| 622 |
|
|
s_fifo_read_info_reg(2) = '0') THEN
|
| 623 |
|
|
s_fifo_read_info_reg <= unsigned(s_fifo_read_info_reg) + 1;
|
| 624 |
|
|
END IF;
|
| 625 |
|
|
END IF;
|
| 626 |
|
|
END PROCESS make_fifo_read_info_reg;
|
| 627 |
|
|
|
| 628 |
|
|
make_payload_size_cnt_reg : PROCESS( clock , s_flash_state_reg ,
|
| 629 |
|
|
s_push_lo , s_push_hi ,
|
| 630 |
|
|
s_payload_size_cnt_next )
|
| 631 |
|
|
BEGIN
|
| 632 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 633 |
|
|
IF (s_flash_state_reg = IDLE) THEN
|
| 634 |
|
|
s_payload_size_cnt_reg <= "01"&X"FFFFF";
|
| 635 |
|
|
ELSIF (s_push_lo = '1' OR
|
| 636 |
|
|
s_push_hi = '1') THEN
|
| 637 |
|
|
CASE (s_fifo_read_info_reg) IS
|
| 638 |
|
|
WHEN "000" => s_payload_size_cnt_reg( 7 DOWNTO 0 ) <=
|
| 639 |
|
|
s_word_data_reg( 7 DOWNTO 0 );
|
| 640 |
|
|
WHEN "001" => s_payload_size_cnt_reg( 15 DOWNTO 8 ) <=
|
| 641 |
|
|
s_word_data_reg(15 DOWNTO 8 );
|
| 642 |
|
|
WHEN "010" => s_payload_size_cnt_reg( 21 DOWNTO 16 ) <=
|
| 643 |
|
|
"0"&s_word_data_reg( 4 DOWNTO 0 );
|
| 644 |
|
|
WHEN OTHERS => s_payload_size_cnt_reg <= s_payload_size_cnt_next;
|
| 645 |
|
|
END CASE;
|
| 646 |
|
|
END IF;
|
| 647 |
|
|
END IF;
|
| 648 |
|
|
END PROCESS make_payload_size_cnt_reg;
|
| 649 |
|
|
|
| 650 |
|
|
--------------------------------------------------------------------------------
|
| 651 |
|
|
--- Here the addresses are defined ---
|
| 652 |
|
|
--------------------------------------------------------------------------------
|
| 653 |
|
|
s_pud_sector_address <= (OTHERS => '1') WHEN s_flash_top_boot_reg = '1' ELSE
|
| 654 |
|
|
(OTHERS => '0');
|
| 655 |
|
|
|
| 656 |
|
|
make_sector_address : PROCESS( clock , s_flash_state_reg ,
|
| 657 |
|
|
s_flash_top_boot_reg , s_next_address ,
|
| 658 |
|
|
s_next_in_sector_addr )
|
| 659 |
|
|
BEGIN
|
| 660 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 661 |
|
|
IF (s_flash_state_reg = RESET_STATE) THEN
|
| 662 |
|
|
s_sector_address_reg <= (OTHERS => '0');
|
| 663 |
|
|
ELSIF (s_flash_state_reg = RESET_AUTO OR
|
| 664 |
|
|
s_flash_state_reg = IDLE) THEN
|
| 665 |
|
|
s_sector_address_reg(20 DOWNTO 17) <= (OTHERS => '0');
|
| 666 |
|
|
s_sector_address_reg(16) <= NOT(s_flash_top_boot_reg);
|
| 667 |
|
|
ELSIF ((s_flash_state_reg = INIT_ERASE_S1 AND
|
| 668 |
|
|
s_is_pud_action_reg = '1') OR
|
| 669 |
|
|
s_flash_state_reg = READ_HW) THEN
|
| 670 |
|
|
s_sector_address_reg <= s_pud_sector_address;
|
| 671 |
|
|
ELSIF ((s_next_address = '1' AND
|
| 672 |
|
|
s_next_in_sector_addr(16) = '1') OR
|
| 673 |
|
|
s_flash_state_reg = NEXT_SECTOR) THEN
|
| 674 |
|
|
s_sector_address_reg <= unsigned(s_sector_address_reg) + 1;
|
| 675 |
|
|
END IF;
|
| 676 |
|
|
END IF;
|
| 677 |
|
|
END PROCESS make_sector_address;
|
| 678 |
|
|
|
| 679 |
|
|
make_in_sector_address : PROCESS( clock , s_flash_state_reg ,
|
| 680 |
|
|
s_next_address , s_next_in_sector_addr )
|
| 681 |
|
|
BEGIN
|
| 682 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 683 |
|
|
IF (s_flash_state_reg = RESET_STATE) THEN
|
| 684 |
|
|
s_in_sector_address_reg <= (1=>'1', OTHERS => '0');
|
| 685 |
|
|
ELSIF (s_flash_state_reg = RESET_AUTO OR
|
| 686 |
|
|
s_flash_state_reg = IDLE OR
|
| 687 |
|
|
s_flash_state_reg = INIT_ERASE_S1 OR
|
| 688 |
|
|
s_flash_state_reg = READ_HW) THEN
|
| 689 |
|
|
s_in_sector_address_reg <= (OTHERS => '0');
|
| 690 |
|
|
ELSIF (s_next_address = '1') THEN
|
| 691 |
|
|
s_in_sector_address_reg <= s_next_in_sector_addr( 15 DOWNTO 1 );
|
| 692 |
|
|
END IF;
|
| 693 |
|
|
END IF;
|
| 694 |
|
|
END PROCESS make_in_sector_address;
|
| 695 |
|
|
|
| 696 |
|
|
--------------------------------------------------------------------------------
|
| 697 |
|
|
--- Here the command player is defined ---
|
| 698 |
|
|
--------------------------------------------------------------------------------
|
| 699 |
|
|
make_player_count_reg : PROCESS( clock , s_flash_state_reg ,
|
| 700 |
|
|
s_delay_counter_reg )
|
| 701 |
|
|
BEGIN
|
| 702 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 703 |
|
|
IF (s_flash_state_reg = RESET_STATE OR
|
| 704 |
|
|
s_flash_state_reg = INIT_ERASE_S1 OR
|
| 705 |
|
|
s_flash_state_reg = INIT_WRITE) THEN
|
| 706 |
|
|
s_player_count_reg <= "001";
|
| 707 |
|
|
ELSIF (s_flash_state_reg = CHECK_ID) THEN
|
| 708 |
|
|
s_player_count_reg <= "011";
|
| 709 |
|
|
ELSIF (s_delay_counter_reg(2) = '1') THEN
|
| 710 |
|
|
CASE (s_player_count_reg) IS
|
| 711 |
|
|
WHEN "000" => NULL;
|
| 712 |
|
|
WHEN "011" => IF (s_flash_state_reg = SET_AUTOSELECT OR
|
| 713 |
|
|
s_flash_state_reg = RESET_AUTO OR
|
| 714 |
|
|
s_flash_state_reg = PLAY_WRITE) THEN
|
| 715 |
|
|
s_player_count_reg <= "000";
|
| 716 |
|
|
ELSE
|
| 717 |
|
|
s_player_count_reg <= "101";
|
| 718 |
|
|
END IF;
|
| 719 |
|
|
WHEN OTHERS => s_player_count_reg <= unsigned(s_player_count_reg) + 1;
|
| 720 |
|
|
END CASE;
|
| 721 |
|
|
END IF;
|
| 722 |
|
|
END IF;
|
| 723 |
|
|
END PROCESS make_player_count_reg;
|
| 724 |
|
|
|
| 725 |
|
|
make_command_byte : PROCESS( s_flash_state_reg , s_player_count_reg )
|
| 726 |
|
|
BEGIN
|
| 727 |
|
|
CASE (s_flash_state_reg) IS
|
| 728 |
|
|
WHEN SET_AUTOSELECT => s_command_byte <= X"90";
|
| 729 |
|
|
WHEN RESET_AUTO => s_command_byte <= X"F0";
|
| 730 |
|
|
WHEN ERASE_S1 => IF (s_player_count_reg(2) = '0') THEN
|
| 731 |
|
|
s_command_byte <= X"80";
|
| 732 |
|
|
ELSE
|
| 733 |
|
|
s_command_byte <= X"30";
|
| 734 |
|
|
END IF;
|
| 735 |
|
|
WHEN PLAY_WRITE => s_command_byte <= X"A0";
|
| 736 |
|
|
WHEN OTHERS => s_command_byte <= X"00";
|
| 737 |
|
|
END CASE;
|
| 738 |
|
|
END PROCESS make_command_byte;
|
| 739 |
|
|
|
| 740 |
|
|
--------------------------------------------------------------------------------
|
| 741 |
|
|
--- Here the delay counter is defined ---
|
| 742 |
|
|
--------------------------------------------------------------------------------
|
| 743 |
|
|
make_delay_counter : PROCESS( clock , reset , s_flash_state_reg ,
|
| 744 |
|
|
s_delay_counter_reg )
|
| 745 |
|
|
BEGIN
|
| 746 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 747 |
|
|
IF (s_flash_state_reg = IDLE OR
|
| 748 |
|
|
s_delay_counter_reg(2) = '1' OR
|
| 749 |
|
|
reset = '1') THEN s_delay_counter_reg <= "000";
|
| 750 |
|
|
ELSE
|
| 751 |
|
|
s_delay_counter_reg <= unsigned(s_delay_counter_reg) + 1;
|
| 752 |
|
|
END IF;
|
| 753 |
|
|
END IF;
|
| 754 |
|
|
END PROCESS make_delay_counter;
|
| 755 |
|
|
|
| 756 |
|
|
--------------------------------------------------------------------------------
|
| 757 |
|
|
--- Here the flash id regs are defined ---
|
| 758 |
|
|
--------------------------------------------------------------------------------
|
| 759 |
|
|
make_flash_mt_regs : PROCESS( clock , s_flash_state_reg , s_flash_data_in )
|
| 760 |
|
|
BEGIN
|
| 761 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 762 |
|
|
IF (reset = '1') THEN s_flash_mounted_reg <= '0';
|
| 763 |
|
|
s_flash_top_boot_reg <= '0';
|
| 764 |
|
|
ELSIF (s_flash_state_reg = CHECK_ID) THEN
|
| 765 |
|
|
CASE (s_flash_data_in) IS
|
| 766 |
|
|
WHEN X"22C4" => s_flash_mounted_reg <= '1';
|
| 767 |
|
|
s_flash_top_boot_reg <= '1';
|
| 768 |
|
|
WHEN X"2249" => s_flash_mounted_reg <= '1';
|
| 769 |
|
|
s_flash_top_boot_reg <= '0';
|
| 770 |
|
|
WHEN OTHERS => s_flash_mounted_reg <= '0';
|
| 771 |
|
|
s_flash_top_boot_reg <= '0';
|
| 772 |
|
|
END CASE;
|
| 773 |
|
|
END IF;
|
| 774 |
|
|
END IF;
|
| 775 |
|
|
END PROCESS make_flash_mt_regs;
|
| 776 |
|
|
|
| 777 |
|
|
make_flash_sec1_empty_reg : PROCESS( clock , s_flash_state_reg ,
|
| 778 |
|
|
s_flash_data_in )
|
| 779 |
|
|
BEGIN
|
| 780 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 781 |
|
|
IF (reset = '1' OR
|
| 782 |
|
|
(s_flash_state_reg = WRITE_UPDATE AND
|
| 783 |
|
|
s_is_pud_action_reg = '0')) THEN s_flash_sec1_empty_reg <= '0';
|
| 784 |
|
|
ELSIF (s_flash_state_reg = CHECK_HW) THEN
|
| 785 |
|
|
IF (s_flash_data_in = X"FFFF") THEN s_flash_sec1_empty_reg <= '1';
|
| 786 |
|
|
ELSE s_flash_sec1_empty_reg <= '0';
|
| 787 |
|
|
END IF;
|
| 788 |
|
|
ELSIF (s_flash_state_reg = INIT_ERASE_S1 AND
|
| 789 |
|
|
s_is_pud_action_reg = '0') THEN
|
| 790 |
|
|
s_flash_sec1_empty_reg <= '1';
|
| 791 |
|
|
END IF;
|
| 792 |
|
|
END IF;
|
| 793 |
|
|
END PROCESS make_flash_sec1_empty_reg;
|
| 794 |
|
|
|
| 795 |
|
|
--------------------------------------------------------------------------------
|
| 796 |
|
|
--- Here the write signals are defined ---
|
| 797 |
|
|
--------------------------------------------------------------------------------
|
| 798 |
|
|
s_write_size <= '1' WHEN s_flash_state_reg = INIT_WRITE AND
|
| 799 |
|
|
s_write_idx_reg(1) = '0' AND
|
| 800 |
|
|
s_state_tick = '1' AND
|
| 801 |
|
|
s_is_pud_action_reg = '0' ELSE '0';
|
| 802 |
|
|
s_write_data <= '1' WHEN s_flash_state_reg = INIT_WRITE AND
|
| 803 |
|
|
s_write_idx_reg(1) = '1' AND
|
| 804 |
|
|
s_state_tick = '1' AND
|
| 805 |
|
|
s_fifo_word_valid_reg(1) = '1' AND
|
| 806 |
|
|
s_is_pud_action_reg = '0' ELSE '0';
|
| 807 |
|
|
|
| 808 |
|
|
make_write_done_reg : PROCESS( clock , reset , s_write_data ,
|
| 809 |
|
|
s_flash_state_reg , s_last_byte_reg )
|
| 810 |
|
|
BEGIN
|
| 811 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 812 |
|
|
IF (s_flash_state_reg = WRITE_UPDATE OR
|
| 813 |
|
|
reset = '1') THEN s_write_done_reg <= '0';
|
| 814 |
|
|
ELSIF (s_write_data = '1') THEN s_write_done_reg <= s_last_byte_reg;
|
| 815 |
|
|
ELSIF (s_write_pud = '1') THEN
|
| 816 |
|
|
s_write_done_reg <= s_next_in_sector_addr(11);
|
| 817 |
|
|
END IF;
|
| 818 |
|
|
END IF;
|
| 819 |
|
|
END PROCESS make_write_done_reg;
|
| 820 |
|
|
|
| 821 |
|
|
|
| 822 |
|
|
make_write_idx_reg : PROCESS( clock , s_flash_state_reg )
|
| 823 |
|
|
BEGIN
|
| 824 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 825 |
|
|
IF (s_flash_state_reg = IDLE) THEN
|
| 826 |
|
|
s_write_idx_reg <= "00";
|
| 827 |
|
|
ELSIF (s_write_size = '1') THEN
|
| 828 |
|
|
s_write_idx_reg <= unsigned(s_write_idx_reg) + 1;
|
| 829 |
|
|
END IF;
|
| 830 |
|
|
END IF;
|
| 831 |
|
|
END PROCESS make_write_idx_reg;
|
| 832 |
|
|
|
| 833 |
|
|
make_write_data_reg : PROCESS( clock , s_fifo_pop , s_write_size ,
|
| 834 |
|
|
s_write_idx_reg )
|
| 835 |
|
|
BEGIN
|
| 836 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 837 |
|
|
IF (s_is_pud_action_reg = '1') THEN s_write_data_reg <= s_pud_word;
|
| 838 |
|
|
ELSIF (s_write_size = '1' OR
|
| 839 |
|
|
s_write_data = '1') THEN
|
| 840 |
|
|
CASE (s_write_idx_reg) IS
|
| 841 |
|
|
WHEN "00" => s_write_data_reg <= bitfile_size(15 DOWNTO 0);
|
| 842 |
|
|
WHEN "01" => s_write_data_reg <= bitfile_size(31 DOWNTO 16);
|
| 843 |
|
|
WHEN OTHERS => s_write_data_reg <= s_fifo_word_reg;
|
| 844 |
|
|
END CASE;
|
| 845 |
|
|
END IF;
|
| 846 |
|
|
END IF;
|
| 847 |
|
|
END PROCESS make_write_data_reg;
|
| 848 |
|
|
|
| 849 |
|
|
--------------------------------------------------------------------------------
|
| 850 |
|
|
--- Here the write fifo interface is defined ---
|
| 851 |
|
|
--------------------------------------------------------------------------------
|
| 852 |
|
|
s_fifo_pop <= '1' WHEN s_fifo_empty = '0' AND
|
| 853 |
|
|
s_fifo_word_valid_reg(1) = '0' AND
|
| 854 |
|
|
s_last_byte_reg = '0' ELSE '0';
|
| 855 |
|
|
|
| 856 |
|
|
|
| 857 |
|
|
make_fifo_word_reg : PROCESS( clock , s_fifo_reset , s_fifo_pop ,
|
| 858 |
|
|
s_fifo_pop_data , s_fifo_word_valid_reg ,
|
| 859 |
|
|
s_write_data )
|
| 860 |
|
|
VARIABLE v_select : std_logic_vector( 2 DOWNTO 0 );
|
| 861 |
|
|
BEGIN
|
| 862 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 863 |
|
|
IF (s_fifo_reset = '1' OR
|
| 864 |
|
|
s_write_data = '1') THEN s_fifo_word_valid_reg <= "00";
|
| 865 |
|
|
s_fifo_word_reg <= (OTHERS => '0');
|
| 866 |
|
|
ELSIF (s_fifo_pop = '1') THEN
|
| 867 |
|
|
IF (s_fifo_word_valid_reg = "00" AND
|
| 868 |
|
|
s_fifo_pop_last = '1') THEN
|
| 869 |
|
|
s_fifo_word_valid_reg <= "11";
|
| 870 |
|
|
s_fifo_word_reg <= X"FF"&s_fifo_pop_data;
|
| 871 |
|
|
ELSE
|
| 872 |
|
|
s_fifo_word_reg <= s_fifo_pop_data&s_fifo_word_reg(15 DOWNTO 8);
|
| 873 |
|
|
s_fifo_word_valid_reg <= s_fifo_word_valid_reg(0)&"1";
|
| 874 |
|
|
END IF;
|
| 875 |
|
|
END IF;
|
| 876 |
|
|
END IF;
|
| 877 |
|
|
END PROCESS make_fifo_word_reg;
|
| 878 |
|
|
|
| 879 |
|
|
make_last_byte_reg : PROCESS( clock , s_fifo_pop ,
|
| 880 |
|
|
s_fifo_pop_last , s_flash_state_reg )
|
| 881 |
|
|
BEGIN
|
| 882 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 883 |
|
|
IF (s_flash_state_reg = IDLE) THEN s_last_byte_reg <= '0';
|
| 884 |
|
|
ELSIF (s_fifo_pop = '1' AND
|
| 885 |
|
|
s_fifo_pop_last = '1') THEN s_last_byte_reg <= '1';
|
| 886 |
|
|
END IF;
|
| 887 |
|
|
END IF;
|
| 888 |
|
|
END PROCESS make_last_byte_reg;
|
| 889 |
|
|
|
| 890 |
|
|
|
| 891 |
|
|
write_fifo : fifo_2kb
|
| 892 |
|
|
PORT MAP ( clock => clock,
|
| 893 |
|
|
reset => s_fifo_reset,
|
| 894 |
|
|
-- push port
|
| 895 |
|
|
push => we_fifo,
|
| 896 |
|
|
push_data => we_data,
|
| 897 |
|
|
push_size => we_last,
|
| 898 |
|
|
-- pop port
|
| 899 |
|
|
pop => s_fifo_pop,
|
| 900 |
|
|
pop_data => s_fifo_pop_data,
|
| 901 |
|
|
pop_size => s_fifo_pop_last,
|
| 902 |
|
|
-- control port
|
| 903 |
|
|
fifo_full => we_fifo_full,
|
| 904 |
|
|
fifo_empty => s_fifo_empty );
|
| 905 |
|
|
|
| 906 |
|
|
--------------------------------------------------------------------------------
|
| 907 |
|
|
--- Here the PUD signals are defined ---
|
| 908 |
|
|
--------------------------------------------------------------------------------
|
| 909 |
|
|
s_write_pud <= '1' WHEN s_flash_state_reg = INIT_WRITE AND
|
| 910 |
|
|
s_state_tick = '1' AND
|
| 911 |
|
|
s_is_pud_action_reg = '1' ELSE '0';
|
| 912 |
|
|
s_start_pud_write <= '1' WHEN start_command = '1' AND
|
| 913 |
|
|
command_id = "0001101" ELSE '0';
|
| 914 |
|
|
s_start_pud_read <= '1' WHEN start_command = '1' AND
|
| 915 |
|
|
command_id = "0001110" ELSE '0';
|
| 916 |
|
|
s_we_pud_byte <= '1' WHEN s_flash_state_reg = DO_PUD_WRITE AND
|
| 917 |
|
|
scpi_empty = '0' ELSE '0';
|
| 918 |
|
|
s_ena_pud_byte <= '1' WHEN s_we_pud_byte = '1' OR
|
| 919 |
|
|
(s_scpi_push = '1' AND
|
| 920 |
|
|
s_flash_state_reg = DO_PUD_READ) ELSE '0';
|
| 921 |
|
|
s_ena_pud_word_read <= (NOT(s_we_pud_byte) AND s_is_pud_action_reg) OR
|
| 922 |
|
|
s_we_pud_payload;
|
| 923 |
|
|
s_scpi_push <= '1' WHEN scpi_full = '0' AND
|
| 924 |
|
|
(s_flash_state_reg = SET_PUD_SIZE_1 OR
|
| 925 |
|
|
s_flash_state_reg = SET_PUD_SIZE_2 OR
|
| 926 |
|
|
(s_flash_state_reg = DO_PUD_READ AND
|
| 927 |
|
|
s_pud_byte_addr_reg(11) = '0')) ELSE '0';
|
| 928 |
|
|
s_scpi_n_reset <= '0' WHEN s_flash_state_reg = DO_PUD_READ ELSE '1';
|
| 929 |
|
|
s_we_pud_payload <= '1' WHEN s_flash_state_reg = COPY_PUD_DATA AND
|
| 930 |
|
|
s_delay_counter_reg = "000" ELSE '0';
|
| 931 |
|
|
|
| 932 |
|
|
make_scpi_push : PROCESS( clock , s_scpi_push )
|
| 933 |
|
|
BEGIN
|
| 934 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 935 |
|
|
scpi_push <= s_scpi_push;
|
| 936 |
|
|
IF (s_scpi_push = '1' AND
|
| 937 |
|
|
s_flash_state_reg = SET_PUD_SIZE_2) THEN
|
| 938 |
|
|
s_pud_size_value <= X"08";
|
| 939 |
|
|
ELSE
|
| 940 |
|
|
s_pud_size_value <= X"00";
|
| 941 |
|
|
END IF;
|
| 942 |
|
|
IF (s_scpi_push = '1' AND
|
| 943 |
|
|
(s_flash_state_reg = SET_PUD_SIZE_1 OR
|
| 944 |
|
|
s_flash_state_reg = SET_PUD_SIZE_2)) THEN
|
| 945 |
|
|
scpi_push_size <= '1';
|
| 946 |
|
|
ELSE
|
| 947 |
|
|
scpi_push_size <= '0';
|
| 948 |
|
|
END IF;
|
| 949 |
|
|
END IF;
|
| 950 |
|
|
END PROCESS make_scpi_push;
|
| 951 |
|
|
|
| 952 |
|
|
make_is_pud_action_reg : PROCESS( clock , reset , s_start_pud_write ,
|
| 953 |
|
|
s_flash_state_reg )
|
| 954 |
|
|
BEGIN
|
| 955 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 956 |
|
|
IF (s_start_pud_write = '1') THEN
|
| 957 |
|
|
s_is_pud_action_reg <= '1';
|
| 958 |
|
|
ELSIF (reset = '1' OR
|
| 959 |
|
|
s_flash_state_reg = IDLE) THEN s_is_pud_action_reg <= '0';
|
| 960 |
|
|
END IF;
|
| 961 |
|
|
END IF;
|
| 962 |
|
|
END PROCESS make_is_pud_action_reg;
|
| 963 |
|
|
|
| 964 |
|
|
make_pud_byte_addr_reg : PROCESS( clock , reset , s_flash_state_reg ,
|
| 965 |
|
|
s_ena_pud_byte )
|
| 966 |
|
|
BEGIN
|
| 967 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 968 |
|
|
IF (s_flash_state_reg = IDLE OR
|
| 969 |
|
|
reset = '1') THEN s_pud_byte_addr_reg <= (OTHERS => '0');
|
| 970 |
|
|
ELSIF (s_ena_pud_byte = '1') THEN
|
| 971 |
|
|
s_pud_byte_addr_reg <= unsigned(s_pud_byte_addr_reg) + 1;
|
| 972 |
|
|
END IF;
|
| 973 |
|
|
END IF;
|
| 974 |
|
|
END PROCESS make_pud_byte_addr_reg;
|
| 975 |
|
|
|
| 976 |
|
|
make_pud_word_address_reg : PROCESS( clock , s_flash_state_reg , reset ,
|
| 977 |
|
|
s_next_address , s_next_in_sector_addr )
|
| 978 |
|
|
BEGIN
|
| 979 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 980 |
|
|
IF (s_flash_state_reg = IDLE OR
|
| 981 |
|
|
reset = '1') THEN s_pud_word_address_reg <= (OTHERS => '0');
|
| 982 |
|
|
ELSIF (s_next_address = '1' AND
|
| 983 |
|
|
s_is_pud_action_reg = '1') THEN
|
| 984 |
|
|
s_pud_word_address_reg <= s_next_in_sector_addr( 10 DOWNTO 1 );
|
| 985 |
|
|
ELSIF (s_pud_hi_reg = '1') THEN
|
| 986 |
|
|
s_pud_word_address_reg <= s_in_sector_address_reg( 10 DOWNTO 1 );
|
| 987 |
|
|
END IF;
|
| 988 |
|
|
END IF;
|
| 989 |
|
|
END PROCESS make_pud_word_address_reg;
|
| 990 |
|
|
|
| 991 |
|
|
s_we_vga <= '1' WHEN (s_we_pud_byte = '1' AND
|
| 992 |
|
|
unsigned(s_pud_byte_addr_reg( 10 DOWNTO 6)) >
|
| 993 |
|
|
unsigned(c_vga_offset)) OR
|
| 994 |
|
|
((s_pud_hi_reg = '1' OR
|
| 995 |
|
|
s_we_pud_payload = '1') AND
|
| 996 |
|
|
unsigned(s_pud_word_address_reg( 9 DOWNTO 5 )) >
|
| 997 |
|
|
unsigned(c_vga_offset)) ELSE '0';
|
| 998 |
|
|
s_we_addr(10 DOWNTO 8) <= unsigned(s_pud_byte_addr_reg( 9 DOWNTO 7 )) - 1
|
| 999 |
|
|
WHEN s_we_pud_byte = '1' ELSE
|
| 1000 |
|
|
unsigned(s_pud_word_address_reg( 8 DOWNTO 6 )) - 1;
|
| 1001 |
|
|
s_we_addr(7) <= s_pud_byte_addr_reg(6)
|
| 1002 |
|
|
WHEN s_we_pud_byte = '1' ELSE
|
| 1003 |
|
|
s_pud_word_address_reg(5);
|
| 1004 |
|
|
s_we_addr(6) <= '1';
|
| 1005 |
|
|
s_we_addr( 5 DOWNTO 0) <= s_pud_byte_addr_reg( 5 DOWNTO 0 )
|
| 1006 |
|
|
WHEN s_we_pud_byte = '1' ELSE
|
| 1007 |
|
|
s_pud_word_address_reg(4 DOWNTO 0)&s_pud_hi_reg;
|
| 1008 |
|
|
s_we_data <= scpi_pop_data WHEN s_we_pud_byte = '1' ELSE
|
| 1009 |
|
|
s_flash_data_in( 7 DOWNTO 0)
|
| 1010 |
|
|
WHEN s_pud_hi_reg = '0' ELSE
|
| 1011 |
|
|
s_flash_data_in(15 DOWNTO 8) ;
|
| 1012 |
|
|
|
| 1013 |
|
|
make_vga_signals : PROCESS( clock )
|
| 1014 |
|
|
BEGIN
|
| 1015 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 1016 |
|
|
we_char <= s_we_vga;
|
| 1017 |
|
|
we_ascii <= s_we_data;
|
| 1018 |
|
|
we_addr <= s_we_addr;
|
| 1019 |
|
|
END IF;
|
| 1020 |
|
|
END PROCESS make_vga_signals;
|
| 1021 |
|
|
|
| 1022 |
|
|
make_pud_hi_reg : PROCESS( clock )
|
| 1023 |
|
|
BEGIN
|
| 1024 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 1025 |
|
|
s_pud_hi_reg <= s_we_pud_payload;
|
| 1026 |
|
|
END IF;
|
| 1027 |
|
|
END PROCESS make_pud_hi_reg;
|
| 1028 |
|
|
|
| 1029 |
|
|
|
| 1030 |
|
|
|
| 1031 |
|
|
pud_buffer : RAMB16_S9_S18
|
| 1032 |
|
|
PORT MAP ( DOA => s_pud_byte,
|
| 1033 |
|
|
DOPA => OPEN,
|
| 1034 |
|
|
ADDRA => s_pud_byte_addr_reg( 10 DOWNTO 0 ),
|
| 1035 |
|
|
CLKA => clock,
|
| 1036 |
|
|
DIA => scpi_pop_data,
|
| 1037 |
|
|
DIPA => "0",
|
| 1038 |
|
|
ENA => '1',
|
| 1039 |
|
|
SSRA => s_scpi_n_reset,
|
| 1040 |
|
|
WEA => s_we_pud_byte,
|
| 1041 |
|
|
DOB => s_pud_word,
|
| 1042 |
|
|
DOPB => OPEN,
|
| 1043 |
|
|
ADDRB => s_pud_word_address_reg,
|
| 1044 |
|
|
CLKB => clock,
|
| 1045 |
|
|
DIB => s_flash_data_in,
|
| 1046 |
|
|
DIPB => "00",
|
| 1047 |
|
|
ENB => s_ena_pud_word_read,
|
| 1048 |
|
|
SSRB => '0',
|
| 1049 |
|
|
WEB => s_we_pud_payload );
|
| 1050 |
|
|
|
| 1051 |
|
|
make_busy_pipe_reg : PROCESS( clock , reset , flash_ready_n_busy )
|
| 1052 |
|
|
BEGIN
|
| 1053 |
|
|
IF (clock'event AND (clock = '1')) THEN
|
| 1054 |
|
|
IF (reset = '1') THEN s_busy_pipe_reg <= X"0";
|
| 1055 |
|
|
ELSE
|
| 1056 |
|
|
s_busy_pipe_reg( 2 DOWNTO 0 ) <= s_busy_pipe_reg(1 DOWNTO 0)&flash_ready_n_busy;
|
| 1057 |
|
|
IF (s_busy_pipe_reg( 2 DOWNTO 0 ) = "000") THEN s_busy_pipe_reg(3) <= '0';
|
| 1058 |
|
|
ELSIF (s_busy_pipe_reg( 2 DOWNTO 0 ) = "111") THEN s_busy_pipe_reg(3) <= '1';
|
| 1059 |
|
|
END IF;
|
| 1060 |
|
|
END IF;
|
| 1061 |
|
|
END IF;
|
| 1062 |
|
|
END PROCESS make_busy_pipe_reg;
|
| 1063 |
|
|
|
| 1064 |
|
|
--------------------------------------------------------------------------------
|
| 1065 |
|
|
--- Here the IOB flipflops are defined ---
|
| 1066 |
|
|
--------------------------------------------------------------------------------
|
| 1067 |
|
|
address_ffs : FOR n IN 19 DOWNTO 0 GENERATE
|
| 1068 |
|
|
one_ff : FDE
|
| 1069 |
|
|
GENERIC MAP ( INIT => '1')
|
| 1070 |
|
|
PORT MAP ( Q => flash_address(n),
|
| 1071 |
|
|
C => clock,
|
| 1072 |
|
|
CE => s_delay_counter_reg(2),
|
| 1073 |
|
|
D => s_byte_address(n+1) );
|
| 1074 |
|
|
END GENERATE address_ffs;
|
| 1075 |
|
|
|
| 1076 |
|
|
data_in_out_ffs : FOR n IN 15 DOWNTO 0 GENERATE
|
| 1077 |
|
|
in_ff : FDE_1
|
| 1078 |
|
|
GENERIC MAP ( INIT => '1')
|
| 1079 |
|
|
PORT MAP ( Q => s_flash_data_in(n),
|
| 1080 |
|
|
C => clock,
|
| 1081 |
|
|
CE => s_delay_counter_reg(2),
|
| 1082 |
|
|
D => flash_data_in(n) );
|
| 1083 |
|
|
out_ff : FDE
|
| 1084 |
|
|
GENERIC MAP ( INIT => '1')
|
| 1085 |
|
|
PORT MAP ( Q => flash_data_out(n),
|
| 1086 |
|
|
C => clock,
|
| 1087 |
|
|
CE => s_delay_counter_reg(2),
|
| 1088 |
|
|
D => s_data_out_next(n) );
|
| 1089 |
|
|
oe_ff : FDE
|
| 1090 |
|
|
GENERIC MAP ( INIT => '1')
|
| 1091 |
|
|
PORT MAP ( Q => flash_data_oe(n),
|
| 1092 |
|
|
C => clock,
|
| 1093 |
|
|
CE => s_delay_counter_reg(2),
|
| 1094 |
|
|
D => s_tri_data_out );
|
| 1095 |
|
|
END GENERATE data_in_out_ffs;
|
| 1096 |
|
|
|
| 1097 |
|
|
nce_reg : FD
|
| 1098 |
|
|
GENERIC MAP ( INIT => '1')
|
| 1099 |
|
|
PORT MAP ( Q => flash_n_ce,
|
| 1100 |
|
|
C => clock,
|
| 1101 |
|
|
D => s_flash_n_ce );
|
| 1102 |
|
|
noe_reg : FD
|
| 1103 |
|
|
GENERIC MAP ( INIT => '1')
|
| 1104 |
|
|
PORT MAP ( Q => flash_n_oe,
|
| 1105 |
|
|
C => clock,
|
| 1106 |
|
|
D => s_flash_n_oe );
|
| 1107 |
|
|
nwe_reg : FD
|
| 1108 |
|
|
GENERIC MAP ( INIT => '1')
|
| 1109 |
|
|
PORT MAP ( Q => flash_n_we,
|
| 1110 |
|
|
C => clock,
|
| 1111 |
|
|
D => s_flash_n_we );
|
| 1112 |
|
|
END xilinx;
|
