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[/] [generic_booth_multipler/] [trunk/] [rtl/] [modules/] [01.BoothDatapath.vhd] - Blame information for rev 6

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1 2 alimpk 
library IEEE;
2 
use IEEE.STD_LOGIC_1164.ALL;
3 
 
4 
entity BoothDatapath is
5 6 alimpk 
        generic(
6 
                size: integer := 4
7 
        );
8 2 alimpk 
        port(
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                clock :in       std_logic;
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                reset :in std_logic;
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                load :in std_logic;
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                shift :in std_logic;
13 6 alimpk 
                X       : in std_logic_vector(size-1 downto 0);
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                Y       : in std_logic_vector(size-1 downto 0);
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                P       : out std_logic_vector(2*size-1 downto 0));
16 2 alimpk 
end BoothDatapath;
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architecture Behavioral of BoothDatapath is
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        component Regeister is
21 6 alimpk 
                generic (
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                        size: integer := 4
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                );
24 2 alimpk 
                port(
25 6 alimpk 
                        clock :in       std_logic;
26 2 alimpk 
                        enable :in      std_logic;
27 6 alimpk 
                        reset :in       std_logic;
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                        din      :in    std_logic_vector(size-1 downto 0);
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                        dout :out std_logic_vector(size-1 downto 0));
30 2 alimpk 
        end component;
31 
 
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        component LeftShiftReg is
33 6 alimpk 
                generic(
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                        size : integer:= 4
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                );
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                port(
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                        clock    :in    std_logic;
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                        enable :in      std_logic;
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                        shift    :in    std_logic;
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                        din      :in    std_logic_vector(size-1 downto 0);
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                        dout     :out std_logic_vector(size-1 downto 0));
42 2 alimpk 
        end component;
43 
 
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        component RightShiftReg is
45 6 alimpk 
                generic(
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                        size : integer := 4
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                );
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                port(
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                        clock    :in    std_logic;
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                        enable :in      std_logic;
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                        shift    :in    std_logic;
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                        din      :in    std_logic_vector(size-1 downto 0);
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                        dout     :out std_logic_vector(1 downto 0));
54 2 alimpk 
        end component;
55 
        component BoothEncoder is
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                port(
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                        input1  : in    std_logic;
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                        input0  : in    std_logic;
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                        operator        : out std_logic;
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                        product : out   std_logic
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                        );
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        end component;
63 
 
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        component Alu is
65 6 alimpk 
                generic(
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                        size : integer:= 4
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                );
68 2 alimpk 
                port(
69 6 alimpk 
                        A       : in  std_logic_vector(size-1 downto 0);
70 
                        B       : in  std_logic_vector(size-1 downto 0);
71 2 alimpk 
                        op      : in  std_logic;
72 6 alimpk 
                        S       : out std_logic_vector(size-1 downto 0));
73 2 alimpk 
        end component;
74 
        component Ander is
75 6 alimpk 
                generic(
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                        size : integer:= 4
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                );
78 2 alimpk 
                port(
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                        input1 : in      std_logic;
80 6 alimpk 
                        input2 : in  std_logic_vector(size-1 downto 0);
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                        result : out std_logic_vector(size-1 downto 0));
82 2 alimpk 
        end component;
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        signal sign_extended_x,andout,alu_out,p_out,X_reg_dout: std_logic_vector(2*X'length -1 downto 0);
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        signal lessTwoBits : std_logic_vector(1 downto 0);
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        signal operator,product : std_logic;
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        signal Y_concat_zero : std_logic_vector(y'length downto 0);
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begin
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        Y_concat_zero <= Y & '0';
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        sign_extended_x(X'range) <= X;
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        sign_extended_x(sign_extended_x'length - 1 downto X'length) <= (others=> X(X'length-1));
91 
 
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  Booth_ENC: BoothEncoder
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    port map(input1 => lessTwoBits(1),
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      input0=>lessTwoBits(0),
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      operator => operator,
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      product => product);
97 
 
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        Y_REG           : RightShiftReg
99 6 alimpk 
        generic map(size => size+1)
100 2 alimpk 
        port map(
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    clock => clock,
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    enable => load,
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    shift =>shift,
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    din => Y_concat_zero,
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    dout => lessTwoBits);
106 
 
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  X_REG : LeftShiftReg
108 6 alimpk 
  generic map(size => 2*size)
109 2 alimpk 
  port map(
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    clock => clock,
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    enable => load,
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    shift => shift,
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    din => sign_extended_x,
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    dout => X_reg_dout);
115 
 
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  ANDing : Ander
117 6 alimpk 
  generic map(size => 2*size)
118 2 alimpk 
  port map(
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    input1 => product,
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    input2 => X_reg_dout,
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    result => AndOut);
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  Add_Sub : ALU
124 6 alimpk 
  generic map(size => 2*size)
125 2 alimpk 
  port map(
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    A => P_out,
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    B => AndOut,
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    op => operator,
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    S => ALU_Out);
130 
 
131 
  P_REG : Regeister
132 6 alimpk 
  generic map(size => 2*size)
133 2 alimpk 
    port map(
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      clock => clock,
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      enable => shift,
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      reset => reset,
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      din => ALU_Out,
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      dout => P_out);
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  P <= P_out;
140 
 
141 
end Behavioral;
142 
 

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