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[/] [generic_booth_multipler/] [trunk/] [rtl/] [modules/] [01.BoothDatapath.vhd] - Blame information for rev 2

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity BoothDatapath is
        port(
                clock :in       std_logic;
                reset :in std_logic;
                load :in std_logic;
                shift :in std_logic;
                X       : in std_logic_vector;
                Y       : in std_logic_vector;
                P       : out std_logic_vector);
end BoothDatapath;
 
architecture Behavioral of BoothDatapath is
 
        component Regeister is
                port(
                        clock    :in    std_logic;
                        enable :in      std_logic;
                        reset    :in    std_logic;
                        din      :in    std_logic_vector;
                        dout     :out std_logic_vector);
        end component;
 
        component LeftShiftReg is
                        port(
                                clock   :in     std_logic;
                                enable :in      std_logic;
                                shift   :in     std_logic;
                                din      :in    std_logic_vector;
                                dout :out std_logic_vector);
        end component;
 
        component RightShiftReg is
        port(
                        clock   : in std_logic;
                        enable : in std_logic;
                        shift   : in std_logic;
                        din     : in std_logic_vector;
                        dout : out std_logic_vector(1 downto 0));
        end component;
        component BoothEncoder is
                port(
                        input1  : in    std_logic;
                        input0  : in    std_logic;
                        operator        : out std_logic;
                        product : out   std_logic
                        );
        end component;
 
        component Alu is
                port(
                        A       : in  std_logic_vector;
                        B       : in  std_logic_vector;
                        op      : in  std_logic;
                        S       : out std_logic_vector);
        end component;
        component Ander is
                port(
                        input1 : in      std_logic;
                        input2 : in  std_logic_vector;
                        result : out std_logic_vector);
        end component;
        signal sign_extended_x,andout,alu_out,p_out,X_reg_dout: std_logic_vector(2*X'length -1 downto 0);
        signal lessTwoBits : std_logic_vector(1 downto 0);
        signal operator,product : std_logic;
        signal Y_concat_zero : std_logic_vector(y'length downto 0);
begin
        Y_concat_zero <= Y & '0';
        sign_extended_x(X'range) <= X;
        sign_extended_x(sign_extended_x'length - 1 downto X'length) <= (others=> X(X'length-1));
 
  Booth_ENC: BoothEncoder
    port map(input1 => lessTwoBits(1),
      input0=>lessTwoBits(0),
      operator => operator,
      product => product);
 
        Y_REG           : RightShiftReg
        port map(
    clock => clock,
    enable => load,
    shift =>shift,
    din => Y_concat_zero,
    dout => lessTwoBits);
 
  X_REG : LeftShiftReg
  port map(
    clock => clock,
    enable => load,
    shift => shift,
    din => sign_extended_x,
    dout => X_reg_dout);
 
  ANDing : Ander
  port map(
    input1 => product,
    input2 => X_reg_dout,
    result => AndOut);
 
  Add_Sub : ALU
  port map(
    A => P_out,
    B => AndOut,
    op => operator,
    S => ALU_Out);
 
  P_REG : Regeister
    port map(
      clock => clock,
      enable => shift,
      reset => reset,
      din => ALU_Out,
      dout => P_out);
  P <= P_out;
 
end Behavioral;
 

Line No.	Rev	Author	Line
1	2	alimpk	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3
4			`entity BoothDatapath is`
5			`port(`
6			`clock :in std_logic;`
7			`reset :in std_logic;`
8			`load :in std_logic;`
9			`shift :in std_logic;`
10			`X : in std_logic_vector;`
11			`Y : in std_logic_vector;`
12			`P : out std_logic_vector);`
13			`end BoothDatapath;`
14
15			`architecture Behavioral of BoothDatapath is`
16
17			`component Regeister is`
18			`port(`
19			`clock :in std_logic;`
20			`enable :in std_logic;`
21			`reset :in std_logic;`
22			`din :in std_logic_vector;`
23			`dout :out std_logic_vector);`
24			`end component;`
25
26			`component LeftShiftReg is`
27			`port(`
28			`clock :in std_logic;`
29			`enable :in std_logic;`
30			`shift :in std_logic;`
31			`din :in std_logic_vector;`
32			`dout :out std_logic_vector);`
33			`end component;`
34
35			`component RightShiftReg is`
36			`port(`
37			`clock : in std_logic;`
38			`enable : in std_logic;`
39			`shift : in std_logic;`
40			`din : in std_logic_vector;`
41			`dout : out std_logic_vector(1 downto 0));`
42			`end component;`
43			`component BoothEncoder is`
44			`port(`
45			`input1 : in std_logic;`
46			`input0 : in std_logic;`
47			`operator : out std_logic;`
48			`product : out std_logic`
49			`);`
50			`end component;`
51
52			`component Alu is`
53			`port(`
54			`A : in std_logic_vector;`
55			`B : in std_logic_vector;`
56			`op : in std_logic;`
57			`S : out std_logic_vector);`
58			`end component;`
59			`component Ander is`
60			`port(`
61			`input1 : in std_logic;`
62			`input2 : in std_logic_vector;`
63			`result : out std_logic_vector);`
64			`end component;`
65			`signal sign_extended_x,andout,alu_out,p_out,X_reg_dout: std_logic_vector(2*X'length -1 downto 0);`
66			`signal lessTwoBits : std_logic_vector(1 downto 0);`
67			`signal operator,product : std_logic;`
68			`signal Y_concat_zero : std_logic_vector(y'length downto 0);`
69			`begin`
70			`Y_concat_zero <= Y & '0';`
71			`sign_extended_x(X'range) <= X;`
72			`sign_extended_x(sign_extended_x'length - 1 downto X'length) <= (others=> X(X'length-1));`
73
74			`Booth_ENC: BoothEncoder`
75			`port map(input1 => lessTwoBits(1),`
76			`input0=>lessTwoBits(0),`
77			`operator => operator,`
78			`product => product);`
79
80			`Y_REG : RightShiftReg`
81			`port map(`
82			`clock => clock,`
83			`enable => load,`
84			`shift =>shift,`
85			`din => Y_concat_zero,`
86			`dout => lessTwoBits);`
87
88			`X_REG : LeftShiftReg`
89			`port map(`
90			`clock => clock,`
91			`enable => load,`
92			`shift => shift,`
93			`din => sign_extended_x,`
94			`dout => X_reg_dout);`
95
96			`ANDing : Ander`
97			`port map(`
98			`input1 => product,`
99			`input2 => X_reg_dout,`
100			`result => AndOut);`
101
102			`Add_Sub : ALU`
103			`port map(`
104			`A => P_out,`
105			`B => AndOut,`
106			`op => operator,`
107			`S => ALU_Out);`
108
109			`P_REG : Regeister`
110			`port map(`
111			`clock => clock,`
112			`enable => shift,`
113			`reset => reset,`
114			`din => ALU_Out,`
115			`dout => P_out);`
116			`P <= P_out;`
117
118			`end Behavioral;`
119

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[/] [generic_booth_multipler/] [trunk/] [rtl/] [modules/] [01.BoothDatapath.vhd] - Blame information for rev 2