Subversion Repositories genesys_ddr2

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//   ____  ____

//  /   /\/   /

// /___/  \  /    Vendor: Xilinx

// \   \   \/     Version: 3.6.1

//  \   \         Application: MIG

//  /   /         Filename: ddr2_phy_dm_iob.v

// /___/   /\     Date Last Modified: $Date: 2010/11/26 18:26:02 $

// \   \  /  \    Date Created: Wed Aug 16 2006

//  \___\/\___\

//

//Device: Virtex-5

//Design Name: DDR2

//Purpose:

//   This module places the data mask signals into the IOBs.

//Reference:

//Revision History:

//   Rev 1.1 - To fix timing issues with Synplicity 9.6.1, syn_preserve 

//             attribute added for the instance u_dm_ce. PK. 11/11/08

//*****************************************************************************

`timescale 1ns/1ps

module ddr2_phy_dm_iob

  (

   input  clk90,

   input  dm_ce,

   input  mask_data_rise,

   input  mask_data_fall,

   output ddr_dm

   );

  wire    dm_out;

  wire    dm_ce_r;

  FDRSE_1 u_dm_ce

    (

     .Q    (dm_ce_r),

     .C    (clk90),

     .CE   (1'b1),

     .D    (dm_ce),

     .R   (1'b0),

     .S   (1'b0)

     ) /* synthesis syn_preserve=1 */;

  ODDR #

    (

     .SRTYPE("SYNC"),

     .DDR_CLK_EDGE("SAME_EDGE")

     )

    u_oddr_dm

      (

       .Q  (dm_out),

       .C  (clk90),

       .CE (dm_ce_r),

       .D1 (mask_data_rise),

       .D2 (mask_data_fall),

       .R  (1'b0),

       .S  (1'b0)

       );

  OBUF u_obuf_dm

    (

     .I (dm_out),

     .O (ddr_dm)

     );

endmodule