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//*****************************************************************************
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// DISCLAIMER OF LIABILITY
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//
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// This file contains proprietary and confidential information of
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// Xilinx, Inc. ("Xilinx"), that is distributed under a license
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// from Xilinx, and may be used, copied and/or disclosed only
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// pursuant to the terms of a valid license agreement with Xilinx.
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//
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// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
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// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
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// does not warrant that functions included in the Materials will
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// meet the requirements of Licensee, or that the operation of the
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// Materials will be uninterrupted or error-free, or that defects
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// in the Materials will be corrected. Furthermore, Xilinx does
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// not warrant or make any representations regarding use, or the
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// results of the use, of the Materials in terms of correctness,
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// accuracy, reliability or otherwise.
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//
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// Xilinx products are not designed or intended to be fail-safe,
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// or for use in any application requiring fail-safe performance,
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// such as life-support or safety devices or systems, Class III
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// medical devices, nuclear facilities, applications related to
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// the deployment of airbags, or any other applications that could
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// lead to death, personal injury or severe property or
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// environmental damage (individually and collectively, "critical
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// applications"). Customer assumes the sole risk and liability
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// of any use of Xilinx products in critical applications,
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// subject only to applicable laws and regulations governing
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// limitations on product liability.
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//
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// Copyright 2006, 2007, 2008 Xilinx, Inc.
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// All rights reserved.
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//
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// This disclaimer and copyright notice must be retained as part
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// of this file at all times.
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: 3.6.1
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// \ \ Application: MIG
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// / / Filename: ddr2_phy_top.v
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// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
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// \ \ / \ Date Created: Wed Aug 16 2006
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// \___\/\___\
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//
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//Device: Virtex-5
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//Design Name: DDR2
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//Purpose:
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// Top-level for memory physical layer (PHY) interface
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//Reference:
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//Revision History:
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// Rev 1.1 - Parameter USE_DM_PORT added. PK. 6/25/08
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// Rev 1.2 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08
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// Rev 1.3 - Parameter CS_BITS added. PK. 10/8/08
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// Rev 1.4 - Parameter IODELAY_GRP added. PK. 11/27/08
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//*****************************************************************************
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`timescale 1ns/1ps
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(* X_CORE_INFO = "mig_v3_61_ddr2_sdram_v5, Coregen 12.4" , CORE_GENERATION_INFO = "ddr2_sdram_v5,mig_v3_61,{component_name=ddr2_phy_top, BANK_WIDTH=2, CKE_WIDTH=1, CLK_WIDTH=2, COL_WIDTH=10, CS_NUM=1, CS_WIDTH=1, DM_WIDTH=8, DQ_WIDTH=64, DQ_PER_DQS=8, DQS_WIDTH=8, ODT_WIDTH=1, ROW_WIDTH=13, ADDITIVE_LAT=0, BURST_LEN=4, BURST_TYPE=0, CAS_LAT=3, ECC_ENABLE=0, MULTI_BANK_EN=1, TWO_T_TIME_EN=1, ODT_TYPE=1, REDUCE_DRV=0, REG_ENABLE=0, TREFI_NS=7800, TRAS=40000, TRCD=15000, TRFC=105000, TRP=15000, TRTP=7500, TWR=15000, TWTR=7500, CLK_PERIOD=8000, RST_ACT_LOW=1, INTERFACE_TYPE=DDR2_SDRAM, LANGUAGE=Verilog, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1}" *)
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module ddr2_phy_top #
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(
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// Following parameters are for 72-bit RDIMM design (for ML561 Reference
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// board design). Actual values may be different. Actual parameters values
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// are passed from design top module MEMCtrl module. Please refer to
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// the MEMCtrl module for actual values.
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parameter BANK_WIDTH = 2,
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parameter CLK_WIDTH = 1,
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parameter CKE_WIDTH = 1,
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parameter COL_WIDTH = 10,
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parameter CS_BITS = 0,
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parameter CS_NUM = 1,
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parameter CS_WIDTH = 1,
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parameter USE_DM_PORT = 1,
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parameter DM_WIDTH = 9,
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parameter DQ_WIDTH = 72,
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parameter DQ_BITS = 7,
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parameter DQ_PER_DQS = 8,
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parameter DQS_WIDTH = 9,
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parameter DQS_BITS = 4,
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parameter HIGH_PERFORMANCE_MODE = "TRUE",
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parameter IODELAY_GRP = "IODELAY_MIG",
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parameter ODT_WIDTH = 1,
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parameter ROW_WIDTH = 14,
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parameter ADDITIVE_LAT = 0,
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parameter TWO_T_TIME_EN = 0,
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parameter BURST_LEN = 4,
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parameter BURST_TYPE = 0,
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parameter CAS_LAT = 5,
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parameter TWR = 15000,
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parameter ECC_ENABLE = 0,
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parameter ODT_TYPE = 1,
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parameter DDR_TYPE = 1,
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parameter REDUCE_DRV = 0,
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parameter REG_ENABLE = 1,
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parameter CLK_PERIOD = 3000,
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parameter SIM_ONLY = 0,
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parameter DEBUG_EN = 0,
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parameter FPGA_SPEED_GRADE = 2
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)
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(
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input clk0,
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input clk90,
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input clkdiv0,
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input rst0,
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input rst90,
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input rstdiv0,
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input ctrl_wren,
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input [ROW_WIDTH-1:0] ctrl_addr,
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input [BANK_WIDTH-1:0] ctrl_ba,
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input ctrl_ras_n,
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input ctrl_cas_n,
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input ctrl_we_n,
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input [CS_NUM-1:0] ctrl_cs_n,
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input ctrl_rden,
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input ctrl_ref_flag,
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input [(2*DQ_WIDTH)-1:0] wdf_data,
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input [(2*DQ_WIDTH/8)-1:0] wdf_mask_data,
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output wdf_rden,
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output phy_init_done,
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output [DQS_WIDTH-1:0] phy_calib_rden,
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output [DQS_WIDTH-1:0] phy_calib_rden_sel,
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output [DQ_WIDTH-1:0] rd_data_rise,
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output [DQ_WIDTH-1:0] rd_data_fall,
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output [CLK_WIDTH-1:0] ddr_ck,
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output [CLK_WIDTH-1:0] ddr_ck_n,
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output [ROW_WIDTH-1:0] ddr_addr,
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output [BANK_WIDTH-1:0] ddr_ba,
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output ddr_ras_n,
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output ddr_cas_n,
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output ddr_we_n,
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output [CS_WIDTH-1:0] ddr_cs_n,
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output [CKE_WIDTH-1:0] ddr_cke,
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output [ODT_WIDTH-1:0] ddr_odt,
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output [DM_WIDTH-1:0] ddr_dm,
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inout [DQS_WIDTH-1:0] ddr_dqs,
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inout [DQS_WIDTH-1:0] ddr_dqs_n,
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inout [DQ_WIDTH-1:0] ddr_dq,
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// Debug signals (optional use)
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input dbg_idel_up_all,
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input dbg_idel_down_all,
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input dbg_idel_up_dq,
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input dbg_idel_down_dq,
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input dbg_idel_up_dqs,
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input dbg_idel_down_dqs,
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input dbg_idel_up_gate,
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input dbg_idel_down_gate,
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input [DQ_BITS-1:0] dbg_sel_idel_dq,
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input dbg_sel_all_idel_dq,
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input [DQS_BITS:0] dbg_sel_idel_dqs,
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input dbg_sel_all_idel_dqs,
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input [DQS_BITS:0] dbg_sel_idel_gate,
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input dbg_sel_all_idel_gate,
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output [3:0] dbg_calib_done,
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output [3:0] dbg_calib_err,
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output [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt,
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output [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt,
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output [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt,
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output [DQS_WIDTH-1:0] dbg_calib_rd_data_sel,
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output [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly,
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output [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly
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);
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wire [3:0] calib_done;
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wire calib_ref_done;
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wire calib_ref_req;
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wire [3:0] calib_start;
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wire dm_ce;
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wire [1:0] dq_oe_n;
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wire dqs_oe_n;
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wire dqs_rst_n;
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wire [(DQ_WIDTH/8)-1:0] mask_data_fall;
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wire [(DQ_WIDTH/8)-1:0] mask_data_rise;
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wire [CS_NUM-1:0] odt;
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wire [ROW_WIDTH-1:0] phy_init_addr;
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wire [BANK_WIDTH-1:0] phy_init_ba;
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wire phy_init_cas_n;
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wire [CKE_WIDTH-1:0] phy_init_cke;
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wire [CS_NUM-1:0] phy_init_cs_n;
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wire phy_init_data_sel;
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wire phy_init_ras_n;
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wire phy_init_rden;
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wire phy_init_we_n;
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wire phy_init_wren;
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wire [DQ_WIDTH-1:0] wr_data_fall;
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wire [DQ_WIDTH-1:0] wr_data_rise;
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//***************************************************************************
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ddr2_phy_write #
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(
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.DQ_WIDTH (DQ_WIDTH),
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.CS_NUM (CS_NUM),
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.ADDITIVE_LAT (ADDITIVE_LAT),
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.CAS_LAT (CAS_LAT),
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.ECC_ENABLE (ECC_ENABLE),
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.ODT_TYPE (ODT_TYPE),
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.REG_ENABLE (REG_ENABLE),
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.DDR_TYPE (DDR_TYPE)
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)
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u_phy_write
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(
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.clk0 (clk0),
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.clk90 (clk90),
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.rst90 (rst90),
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.wdf_data (wdf_data),
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.wdf_mask_data (wdf_mask_data),
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.ctrl_wren (ctrl_wren),
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.phy_init_wren (phy_init_wren),
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.phy_init_data_sel (phy_init_data_sel),
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.dm_ce (dm_ce),
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.dq_oe_n (dq_oe_n),
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.dqs_oe_n (dqs_oe_n),
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.dqs_rst_n (dqs_rst_n),
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.wdf_rden (wdf_rden),
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.odt (odt),
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.wr_data_rise (wr_data_rise),
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.wr_data_fall (wr_data_fall),
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.mask_data_rise (mask_data_rise),
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.mask_data_fall (mask_data_fall)
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);
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ddr2_phy_io #
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(
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.CLK_WIDTH (CLK_WIDTH),
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.USE_DM_PORT (USE_DM_PORT),
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.DM_WIDTH (DM_WIDTH),
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.DQ_WIDTH (DQ_WIDTH),
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.DQ_BITS (DQ_BITS),
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.DQ_PER_DQS (DQ_PER_DQS),
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.DQS_BITS (DQS_BITS),
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.DQS_WIDTH (DQS_WIDTH),
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.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
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.IODELAY_GRP (IODELAY_GRP),
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.ODT_WIDTH (ODT_WIDTH),
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.ADDITIVE_LAT (ADDITIVE_LAT),
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.CAS_LAT (CAS_LAT),
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.REG_ENABLE (REG_ENABLE),
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.CLK_PERIOD (CLK_PERIOD),
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.DDR_TYPE (DDR_TYPE),
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.SIM_ONLY (SIM_ONLY),
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| 246 |
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.DEBUG_EN (DEBUG_EN),
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.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE)
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)
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u_phy_io
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(
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| 251 |
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.clk0 (clk0),
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| 252 |
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.clk90 (clk90),
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| 253 |
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.clkdiv0 (clkdiv0),
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| 254 |
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.rst0 (rst0),
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| 255 |
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.rst90 (rst90),
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| 256 |
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.rstdiv0 (rstdiv0),
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| 257 |
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.dm_ce (dm_ce),
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| 258 |
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.dq_oe_n (dq_oe_n),
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| 259 |
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.dqs_oe_n (dqs_oe_n),
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| 260 |
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.dqs_rst_n (dqs_rst_n),
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| 261 |
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.calib_start (calib_start),
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| 262 |
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.ctrl_rden (ctrl_rden),
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| 263 |
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.phy_init_rden (phy_init_rden),
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| 264 |
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.calib_ref_done (calib_ref_done),
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| 265 |
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.calib_done (calib_done),
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| 266 |
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.calib_ref_req (calib_ref_req),
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| 267 |
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.calib_rden (phy_calib_rden),
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| 268 |
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.calib_rden_sel (phy_calib_rden_sel),
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| 269 |
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.wr_data_rise (wr_data_rise),
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| 270 |
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.wr_data_fall (wr_data_fall),
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| 271 |
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.mask_data_rise (mask_data_rise),
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| 272 |
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.mask_data_fall (mask_data_fall),
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| 273 |
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.rd_data_rise (rd_data_rise),
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| 274 |
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.rd_data_fall (rd_data_fall),
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| 275 |
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.ddr_ck (ddr_ck),
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| 276 |
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.ddr_ck_n (ddr_ck_n),
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| 277 |
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.ddr_dm (ddr_dm),
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| 278 |
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.ddr_dqs (ddr_dqs),
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| 279 |
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.ddr_dqs_n (ddr_dqs_n),
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| 280 |
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.ddr_dq (ddr_dq),
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| 281 |
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.dbg_idel_up_all (dbg_idel_up_all),
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| 282 |
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.dbg_idel_down_all (dbg_idel_down_all),
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| 283 |
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.dbg_idel_up_dq (dbg_idel_up_dq),
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| 284 |
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.dbg_idel_down_dq (dbg_idel_down_dq),
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| 285 |
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.dbg_idel_up_dqs (dbg_idel_up_dqs),
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| 286 |
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.dbg_idel_down_dqs (dbg_idel_down_dqs),
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| 287 |
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.dbg_idel_up_gate (dbg_idel_up_gate),
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| 288 |
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.dbg_idel_down_gate (dbg_idel_down_gate),
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| 289 |
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.dbg_sel_idel_dq (dbg_sel_idel_dq),
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| 290 |
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.dbg_sel_all_idel_dq (dbg_sel_all_idel_dq),
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| 291 |
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.dbg_sel_idel_dqs (dbg_sel_idel_dqs),
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| 292 |
|
|
.dbg_sel_all_idel_dqs (dbg_sel_all_idel_dqs),
|
| 293 |
|
|
.dbg_sel_idel_gate (dbg_sel_idel_gate),
|
| 294 |
|
|
.dbg_sel_all_idel_gate (dbg_sel_all_idel_gate),
|
| 295 |
|
|
.dbg_calib_done (dbg_calib_done),
|
| 296 |
|
|
.dbg_calib_err (dbg_calib_err),
|
| 297 |
|
|
.dbg_calib_dq_tap_cnt (dbg_calib_dq_tap_cnt),
|
| 298 |
|
|
.dbg_calib_dqs_tap_cnt (dbg_calib_dqs_tap_cnt),
|
| 299 |
|
|
.dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
|
| 300 |
|
|
.dbg_calib_rd_data_sel (dbg_calib_rd_data_sel),
|
| 301 |
|
|
.dbg_calib_rden_dly (dbg_calib_rden_dly),
|
| 302 |
|
|
.dbg_calib_gate_dly (dbg_calib_gate_dly)
|
| 303 |
|
|
);
|
| 304 |
|
|
|
| 305 |
|
|
ddr2_phy_ctl_io #
|
| 306 |
|
|
(
|
| 307 |
|
|
.BANK_WIDTH (BANK_WIDTH),
|
| 308 |
|
|
.CKE_WIDTH (CKE_WIDTH),
|
| 309 |
|
|
.COL_WIDTH (COL_WIDTH),
|
| 310 |
|
|
.CS_NUM (CS_NUM),
|
| 311 |
|
|
.CS_WIDTH (CS_WIDTH),
|
| 312 |
|
|
.TWO_T_TIME_EN (TWO_T_TIME_EN),
|
| 313 |
|
|
.ODT_WIDTH (ODT_WIDTH),
|
| 314 |
|
|
.ROW_WIDTH (ROW_WIDTH),
|
| 315 |
|
|
.DDR_TYPE (DDR_TYPE)
|
| 316 |
|
|
)
|
| 317 |
|
|
u_phy_ctl_io
|
| 318 |
|
|
(
|
| 319 |
|
|
.clk0 (clk0),
|
| 320 |
|
|
.clk90 (clk90),
|
| 321 |
|
|
.rst0 (rst0),
|
| 322 |
|
|
.rst90 (rst90),
|
| 323 |
|
|
.ctrl_addr (ctrl_addr),
|
| 324 |
|
|
.ctrl_ba (ctrl_ba),
|
| 325 |
|
|
.ctrl_ras_n (ctrl_ras_n),
|
| 326 |
|
|
.ctrl_cas_n (ctrl_cas_n),
|
| 327 |
|
|
.ctrl_we_n (ctrl_we_n),
|
| 328 |
|
|
.ctrl_cs_n (ctrl_cs_n),
|
| 329 |
|
|
.phy_init_addr (phy_init_addr),
|
| 330 |
|
|
.phy_init_ba (phy_init_ba),
|
| 331 |
|
|
.phy_init_ras_n (phy_init_ras_n),
|
| 332 |
|
|
.phy_init_cas_n (phy_init_cas_n),
|
| 333 |
|
|
.phy_init_we_n (phy_init_we_n),
|
| 334 |
|
|
.phy_init_cs_n (phy_init_cs_n),
|
| 335 |
|
|
.phy_init_cke (phy_init_cke),
|
| 336 |
|
|
.phy_init_data_sel (phy_init_data_sel),
|
| 337 |
|
|
.odt (odt),
|
| 338 |
|
|
.ddr_addr (ddr_addr),
|
| 339 |
|
|
.ddr_ba (ddr_ba),
|
| 340 |
|
|
.ddr_ras_n (ddr_ras_n),
|
| 341 |
|
|
.ddr_cas_n (ddr_cas_n),
|
| 342 |
|
|
.ddr_we_n (ddr_we_n),
|
| 343 |
|
|
.ddr_cke (ddr_cke),
|
| 344 |
|
|
.ddr_cs_n (ddr_cs_n),
|
| 345 |
|
|
.ddr_odt (ddr_odt)
|
| 346 |
|
|
);
|
| 347 |
|
|
|
| 348 |
|
|
ddr2_phy_init #
|
| 349 |
|
|
(
|
| 350 |
|
|
.BANK_WIDTH (BANK_WIDTH),
|
| 351 |
|
|
.CKE_WIDTH (CKE_WIDTH),
|
| 352 |
|
|
.COL_WIDTH (COL_WIDTH),
|
| 353 |
|
|
.CS_BITS (CS_BITS),
|
| 354 |
|
|
.CS_NUM (CS_NUM),
|
| 355 |
|
|
.DQ_WIDTH (DQ_WIDTH),
|
| 356 |
|
|
.ODT_WIDTH (ODT_WIDTH),
|
| 357 |
|
|
.ROW_WIDTH (ROW_WIDTH),
|
| 358 |
|
|
.ADDITIVE_LAT (ADDITIVE_LAT),
|
| 359 |
|
|
.BURST_LEN (BURST_LEN),
|
| 360 |
|
|
.BURST_TYPE (BURST_TYPE),
|
| 361 |
|
|
.TWO_T_TIME_EN(TWO_T_TIME_EN),
|
| 362 |
|
|
.CAS_LAT (CAS_LAT),
|
| 363 |
|
|
.ODT_TYPE (ODT_TYPE),
|
| 364 |
|
|
.REDUCE_DRV (REDUCE_DRV),
|
| 365 |
|
|
.REG_ENABLE (REG_ENABLE),
|
| 366 |
|
|
.TWR (TWR),
|
| 367 |
|
|
.CLK_PERIOD (CLK_PERIOD),
|
| 368 |
|
|
.DDR_TYPE (DDR_TYPE),
|
| 369 |
|
|
.SIM_ONLY (SIM_ONLY)
|
| 370 |
|
|
)
|
| 371 |
|
|
u_phy_init
|
| 372 |
|
|
(
|
| 373 |
|
|
.clk0 (clk0),
|
| 374 |
|
|
.clkdiv0 (clkdiv0),
|
| 375 |
|
|
.rst0 (rst0),
|
| 376 |
|
|
.rstdiv0 (rstdiv0),
|
| 377 |
|
|
.calib_done (calib_done),
|
| 378 |
|
|
.ctrl_ref_flag (ctrl_ref_flag),
|
| 379 |
|
|
.calib_ref_req (calib_ref_req),
|
| 380 |
|
|
.calib_start (calib_start),
|
| 381 |
|
|
.calib_ref_done (calib_ref_done),
|
| 382 |
|
|
.phy_init_wren (phy_init_wren),
|
| 383 |
|
|
.phy_init_rden (phy_init_rden),
|
| 384 |
|
|
.phy_init_addr (phy_init_addr),
|
| 385 |
|
|
.phy_init_ba (phy_init_ba),
|
| 386 |
|
|
.phy_init_ras_n (phy_init_ras_n),
|
| 387 |
|
|
.phy_init_cas_n (phy_init_cas_n),
|
| 388 |
|
|
.phy_init_we_n (phy_init_we_n),
|
| 389 |
|
|
.phy_init_cs_n (phy_init_cs_n),
|
| 390 |
|
|
.phy_init_cke (phy_init_cke),
|
| 391 |
|
|
.phy_init_done (phy_init_done),
|
| 392 |
|
|
.phy_init_data_sel (phy_init_data_sel)
|
| 393 |
|
|
);
|
| 394 |
|
|
|
| 395 |
|
|
endmodule
|
