1 |
3 |
oana.bonca |
//*****************************************************************************
|
2 |
|
|
// DISCLAIMER OF LIABILITY
|
3 |
|
|
//
|
4 |
|
|
// This file contains proprietary and confidential information of
|
5 |
|
|
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
|
6 |
|
|
// from Xilinx, and may be used, copied and/or disclosed only
|
7 |
|
|
// pursuant to the terms of a valid license agreement with Xilinx.
|
8 |
|
|
//
|
9 |
|
|
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
10 |
|
|
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
|
11 |
|
|
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
|
12 |
|
|
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
|
13 |
|
|
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
|
14 |
|
|
// does not warrant that functions included in the Materials will
|
15 |
|
|
// meet the requirements of Licensee, or that the operation of the
|
16 |
|
|
// Materials will be uninterrupted or error-free, or that defects
|
17 |
|
|
// in the Materials will be corrected. Furthermore, Xilinx does
|
18 |
|
|
// not warrant or make any representations regarding use, or the
|
19 |
|
|
// results of the use, of the Materials in terms of correctness,
|
20 |
|
|
// accuracy, reliability or otherwise.
|
21 |
|
|
//
|
22 |
|
|
// Xilinx products are not designed or intended to be fail-safe,
|
23 |
|
|
// or for use in any application requiring fail-safe performance,
|
24 |
|
|
// such as life-support or safety devices or systems, Class III
|
25 |
|
|
// medical devices, nuclear facilities, applications related to
|
26 |
|
|
// the deployment of airbags, or any other applications that could
|
27 |
|
|
// lead to death, personal injury or severe property or
|
28 |
|
|
// environmental damage (individually and collectively, "critical
|
29 |
|
|
// applications"). Customer assumes the sole risk and liability
|
30 |
|
|
// of any use of Xilinx products in critical applications,
|
31 |
|
|
// subject only to applicable laws and regulations governing
|
32 |
|
|
// limitations on product liability.
|
33 |
|
|
//
|
34 |
|
|
// Copyright 2006, 2007, 2008 Xilinx, Inc.
|
35 |
|
|
// All rights reserved.
|
36 |
|
|
//
|
37 |
|
|
// This disclaimer and copyright notice must be retained as part
|
38 |
|
|
// of this file at all times.
|
39 |
|
|
//*****************************************************************************
|
40 |
|
|
// ____ ____
|
41 |
|
|
// / /\/ /
|
42 |
|
|
// /___/ \ / Vendor: Xilinx
|
43 |
|
|
// \ \ \/ Version: 3.6.1
|
44 |
|
|
// \ \ Application: MIG
|
45 |
|
|
// / / Filename: ddr2_tb_test_addr_gen.v
|
46 |
|
|
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
|
47 |
|
|
// \ \ / \ Date Created: Fri Sep 01 2006
|
48 |
|
|
// \___\/\___\
|
49 |
|
|
//
|
50 |
|
|
//Device: Virtex-5
|
51 |
|
|
//Design Name: DDR2
|
52 |
|
|
//Purpose:
|
53 |
|
|
// The address for the memory and the various user commands can be given
|
54 |
|
|
// through this module. It instantiates the block RAM which stores all the
|
55 |
|
|
// information in particular sequence. The data stored should be in a
|
56 |
|
|
// sequence starting from LSB:
|
57 |
|
|
// column address, row address, bank address, commands.
|
58 |
|
|
//Reference:
|
59 |
|
|
//Revision History:
|
60 |
|
|
//*****************************************************************************
|
61 |
|
|
|
62 |
|
|
`timescale 1ns/1ps
|
63 |
|
|
|
64 |
|
|
module ddr2_tb_test_addr_gen #
|
65 |
|
|
(
|
66 |
|
|
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
|
67 |
|
|
// board design). Actual values may be different. Actual parameters values
|
68 |
|
|
// are passed from design top module MEMCtrl module. Please refer to
|
69 |
|
|
// the MEMCtrl module for actual values.
|
70 |
|
|
parameter BANK_WIDTH = 2,
|
71 |
|
|
parameter COL_WIDTH = 10,
|
72 |
|
|
parameter ROW_WIDTH = 14
|
73 |
|
|
)
|
74 |
|
|
(
|
75 |
|
|
input clk,
|
76 |
|
|
input rst,
|
77 |
|
|
input wr_addr_en,
|
78 |
|
|
output reg [2:0] app_af_cmd,
|
79 |
|
|
output reg [30:0] app_af_addr,
|
80 |
|
|
output reg app_af_wren
|
81 |
|
|
);
|
82 |
|
|
|
83 |
|
|
// RAM initialization patterns
|
84 |
|
|
// NOTE: Not all bits in each range may be used (e.g. in an application
|
85 |
|
|
// using only 10 column bits, bits[11:10] of ROM output will be unused
|
86 |
|
|
// COLUMN = [11:0]
|
87 |
|
|
// ROW = [27:12]
|
88 |
|
|
// BANK = [30:28]
|
89 |
|
|
// CHIP = [31]
|
90 |
|
|
// COMMAND = [35:32]
|
91 |
|
|
|
92 |
|
|
localparam RAM_INIT_00 = {128'h800020C0_800020C8_000020D0_000020D8,
|
93 |
|
|
128'h000010E0_000010E8_800010F0_800010F8};
|
94 |
|
|
localparam RAM_INIT_01 = {128'h800020C0_800020C8_000020D0_000020D8,
|
95 |
|
|
128'h000010E0_000010E8_800010F0_800010F8};
|
96 |
|
|
localparam RAM_INIT_02 = {128'h100040C0_100040C8_900040D0_900040D8,
|
97 |
|
|
128'h900030E0_900030E8_100030F0_100030F8};
|
98 |
|
|
localparam RAM_INIT_03 = {128'h100040C0_100040C8_900040D0_900040D8,
|
99 |
|
|
128'h900030E0_900030E8_100030F0_100030F8};
|
100 |
|
|
localparam RAM_INIT_04 = {128'hA00060C0_200060C8_200060D0_A00060D8,
|
101 |
|
|
128'h200050E0_A00050E8_A00050F0_200050F8};
|
102 |
|
|
localparam RAM_INIT_05 = {128'hA00060C0_200060C8_200060D0_A00060D8,
|
103 |
|
|
128'h200050E0_A00050E8_A00050F0_200050F8};
|
104 |
|
|
localparam RAM_INIT_06 = {128'h300080C0_B00080C8_B00080D0_300080D8,
|
105 |
|
|
128'hB00070E0_300070E8_300070F0_B00070F8};
|
106 |
|
|
localparam RAM_INIT_07 = {128'h300080C0_B00080C8_B00080D0_300080D8,
|
107 |
|
|
128'hB00070E0_300070E8_300070F0_B00070F8};
|
108 |
|
|
localparam RAM_INITP_00 = {128'h11111111_00000000_11111111_00000000,
|
109 |
|
|
128'h11111111_00000000_11111111_00000000};
|
110 |
|
|
|
111 |
|
|
reg wr_addr_en_r1;
|
112 |
|
|
reg [2:0] af_cmd_r;
|
113 |
|
|
reg [30:0] af_addr_r;
|
114 |
|
|
reg af_wren_r;
|
115 |
|
|
wire [15:0] ramb_addr;
|
116 |
|
|
wire [35:0] ramb_dout;
|
117 |
|
|
reg rst_r
|
118 |
|
|
/* synthesis syn_preserve = 1 */;
|
119 |
|
|
reg rst_r1
|
120 |
|
|
/* synthesis syn_maxfan = 10 */;
|
121 |
|
|
reg [5:0] wr_addr_cnt;
|
122 |
|
|
reg wr_addr_en_r0;
|
123 |
|
|
|
124 |
|
|
// XST attributes for local reset "tree"
|
125 |
|
|
// synthesis attribute shreg_extract of rst_r is "no";
|
126 |
|
|
// synthesis attribute shreg_extract of rst_r1 is "no";
|
127 |
|
|
// synthesis attribute equivalent_register_removal of rst_r is "no"
|
128 |
|
|
|
129 |
|
|
//*****************************************************************
|
130 |
|
|
|
131 |
|
|
// local reset "tree" for controller logic only. Create this to ease timing
|
132 |
|
|
// on reset path. Prohibit equivalent register removal on RST_R to prevent
|
133 |
|
|
// "sharing" with other local reset trees (caution: make sure global fanout
|
134 |
|
|
// limit is set to larger than fanout on RST_R, otherwise SLICES will be
|
135 |
|
|
// used for fanout control on RST_R.
|
136 |
|
|
always @(posedge clk) begin
|
137 |
|
|
rst_r <= rst;
|
138 |
|
|
rst_r1 <= rst_r;
|
139 |
|
|
end
|
140 |
|
|
|
141 |
|
|
//***************************************************************************
|
142 |
|
|
// ADDRESS generation for Write and Read Address FIFOs:
|
143 |
|
|
// ROM with address patterns
|
144 |
|
|
// 512x36 mode is used with addresses 0-127 for storing write addresses and
|
145 |
|
|
// addresses (128-511) for storing read addresses
|
146 |
|
|
// INIP_OO: read 1
|
147 |
|
|
// INIP_OO: write 0
|
148 |
|
|
//***************************************************************************
|
149 |
|
|
|
150 |
|
|
assign ramb_addr = {5'b00000, wr_addr_cnt, 5'b00000};
|
151 |
|
|
|
152 |
|
|
RAMB36 #
|
153 |
|
|
(
|
154 |
|
|
.READ_WIDTH_A (36),
|
155 |
|
|
.READ_WIDTH_B (36),
|
156 |
|
|
.DOA_REG (1), // register to help timing
|
157 |
|
|
.INIT_00 (RAM_INIT_00),
|
158 |
|
|
.INIT_01 (RAM_INIT_01),
|
159 |
|
|
.INIT_02 (RAM_INIT_02),
|
160 |
|
|
.INIT_03 (RAM_INIT_03),
|
161 |
|
|
.INIT_04 (RAM_INIT_04),
|
162 |
|
|
.INIT_05 (RAM_INIT_05),
|
163 |
|
|
.INIT_06 (RAM_INIT_06),
|
164 |
|
|
.INIT_07 (RAM_INIT_07),
|
165 |
|
|
.INITP_00 (RAM_INITP_00)
|
166 |
|
|
)
|
167 |
|
|
u_wr_rd_addr_lookup
|
168 |
|
|
(
|
169 |
|
|
.CASCADEOUTLATA (),
|
170 |
|
|
.CASCADEOUTLATB (),
|
171 |
|
|
.CASCADEOUTREGA (),
|
172 |
|
|
.CASCADEOUTREGB (),
|
173 |
|
|
.DOA (ramb_dout[31:0]),
|
174 |
|
|
.DOB (),
|
175 |
|
|
.DOPA (ramb_dout[35:32]),
|
176 |
|
|
.DOPB (),
|
177 |
|
|
.ADDRA (ramb_addr),
|
178 |
|
|
.ADDRB (16'h0000),
|
179 |
|
|
.CASCADEINLATA (),
|
180 |
|
|
.CASCADEINLATB (),
|
181 |
|
|
.CASCADEINREGA (),
|
182 |
|
|
.CASCADEINREGB (),
|
183 |
|
|
.CLKA (clk),
|
184 |
|
|
.CLKB (clk),
|
185 |
|
|
.DIA (32'b0),
|
186 |
|
|
.DIB (32'b0),
|
187 |
|
|
.DIPA (4'b0),
|
188 |
|
|
.DIPB (4'b0),
|
189 |
|
|
.ENA (1'b1),
|
190 |
|
|
.ENB (1'b1),
|
191 |
|
|
.REGCEA (1'b1),
|
192 |
|
|
.REGCEB (1'b1),
|
193 |
|
|
.SSRA (1'b0),
|
194 |
|
|
.SSRB (1'b0),
|
195 |
|
|
.WEA (4'b0000),
|
196 |
|
|
.WEB (4'b0000)
|
197 |
|
|
);
|
198 |
|
|
|
199 |
|
|
// register backend enables / FIFO enables
|
200 |
|
|
// write enable for Command/Address FIFO is generated 2 CC after WR_ADDR_EN
|
201 |
|
|
// (takes 2 CC to come out of test RAM)
|
202 |
|
|
always @(posedge clk)
|
203 |
|
|
if (rst_r1) begin
|
204 |
|
|
app_af_wren <= 1'b0;
|
205 |
|
|
wr_addr_en_r0 <= 1'b0;
|
206 |
|
|
wr_addr_en_r1 <= 1'b0;
|
207 |
|
|
af_wren_r <= 1'b0;
|
208 |
|
|
end else begin
|
209 |
|
|
wr_addr_en_r0 <= wr_addr_en;
|
210 |
|
|
wr_addr_en_r1 <= wr_addr_en_r0;
|
211 |
|
|
af_wren_r <= wr_addr_en_r1;
|
212 |
|
|
app_af_wren <= af_wren_r;
|
213 |
|
|
end
|
214 |
|
|
|
215 |
|
|
// FIFO addresses
|
216 |
|
|
always @(posedge clk) begin
|
217 |
|
|
af_addr_r <= {30{1'b0}};
|
218 |
|
|
af_addr_r[COL_WIDTH-1:0] <= ramb_dout[COL_WIDTH-1:0];
|
219 |
|
|
af_addr_r[ROW_WIDTH+COL_WIDTH-1:COL_WIDTH]
|
220 |
|
|
<= ramb_dout[ROW_WIDTH+11:12];
|
221 |
|
|
af_addr_r[BANK_WIDTH+ROW_WIDTH+COL_WIDTH-1:ROW_WIDTH+COL_WIDTH]
|
222 |
|
|
<= ramb_dout[BANK_WIDTH+27:28];
|
223 |
|
|
af_addr_r[BANK_WIDTH+ROW_WIDTH+COL_WIDTH]
|
224 |
|
|
<= ramb_dout[31];
|
225 |
|
|
// only reads and writes are supported for now
|
226 |
|
|
af_cmd_r <= {1'b0, ramb_dout[33:32]};
|
227 |
|
|
app_af_cmd <= af_cmd_r;
|
228 |
|
|
app_af_addr <= af_addr_r;
|
229 |
|
|
end
|
230 |
|
|
|
231 |
|
|
// address input for RAM
|
232 |
|
|
always @ (posedge clk)
|
233 |
|
|
if (rst_r1)
|
234 |
|
|
wr_addr_cnt <= 6'b000000;
|
235 |
|
|
else if (wr_addr_en)
|
236 |
|
|
wr_addr_cnt <= wr_addr_cnt + 1;
|
237 |
|
|
|
238 |
|
|
|
239 |
|
|
endmodule
|