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[/] [gpib_controller/] [trunk/] [vhdl/] [test/] [gpib_RL_Test.vhd] - Blame information for rev 13

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Line No. Rev Author Line
1 3 Andrewski
--------------------------------------------------------------------------------
2 13 Andrewski
--This file is part of fpga_gpib_controller.
3 3 Andrewski
--
4 13 Andrewski
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
5
-- it under the terms of the GNU General Public License as published by
6
-- the Free Software Foundation, either version 3 of the License, or
7
-- (at your option) any later version.
8
--
9
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
10
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
-- GNU General Public License for more details.
13
 
14
-- You should have received a copy of the GNU General Public License
15
-- along with Fpga_gpib_controller.  If not, see <http://www.gnu.org/licenses/>.
16
--------------------------------------------------------------------------------
17
-- Author: Andrzej Paluch
18
--
19 3 Andrewski
-- Create Date:   23:21:05 10/21/2011
20
-- Design Name:   
21
-- Module Name:   /windows/h/projekty/elektronika/USB_to_HPIB/usbToHpib/test_scr//gpibInterfaceTest.vhd
22
-- Project Name:  usbToHpib
23
-- Target Device:  
24
-- Tool versions:  
25
-- Description:   
26
-- 
27
-- VHDL Test Bench Created by ISE for module: gpibInterface
28
-- 
29
-- Dependencies:
30
-- 
31
-- Revision:
32
-- Revision 0.01 - File Created
33
-- Additional Comments:
34
--
35
-- Notes: 
36
-- This testbench has been automatically generated using types std_logic and
37
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
38
-- that these types always be used for the top-level I/O of a design in order
39
-- to guarantee that the testbench will bind correctly to the post-implementation 
40
-- simulation model.
41
--------------------------------------------------------------------------------
42
LIBRARY ieee;
43
USE ieee.std_logic_1164.ALL;
44
USE ieee.std_logic_unsigned.all;
45
USE ieee.numeric_std.ALL;
46
 
47
use work.gpibComponents.all;
48
use work.helperComponents.all;
49
 
50
 
51
ENTITY gpib_RL_Test IS
52
END gpib_RL_Test;
53
 
54
ARCHITECTURE behavior OF gpib_RL_Test IS
55
 
56
        -- Component Declaration for the Unit Under Test (UUT)
57
 
58
        component gpibCableEmulator is port (
59
                -- interface signals
60
                DIO_1 : in std_logic_vector (7 downto 0);
61
                output_valid_1 : in std_logic;
62
                DIO_2 : in std_logic_vector (7 downto 0);
63
                output_valid_2 : in std_logic;
64
                DIO : out std_logic_vector (7 downto 0);
65
                -- attention
66
                ATN_1 : in std_logic;
67
                ATN_2 : in std_logic;
68
                ATN : out std_logic;
69
                -- data valid
70
                DAV_1 : in std_logic;
71
                DAV_2 : in std_logic;
72
                DAV : out std_logic;
73
                -- not ready for data
74
                NRFD_1 : in std_logic;
75
                NRFD_2 : in std_logic;
76
                NRFD : out std_logic;
77
                -- no data accepted
78
                NDAC_1 : in std_logic;
79
                NDAC_2 : in std_logic;
80
                NDAC : out std_logic;
81
                -- end or identify
82
                EOI_1 : in std_logic;
83
                EOI_2 : in std_logic;
84
                EOI : out std_logic;
85
                -- service request
86
                SRQ_1 : in std_logic;
87
                SRQ_2 : in std_logic;
88
                SRQ : out std_logic;
89
                -- interface clear
90
                IFC_1 : in std_logic;
91
                IFC_2 : in std_logic;
92
                IFC : out std_logic;
93
                -- remote enable
94
                REN_1 : in std_logic;
95
                REN_2 : in std_logic;
96
                REN : out std_logic
97
        );
98
        end component;
99
 
100
        -- inputs common
101
        signal clk : std_logic := '0';
102
        signal reset : std_logic := '0';
103
        signal T1 : std_logic_vector(7 downto 0) := "00000100";
104
 
105
        -- inputs 1
106
        signal data_1 : std_logic_vector(7 downto 0) := (others => '0');
107
        signal status_byte_1 : std_logic_vector(7 downto 0) := (others => '0');
108
        signal rdy_1 : std_logic := '0';
109
        signal nba_1 : std_logic := '0';
110
        signal ltn_1 : std_logic := '0';
111
        signal lun_1 : std_logic := '0';
112
        signal lon_1 : std_logic := '0';
113
        signal ton_1 : std_logic := '0';
114
        signal endOf_1 : std_logic := '0';
115
        signal gts_1 : std_logic := '0';
116
        signal rpp_1 : std_logic := '0';
117
        signal tcs_1 : std_logic := '0';
118
        signal tca_1 : std_logic := '0';
119
        signal sic_1 : std_logic := '0';
120
        signal rsc_1 : std_logic := '0';
121
        signal sre_1 : std_logic := '0';
122
        signal rtl_1 : std_logic := '0';
123
        signal rsv_1 : std_logic := '0';
124
        signal ist_1 : std_logic := '0';
125
        signal lpe_1 : std_logic := '0';
126
 
127
        -- inputs 2
128
        signal data_2 : std_logic_vector(7 downto 0) := (others => '0');
129
        signal status_byte_2 : std_logic_vector(7 downto 0) := (others => '0');
130
        signal rdy_2 : std_logic := '0';
131
        signal nba_2 : std_logic := '0';
132
        signal ltn_2 : std_logic := '0';
133
        signal lun_2 : std_logic := '0';
134
        signal lon_2 : std_logic := '0';
135
        signal ton_2 : std_logic := '0';
136
        signal endOf_2 : std_logic := '0';
137
        signal gts_2 : std_logic := '0';
138
        signal rpp_2 : std_logic := '0';
139
        signal tcs_2 : std_logic := '0';
140
        signal tca_2 : std_logic := '0';
141
        signal sic_2 : std_logic := '0';
142
        signal rsc_2 : std_logic := '0';
143
        signal sre_2 : std_logic := '0';
144
        signal rtl_2 : std_logic := '0';
145
        signal rsv_2 : std_logic := '0';
146
        signal ist_2 : std_logic := '0';
147
        signal lpe_2 : std_logic := '0';
148
 
149
        -- outputs 1
150
        signal dvd_1 : std_logic;
151
        signal wnc_1 : std_logic;
152
        signal tac_1 : std_logic;
153
        signal cwrc_1 : std_logic;
154
        signal cwrd_1 : std_logic;
155
        signal clr_1 : std_logic;
156
        signal trg_1 : std_logic;
157
        signal atl_1 : std_logic;
158
        signal att_1 : std_logic;
159
        signal mla_1 : std_logic;
160
        signal lsb_1 : std_logic;
161
        signal spa_1 : std_logic;
162
        signal ppr_1 : std_logic;
163
        signal sreq_1 : std_logic;
164
        signal isLocal_1 : std_logic;
165
        signal currentSecAddr_1 : std_logic_vector (4 downto 0);
166
 
167
        -- outputs 2
168
        signal dvd_2 : std_logic;
169
        signal wnc_2 : std_logic;
170
        signal tac_2 : std_logic;
171
        signal cwrc_2 : std_logic;
172
        signal cwrd_2 : std_logic;
173
        signal clr_2 : std_logic;
174
        signal trg_2 : std_logic;
175
        signal atl_2 : std_logic;
176
        signal att_2 : std_logic;
177
        signal mla_2 : std_logic;
178
        signal lsb_2 : std_logic;
179
        signal spa_2 : std_logic;
180
        signal ppr_2 : std_logic;
181
        signal sreq_2 : std_logic;
182
        signal isLocal_2 : std_logic;
183
        signal currentSecAddr_2 : std_logic_vector (4 downto 0);
184
 
185
        -- common
186
        signal DO : std_logic_vector (7 downto 0);
187
        signal DI_1 : std_logic_vector (7 downto 0);
188
        signal output_valid_1 : std_logic;
189
        signal DI_2 : std_logic_vector (7 downto 0);
190
        signal output_valid_2 : std_logic;
191
        signal ATN_1, ATN_2, ATN : std_logic;
192
        signal DAV_1, DAV_2, DAV : std_logic;
193
        signal NRFD_1, NRFD_2, NRFD : std_logic;
194
        signal NDAC_1, NDAC_2, NDAC : std_logic;
195
        signal EOI_1, EOI_2, EOI : std_logic;
196
        signal SRQ_1, SRQ_2, SRQ : std_logic;
197
        signal IFC_1, IFC_2, IFC : std_logic;
198
        signal REN_1, REN_2, REN : std_logic;
199
 
200
        -- gpib reader
201
        signal buf_interrupt : std_logic;
202
        signal data_available : std_logic;
203
        signal last_byte_addr : std_logic_vector (3 downto 0);
204
        signal end_of_stream : std_logic;
205
        signal byte_addr : std_logic_vector (3 downto 0);
206
        signal data_out : std_logic_vector (7 downto 0);
207
        signal reset_buffer : std_logic := '0';
208
        signal dataSecAddr : std_logic_vector (4 downto 0);
209
 
210
        -- gpib writer
211
        signal w_last_byte_addr : std_logic_vector (3 downto 0)
212
                := (others => '0');
213
        signal w_end_of_stream : std_logic := '0';
214
        signal w_data_available : std_logic := '0';
215
        signal w_buf_interrupt : std_logic;
216
        signal w_data_in : std_logic_vector (7 downto 0);
217
        signal w_byte_addr : std_logic_vector (3 downto 0);
218
        signal w_reset_buffer : std_logic := '0';
219
        type WR_BUF_TYPE is
220
                array (0 to 15) of std_logic_vector (7 downto 0);
221
        signal w_write_buffer : WR_BUF_TYPE;
222
 
223
        -- Clock period definitions
224
        constant clk_period : time := 2ps;
225
 
226
BEGIN
227
 
228
        -- Instantiate the Unit Under Test (UUT)
229
        gpib1: gpibInterface PORT MAP (
230
                clk => clk,
231
                reset => reset,
232
                isLE => '0',
233
                isTE => '0',
234
                lpeUsed => '0',
235
                fixedPpLine => "000",
236
                eosUsed => '0',
237
                eosMark => "00000000",
238
                myListAddr => "00001",
239
                myTalkAddr => "00001",
240
                secAddrMask => (others => '0'),
241
                data => data_1,
242
                status_byte => status_byte_1,
243
                T1 => T1,
244
                rdy => rdy_1,
245
                nba => nba_1,
246
                ltn => ltn_1,
247
                lun => lun_1,
248
                lon => lon_1,
249
                ton => ton_1,
250
                endOf => endOf_1,
251
                gts => gts_1,
252
                rpp => rpp_1,
253
                tcs => tcs_1,
254
                tca => tca_1,
255
                sic => sic_1,
256
                rsc => rsc_1,
257
                sre => sre_1,
258
                rtl => rtl_1,
259
                rsv => rsv_1,
260
                ist => ist_1,
261
                lpe => lpe_1,
262
                dvd => dvd_1,
263
                wnc => wnc_1,
264
                tac => tac_1,
265
                cwrc => cwrc_1,
266
                cwrd => cwrd_1,
267
                clr => clr_1,
268
                trg => trg_1,
269
                atl => atl_1,
270
                att => att_1,
271
                mla => mla_1,
272
                lsb => lsb_1,
273
                spa => spa_1,
274
                ppr => ppr_1,
275
                sreq => sreq_1,
276
                isLocal => isLocal_1,
277
                currentSecAddr => currentSecAddr_1,
278
                DI => DO,
279
                DO => DI_1,
280
                output_valid => output_valid_1,
281
                ATN_in => ATN,
282
                ATN_out => ATN_1,
283
                DAV_in => DAV,
284
                DAV_out => DAV_1,
285
                NRFD_in => NRFD,
286
                NRFD_out => NRFD_1,
287
                NDAC_in => NDAC,
288
                NDAC_out => NDAC_1,
289
                EOI_in => EOI,
290
                EOI_out => EOI_1,
291
                SRQ_in => SRQ,
292
                SRQ_out => SRQ_1,
293
                IFC_in => IFC,
294
                IFC_out => IFC_1,
295
                REN_in => REN,
296
                REN_out => REN_1
297
                );
298
 
299
        -- Instantiate the Unit Under Test (UUT)
300
        gpib2: gpibInterface PORT MAP (
301
                clk => clk,
302
                reset => reset,
303
                isLE => '0',
304
                isTE => '0',
305
                lpeUsed => '0',
306
                fixedPpLine => "000",
307
                eosUsed => '0',
308
                eosMark => "00000000",
309
                myListAddr => "00010",
310
                myTalkAddr => "00010",
311
                secAddrMask => (others => '0'),
312
                data => data_2,
313
                status_byte => status_byte_2,
314
                T1 => T1,
315
                rdy => rdy_2,
316
                nba => nba_2,
317
                ltn => ltn_2,
318
                lun => lun_2,
319
                lon => lon_2,
320
                ton => ton_2,
321
                endOf => endOf_2,
322
                gts => gts_2,
323
                rpp => rpp_2,
324
                tcs => tcs_2,
325
                tca => tca_2,
326
                sic => sic_2,
327
                rsc => rsc_2,
328
                sre => sre_2,
329
                rtl => rtl_2,
330
                rsv => rsv_2,
331
                ist => ist_2,
332
                lpe => lpe_2,
333
                dvd => dvd_2,
334
                wnc => wnc_2,
335
                tac => tac_2,
336
                cwrc => cwrc_2,
337
                cwrd => cwrd_2,
338
                clr => clr_2,
339
                trg => trg_2,
340
                atl => atl_2,
341
                att => att_2,
342
                mla => mla_2,
343
                lsb => lsb_2,
344
                spa => spa_2,
345
                ppr => ppr_2,
346
                sreq => sreq_2,
347
                isLocal => isLocal_2,
348
                currentSecAddr => currentSecAddr_2,
349
                DI => DO,
350
                DO => DI_2,
351
                output_valid => output_valid_2,
352
                ATN_in => ATN,
353
                ATN_out => ATN_2,
354
                DAV_in => DAV,
355
                DAV_out => DAV_2,
356
                NRFD_in => NRFD,
357
                NRFD_out => NRFD_2,
358
                NDAC_in => NDAC,
359
                NDAC_out => NDAC_2,
360
                EOI_in => EOI,
361
                EOI_out => EOI_2,
362
                SRQ_in => SRQ,
363
                SRQ_out => SRQ_2,
364
                IFC_in => IFC,
365
                IFC_out => IFC_2,
366
                REN_in => REN,
367
                REN_out => REN_2
368
                );
369
 
370
        ce: gpibCableEmulator port map (
371
                -- interface signals
372
                DIO_1 => DI_1,
373
                output_valid_1 => output_valid_1,
374
                DIO_2 => DI_2,
375
                output_valid_2 => output_valid_2,
376
                DIO => DO,
377
                -- attention
378
                ATN_1 => ATN_1, ATN_2 => ATN_2, ATN => ATN,
379
                DAV_1 => DAV_1, DAV_2 => DAV_2, DAV => DAV,
380
                NRFD_1 => NRFD_1, NRFD_2 => NRFD_2, NRFD => NRFD,
381
                NDAC_1 => NDAC_1, NDAC_2 => NDAC_2, NDAC => NDAC,
382
                EOI_1 => EOI_1, EOI_2 => EOI_2, EOI => EOI,
383
                SRQ_1 => SRQ_1, SRQ_2 => SRQ_2, SRQ => SRQ,
384
                IFC_1 => IFC_1, IFC_2 => IFC_2, IFC => IFC,
385
                REN_1 => REN_1, REN_2 => REN_2, REN => REN
386
        );
387
 
388
        gr: gpibReader generic map (ADDR_WIDTH => 4) port map (
389
                clk => clk, reset => reset,
390
                ------------------------------------------------------------------------
391
                ------ GPIB interface --------------------------------------------------
392
                ------------------------------------------------------------------------
393
                data_in => DO, dvd => dvd_2, atl => atl_2, lsb => lsb_2, rdy => rdy_2,
394
                ------------------------------------------------------------------------
395
                ------ external interface ----------------------------------------------
396
                ------------------------------------------------------------------------
397
                isLE => '0', secAddr => (others => '0'), dataSecAddr => dataSecAddr,
398
                buf_interrupt => buf_interrupt, data_available => data_available,
399
                last_byte_addr => last_byte_addr, end_of_stream => end_of_stream,
400
                byte_addr => byte_addr, data_out => data_out,
401
                reset_buffer => reset_buffer
402
        );
403
 
404
        w_data_in <= w_write_buffer(conv_integer(w_byte_addr));
405
 
406
        gw: gpibWriter generic map (ADDR_WIDTH => 4) port map (
407
                        clk => clk, reset => reset,
408
                        ------------------------------------------------------------------------
409
                        ------ GPIB interface --------------------------------------------------
410
                        ------------------------------------------------------------------------
411
                        data_out => data_1, wnc => wnc_1, spa => spa_1, nba => nba_1,
412
                        endOf => endOf_1, att => att_1, cwrc => cwrc_1,
413
                        ------------------------------------------------------------------------
414
                        ------ external interface ----------------------------------------------
415
                        ------------------------------------------------------------------------
416
                        isTE => '0', secAddr => (others => '0'), dataSecAddr => (others => '0'),
417
                        last_byte_addr => w_last_byte_addr, end_of_stream => w_end_of_stream,
418
                        data_available => w_data_available, buf_interrupt => w_buf_interrupt,
419
                        data_in => w_data_in, byte_addr => w_byte_addr,
420
                        reset_buffer => w_reset_buffer
421
                );
422
 
423
        -- Clock process definitions
424
        clk_process :process
425
        begin
426
                clk <= '0';
427
                wait for clk_period/2;
428
                clk <= '1';
429
                wait for clk_period/2;
430
        end process;
431
 
432
 
433
        -- Stimulus process
434
        stim_proc: process
435
        begin
436
                -- hold reset state for 10 clock periods.
437
                reset <= '1';
438
                wait for clk_period*10;
439
                reset <= '0';
440
                wait for clk_period*10;
441
 
442
                -- requests system control
443
                rsc_1 <= '1';
444
 
445
                -- interface clear
446
                sic_1 <= '1';
447
                wait until IFC_1 = '1';
448
                sic_1 <= '0';
449
                wait until IFC_1 = '0';
450
 
451
                assert isLocal_1 = '1';
452
                assert isLocal_2 = '1';
453
                assert REN = '0';
454
 
455
                sre_1 <= '1';
456
 
457
                wait until REN = '1';
458
 
459
                assert isLocal_1 = '1';
460
                assert isLocal_2 = '1';
461
                assert REN = '1';
462
 
463
                -- gpib2 to listen
464
                w_write_buffer(0) <= "00100010";
465
                w_last_byte_addr <= "0000";
466
                w_data_available <= '1';
467
 
468
                wait until w_buf_interrupt='1';
469
 
470
                assert isLocal_1 = '1';
471
                assert isLocal_2 = '0';
472
                assert REN = '1';
473
 
474
                rtl_2 <= '1';
475
 
476
                wait until isLocal_2 = '1';
477
 
478
                assert isLocal_2 = '1';
479
 
480
                w_reset_buffer <= '1';
481
                wait for clk_period*2;
482
                w_reset_buffer <= '0';
483
 
484
                -- send LLO (local lockout)
485
                w_write_buffer(0) <= "10010001";
486
                w_last_byte_addr <= "0000";
487
                w_data_available <= '1';
488
 
489
                wait until w_buf_interrupt='1';
490
 
491
                assert isLocal_2 = '1';
492
 
493
                w_reset_buffer <= '1';
494
                wait for clk_period*2;
495
                w_reset_buffer <= '0';
496
 
497
                -- gpib2 to listen
498
                w_write_buffer(0) <= "00100010";
499
                w_last_byte_addr <= "0000";
500
                w_data_available <= '1';
501
 
502
                wait until w_buf_interrupt='1';
503
 
504
                assert isLocal_2 = '0';
505
 
506
                w_reset_buffer <= '1';
507
                wait for clk_period*2;
508
                w_reset_buffer <= '0';
509
 
510
                -- send GTL (go to local)
511
                w_write_buffer(0) <= "00000001";
512
                w_last_byte_addr <= "0000";
513
                w_data_available <= '1';
514
 
515
                wait until w_buf_interrupt='1';
516
 
517
                assert isLocal_2 = '1';
518
 
519
                w_reset_buffer <= '1';
520
                wait for clk_period*2;
521
                w_reset_buffer <= '0';
522
 
523
                -- gpib2 to listen
524
                w_write_buffer(0) <= "00100010";
525
                w_last_byte_addr <= "0000";
526
                w_data_available <= '1';
527
 
528
                wait until w_buf_interrupt='1';
529
 
530
                assert isLocal_2 = '0';
531
 
532
                sre_1 <= '0';
533
 
534
                wait until REN = '0';
535
 
536
                wait for clk_period*5;
537
 
538
                assert isLocal_2 = '1';
539
 
540
                report "$$$ END OF TEST - remote / local $$$";
541
 
542
                wait;
543
        end process;
544
 
545
END;

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