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[/] [gpio/] [trunk/] [bench/] [verilog/] [wb_master.v] - Blame information for rev 66

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Line No. Rev Author Line
1 8 lampret 
`include "timescale.v"
2 37 gorand 
`include "gpio_defines.v"
3 8 lampret 
 
4 
//                              -*- Mode: Verilog -*-
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// Filename        : wb_master.v
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// Description     : Wishbone Master Behavorial
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// Author          : Winefred Washington
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// Created On      : Thu Jan 11 21:18:41 2001
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// Last Modified By: .
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// Last Modified On: .
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// Update Count    : 0
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// Status          : Unknown, Use with caution!
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//        Description                   Specification
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// General Description:            8, 16, 32-bit WISHBONE Master
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// Supported cycles:               MASTER, READ/WRITE
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//                                 MASTER, BLOCK READ/WRITE
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//                                 MASTER, RMW
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// Data port, size:                8, 16, 32-bit
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// Data port, granularity          8-bit
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// Data port, Max. operand size    32-bit
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// Data transfer ordering:         little endian
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// Data transfer sequencing:       undefined
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//
25 
 
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module wb_master(CLK_I, RST_I, TAG_I, TAG_O,
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                   ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O);
28 
 
29 37 gorand 
parameter aw = `GPIO_ADDRHH+1 ;
30 8 lampret 
   input                CLK_I;
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   input                RST_I;
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   input [3:0]           TAG_I;
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   output [3:0]  TAG_O;
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   input                ACK_I;
35 37 gorand 
   output [aw-1:0]       ADR_O;
36 8 lampret 
   output               CYC_O;
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   input [31:0]  DAT_I;
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   output [31:0]         DAT_O;
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   input                ERR_I;
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   input                RTY_I;
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   output [3:0]  SEL_O;
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   output               STB_O;
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   output               WE_O;
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45 37 gorand 
   reg [aw-1:0]          ADR_O;
46 8 lampret 
   reg [3:0]             SEL_O;
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   reg                  CYC_O;
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   reg                  STB_O;
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   reg                  WE_O;
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   reg [31:0]            DAT_O;
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   wire [15:0]           mem_sizes;      // determines the data width of an address range
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   reg [31:0]            write_burst_buffer[0:7];
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   reg [31:0]            read_burst_buffer[0:7];
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   reg                  GO;
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   integer              cycle_end;
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   integer              address;
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   integer              data;
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   integer              selects;
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   integer              write_flag;
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   //
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   // mem_sizes determines the data widths of memory space
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   // The memory space is divided into eight regions. Each
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   // region is controlled by a two bit field.
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   //
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   //    Bits
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   //    00 = 8 bit memory space
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   //    01 = 16 bit
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   //    10 = 32 bit
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   //    11 = 64 bit (not supported in this model
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   //
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   assign               mem_sizes = 16'b10_01_10_11_00_01_10_11;
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   function [1:0] data_width;
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      input [31:0] adr;
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      begin
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         casex (adr[31:29])
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           3'b000: data_width = mem_sizes[15:14];
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           3'b001: data_width = mem_sizes[13:12];
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           3'b010: data_width = mem_sizes[11:10];
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           3'b011: data_width = mem_sizes[9:8];
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           3'b100: data_width = mem_sizes[7:6];
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           3'b101: data_width = mem_sizes[5:4];
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           3'b110: data_width = mem_sizes[3:2];
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           3'b111: data_width = mem_sizes[1:0];
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           3'bxxx: data_width = 2'bxx;
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         endcase // casex (adr[31:29])
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      end
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   endfunction
93 
 
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   always @(posedge CLK_I or posedge RST_I)
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     begin
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        if (RST_I)
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          begin
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             GO = 1'b0;
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          end
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     end
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   // read single
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   task rd;
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      input [31:0] adr;
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      output [31:0] result;
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      begin
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         cycle_end = 1;
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         address = adr;
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         selects = 255;
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         write_flag = 0;
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         GO <= 1;
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         @(posedge CLK_I);
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//       GO <= 0;
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         // wait for cycle to start
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         while (~CYC_O)
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           @(posedge CLK_I);
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         // wait for cycle to end
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         while (CYC_O)
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           @(posedge CLK_I);
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         result = data;
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//      $display(" Reading %h from address %h", result, address);
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128 
      end
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   endtask // read
130 
 
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   task wr;
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      input [31:0] adr;
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      input [31:0] dat;
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      input [3:0] sel;
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      begin
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         cycle_end = 1;
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         address = adr;
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         selects = sel;
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         write_flag = 1;
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         data = dat;
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         GO <= 1;
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         @(posedge CLK_I);
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//       GO <= 0;
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         // wait for cycle to start
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         while (~CYC_O)
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           @(posedge CLK_I);
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         // wait for cycle to end
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         while (CYC_O)
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           @(posedge CLK_I);
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//      $display(" Writing %h to address %h", data, address);
154 
 
155 
      end
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   endtask // wr
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   // block read
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   task blkrd;
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      input [31:0] adr;
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      input end_flag;
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      output [31:0] result;
163 
 
164 
      begin
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         write_flag = 0;
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         cycle_end = end_flag;
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         address = adr;
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         GO <= 1;
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         @(posedge CLK_I);
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//       GO <= 0;
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         while (~(ACK_I & STB_O))
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           @(posedge CLK_I);
174 
 
175 
         result = data;
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      end
177 
   endtask // blkrd
178 
 
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   // block write
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   task blkwr;
181 
      input [31:0] adr;
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      input [31:0] dat;
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      input [3:0] sel;
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      input end_flag;
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      begin
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         write_flag = 1;
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         cycle_end = end_flag;
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         address = adr;
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         data = dat;
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         selects = sel;
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         GO <= 1;
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         @(posedge CLK_I);
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//       GO <= 0;
194 
 
195 
         while (~(ACK_I & STB_O))
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           @(posedge CLK_I);
197 
 
198 
      end
199 
   endtask // blkwr
200 
 
201 
   // RMW
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   task rmw;
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      input [31:0] adr;
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      input [31:0] dat;
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      input [3:0] sel;
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      output [31:0] result;
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      begin
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         // read phase
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         write_flag = 0;
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         cycle_end = 0;
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         address = adr;
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         GO <= 1;
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         @(posedge CLK_I);
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//       GO <= 0;
216 
 
217 
         while (~(ACK_I & STB_O))
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           @(posedge CLK_I);
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         result = data;
221 
 
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         // write phase
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         write_flag = 1;
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         address = adr;
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         selects = sel;
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         GO <= 1;
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         data <= dat;
228 
         cycle_end <= 1;
229 
         @(posedge CLK_I);
230 
//       GO <= 0;
231 
 
232 
         while (~(ACK_I & STB_O))
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           @(posedge CLK_I);
234 
 
235 
      end
236 
   endtask // rmw
237 
 
238 
   always @(posedge CLK_I)
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     begin
240 
        if (RST_I)
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          ADR_O <= 32'h0000_0000;
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        else
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          ADR_O <= address;
244 
     end
245 
 
246 
   always @(posedge CLK_I)
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     begin
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        if (RST_I | ERR_I | RTY_I)
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          CYC_O <= 1'b0;
250 
        else if ((cycle_end == 1) & ACK_I)
251 
          CYC_O <= 1'b0;
252 
        else if (GO | CYC_O) begin
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          CYC_O <= 1'b1;
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          GO <= 1'b0;
255 
        end
256 
     end
257 
 
258 
   // stb control
259 
   always @(posedge CLK_I)
260 
     begin
261 
        if (RST_I | ERR_I | RTY_I)
262 
          STB_O <= 1'b0;
263 
        else if (STB_O & ACK_I)
264 
          STB_O <= 1'b0;
265 
        else if (GO | STB_O)
266 
          STB_O <= 1'b1;
267 
     end
268 
 
269 
   // selects & data
270 
   always @(posedge CLK_I)
271 
     begin
272 
        if (write_flag == 0) begin
273 
           SEL_O <= 4'b1111;
274 
           if (STB_O & ACK_I)
275 
             data <= DAT_I;
276 
        end
277 
        else begin
278 
           case (data_width(address))
279 
             2'b00: begin
280 
                SEL_O <= {3'b000, selects[0]};
281 
                DAT_O <= {data[7:0], data[7:0], data[7:0], data[7:0]};
282 
             end
283 
             2'b01: begin
284 
                SEL_O <= {2'b00, selects[1:0]};
285 
                DAT_O <= {data[15:0], data[15:0]};
286 
             end
287 
             2'b10: begin
288 
                SEL_O <= selects;
289 
                DAT_O <= data;
290 
             end
291 
           endcase
292 
        end
293 
     end
294 
 
295 
   always @(posedge CLK_I)
296 
     begin
297 
        if (RST_I)
298 
          WE_O <= 1'b0;
299 
        else if (GO)
300 
          WE_O <= write_flag;
301 
     end
302 
 
303 
endmodule
304 
 
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