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[/] [graphicallcd/] [trunk/] [test_lcd.vhd] - Blame information for rev 4

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1 2 maihde 
-------------------------------------------------------------------------------
2 
-- This tests the graphical lcd code
3 
-------------------------------------------------------------------------------
4 
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
8 
 
9 
entity test_lcd is
10 
 
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  port (
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    DONE  : out   std_logic;
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    E     : out   std_logic;
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    R_W   : out   std_logic;
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    CS1   : out   std_logic;
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    CS2   : out   std_logic;
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    D_I   : out   std_logic;
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    DB    : inout std_logic_vector(7 downto 0);
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    CLK   : in    std_logic;
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    RST   : in    std_logic;
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    RAM_DIS : out std_logic);
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23 
end test_lcd;
24 
 
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architecture behavioral of test_lcd is
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  component graphical_lcd
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    port (
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      E     : out   std_logic;
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      R_W   : out   std_logic;
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      CS1   : out   std_logic;
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      CS2   : out   std_logic;
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      D_I   : out   std_logic;
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      DB    : inout std_logic_vector(7 downto 0);
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      CLK_I : in    std_logic;
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      RST_I : in    std_logic;
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      DAT_I : in    std_logic_vector(7 downto 0);
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      DAT_O : out   std_logic_vector(7 downto 0);
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      ACK_O : out   std_logic;
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      STB_I : in    std_logic;
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      WE_I  : in    std_logic;
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      TGD_I : in    std_logic_vector(2 downto 0));
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  end component;
43 
 
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  signal E_i     : std_logic;
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  signal R_W_i   : std_logic;
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  signal CS1_i   : std_logic;
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  signal CS2_i   : std_logic;
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  signal D_I_i   : std_logic;
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  signal DB_i    : std_logic_vector(7 downto 0);
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  signal CLK_i : std_logic;
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  signal RST_i : std_logic;
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  signal DAT_O_i : std_logic_vector(7 downto 0);
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  signal DAT_I_i : std_logic_vector(7 downto 0);
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  signal ACK_i : std_logic;
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  signal STB_i : std_logic;
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  signal WE_i  : std_logic;
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  signal TGD_i : std_logic_vector(2 downto 0);
58 
 
59 
  signal page : std_logic_vector(3 downto 0);
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  signal addr : std_logic_vector(6 downto 0);
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  signal lcd_wr : std_logic;
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  signal lcd_rd : std_logic;
63 
 
64 
  type lcd_state_type is (LCD_IDLE, LCD_DO_WR, LCD_DO_RD, LCD_WR_DONE, LCD_RD_DONE, LCD_READ_STATUS, LCD_STATUS_DONE, LCD_CHK_BUSY, LCD_WAIT_CLEAR);
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  type state_type is (IDLE, TURN_ON, SET_PAGE, SET_ADDR, DRAW_DATA, WAIT_COMPLETE, HALT);
66 
 
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  signal cur_state : state_type;
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  signal next_state : state_type;
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  signal lcd_state : lcd_state_type;
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  signal d_i_int : std_logic;
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  signal cs1_int : std_logic;
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  signal cs2_int : std_logic;
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begin  -- behavioral
74 
 
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  -- Map all the signals to the proper ports
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  E <= E_i;
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  R_W <= R_W_i;
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  CS1 <= CS1_i;
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  CS2 <= CS2_i;
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  D_I <= D_I_i;
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  CLK_i <= CLK;
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  RST_i <= RST;
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  DONE <= '1' when (cur_state = HALT) else '0';
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  RAM_DIS <= '1'; -- disable 'Flash RAM'
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  TGD_i(1) <= cs1_int;
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  TGD_i(2) <= cs2_int;
87 
 
88 
  lcd_op: process (CLK_i, RST_i)
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  begin  -- process
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    if RST_i = '1' then                 -- asynchronous reset (active low)
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      lcd_state <= LCD_IDLE;
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         STB_i <= '0';
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         WE_i <= '0';
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         TGD_i(0) <= '0';
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    elsif CLK_i'event and CLK_i = '1' then  -- rising clock edge
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      case lcd_state is
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        when LCD_IDLE =>
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          STB_i <= '0';
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          WE_i <= '0';
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                TGD_i(0) <= d_i_int;
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          if lcd_wr = '1' then
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            lcd_state <= LCD_DO_WR;
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          elsif lcd_rd = '1' then
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            lcd_state <= LCD_DO_RD;
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          else
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            lcd_state <= LCD_IDLE;
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          end if;
108 
 
109 
        when LCD_DO_WR =>
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          STB_i <= '1';
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          WE_i <= '1';
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                TGD_i(0) <= d_i_int;
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          if (ACK_i = '1') then
114 
            lcd_state <= LCD_WR_DONE;
115 
          end if;
116 
 
117 
        when LCD_WR_DONE =>
118 
          STB_i <= '0';
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          WE_i <= '0';
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                TGD_i(0) <= d_i_int;
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          if (ACK_i = '0') then
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            lcd_state <= LCD_READ_STATUS;
123 
          end if;
124 
 
125 
        when LCD_DO_RD =>
126 
          STB_i <= '1';
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          WE_i <= '0';
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                TGD_i(0) <= '0';
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          if (ACK_i = '1') then
130 
            lcd_state <= LCD_RD_DONE;
131 
          end if;
132 
 
133 
        when LCD_RD_DONE =>
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          STB_i <= '0';
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          WE_i <= '0';
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                TGD_i(0) <= '0';
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          if (ACK_i = '0') then
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            lcd_state <= LCD_READ_STATUS;
139 
          end if;
140 
 
141 
        when LCD_READ_STATUS =>
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          STB_i <= '1';
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          WE_i <= '0';
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                TGD_i(0) <= '0';
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          if (ACK_i = '1') then
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            lcd_state <= LCD_STATUS_DONE;
147 
          end if;
148 
 
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        when LCD_STATUS_DONE =>
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          STB_i <= '0';
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          WE_i <= '0';
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                TGD_i(0) <= '0';
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          if (ACK_i = '0') then
154 
            lcd_state <=  LCD_CHK_BUSY;
155 
          end if;
156 
 
157 
        when LCD_CHK_BUSY =>
158 
          if (DAT_O_i(7) = '0') then
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            lcd_state <= LCD_WAIT_CLEAR;
160 
                else
161 
                  lcd_state <= LCD_READ_STATUS;
162 
          end if;
163 
 
164 
        when LCD_WAIT_CLEAR =>
165 
          if (lcd_wr = '0') and (lcd_rd = '0') and (ACK_i = '0') then
166 
            lcd_state <= LCD_IDLE;
167 
          else
168 
                  lcd_state <= LCD_WAIT_CLEAR;
169 
          end if;
170 
 
171 
        when others => null;
172 
      end case;
173 
    end if;
174 
  end process;
175 
 
176 
  -- Draw lines on the lcd
177 
  draw: process (CLK_i, RST_i)
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  begin  -- process draw
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    if RST_i = '1' then
180 
      cur_state <= IDLE;
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      next_state <= IDLE;
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      d_i_int <= '0';
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         cs1_int <= '1';
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         cs2_int <= '1';
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      DAT_I_i <= "00000000";
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      lcd_wr <= '0';
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      lcd_rd <= '0';
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      page <= "0000";
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      addr <= "0000000";
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    elsif CLK_i'event and CLK_i = '1' then
191 
      case cur_state is
192 
        when IDLE =>
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          lcd_wr <= '0';
194 
          lcd_rd <= '0';
195 
                d_i_int <= '0';
196 
                cs1_int <= '1';
197 
                cs2_int <= '1';
198 
          cur_state <= TURN_ON;
199 
 
200 
        when TURN_ON =>
201 
          DAT_I_i <= "00111111";
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          d_i_int <= '0';
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                cs1_int <= '0';
204 
                cs2_int <= '0';
205 
          lcd_wr <= '1';
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          next_state <= SET_PAGE;
207 
          cur_state <= WAIT_COMPLETE;
208 
 
209 
        when SET_PAGE =>
210 
          DAT_I_i  <= "10111" & page(2 downto 0);
211 
          d_i_int <= '0';
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          cs1_int <= '0';
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                cs2_int <= '0';
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          lcd_wr <= '1';
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          addr <= "0000000";
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          if (page /= "1000") then
217 
            next_state <= SET_ADDR;
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          else
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            next_state <= HALT;
220 
          end if;
221 
          cur_state <= WAIT_COMPLETE;
222 
 
223 
        when SET_ADDR =>
224 
          DAT_I_i  <= "01" & addr(5 downto 0);
225 
          d_i_int <= '0';
226 
                cs1_int <= '0';
227 
          cs2_int <= '0';
228 
                lcd_wr <= '1';
229 
          next_state <= DRAW_DATA;
230 
          cur_state <= WAIT_COMPLETE;
231 
 
232 
        when DRAW_DATA =>
233 
          DAT_I_i  <= "01011010";
234 
          d_i_int <= '1';
235 
          cs1_int <= '0';
236 
                cs2_int <= '0';
237 
          lcd_wr <= '1';
238 
          if (addr /= "1000000") then
239 
                  addr <= addr + 1;
240 
            next_state <= DRAW_DATA;
241 
          else
242 
            page <= page + 1;
243 
            next_state <= SET_PAGE;
244 
          end if;
245 
          cur_state <= WAIT_COMPLETE;
246 
 
247 
        when WAIT_COMPLETE =>
248 
          lcd_wr <= '0';
249 
          lcd_rd <= '0';
250 
          if lcd_state = LCD_WAIT_CLEAR then
251 
            cur_state <= next_state;
252 
          end if;
253 
 
254 
        when HALT =>
255 
          cur_state <= HALT;
256 
 
257 
        when others => null;
258 
      end case;
259 
    end if;
260 
  end process draw;
261 
 
262 
  lcd_cntrl: graphical_lcd
263 
    port map (
264 
        E     => E_i,
265 
        R_W   => R_W_i,
266 
        CS1   => CS1_i,
267 
        CS2   => CS2_i,
268 
        D_I   => D_I_i,
269 
        DB    => DB,
270 
        CLK_I => CLK_i,
271 
        RST_I => RST_i,
272 
        DAT_I => DAT_I_i,
273 
        DAT_O => DAT_O_i,
274 
        ACK_O => ACK_i,
275 
        STB_I => STB_i,
276 
        WE_I  => WE_i,
277 
        TGD_I => TGD_i);
278 
 
279 
 
280 
end behavioral;
281 
 

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