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[/] [graphicsaccelerator/] [trunk/] [Synchronizer.syr] - Blame information for rev 2

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Release 12.3 - xst M.70d (lin)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
 
 
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
-->
Parameter xsthdpdir set to xst
 
 
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
-->
Reading design: Synchronizer.prj
 
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
        9.1) Device utilization summary
        9.2) Partition Resource Summary
        9.3) TIMING REPORT
 
 
=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "Synchronizer.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
 
---- Target Parameters
Output File Name                   : "Synchronizer"
Output Format                      : NGC
Target Device                      : xa3s200-4-ftg256
 
---- Source Options
Top Module Name                    : Synchronizer
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No
 
---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES
 
---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5
 
=========================================================================
 
 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/home/omar/LineFPGA/Synchronizer.vhd" in Library work.
Architecture behavioral of Entity synchronizer is up to date.
 
=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity  in library  (architecture ).
 
 
=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity  in library  (Architecture ).
Entity  analyzed. Unit  generated.
 
 
=========================================================================
*                           HDL Synthesis                               *
=========================================================================
 
Performing bidirectional port resolution...
 
Synthesizing Unit .
    Related source file is "/home/omar/LineFPGA/Synchronizer.vhd".
    Found finite state machine  for signal .
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 43                                             |
    | Inputs             | 5                                              |
    | Outputs            | 8                                              |
    | Clock              | Clk                       (rising_edge)        |
    | Reset              | YState$and0000            (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 01                                             |
    | Power Up State     | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine  for signal .
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 48364                                          |
    | Inputs             | 23                                             |
    | Outputs            | 5                                              |
    | Clock              | Clk                       (rising_edge)        |
    | Clock enable       | XState$not0000            (positive)           |
    | Power Up State     | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 9-bit subtractor for signal .
    Found 9-bit register for signal .
    Found 9-bit adder for signal .
    Found 11-bit adder for signal .
    Found 11-bit register for signal .
    Found 21-bit up counter for signal .
    Summary:
        inferred   2 Finite State Machine(s).
        inferred   1 Counter(s).
        inferred  20 D-type flip-flop(s).
        inferred   3 Adder/Subtractor(s).
Unit  synthesized.
 
 
=========================================================================
HDL Synthesis Report
 
Macro Statistics
# Adders/Subtractors                                   : 3
 11-bit adder                                          : 1
 9-bit adder                                           : 1
 9-bit subtractor                                      : 1
# Counters                                             : 1
 21-bit up counter                                     : 1
# Registers                                            : 2
 11-bit register                                       : 1
 9-bit register                                        : 1
 
=========================================================================
 
=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================
 
Analyzing FSM  for best encoding.
Optimizing FSM  on signal  with gray encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 11
 11    | 10
-------------------
Analyzing FSM  for best encoding.
Optimizing FSM  on signal  with gray encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 11
 11    | 10
-------------------
 
=========================================================================
Advanced HDL Synthesis Report
 
Macro Statistics
# FSMs                                                 : 2
# Adders/Subtractors                                   : 3
 11-bit adder                                          : 1
 9-bit adder                                           : 1
 9-bit subtractor                                      : 1
# Counters                                             : 1
 21-bit up counter                                     : 1
# Registers                                            : 20
 Flip-Flops                                            : 20
 
=========================================================================
 
=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
 
Optimizing unit  ...
 
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block Synchronizer, actual ratio is 3.
 
Final Macro Processing ...
 
=========================================================================
Final Register Report
 
Macro Statistics
# Registers                                            : 45
 Flip-Flops                                            : 45
 
=========================================================================
 
=========================================================================
*                           Partition Report                            *
=========================================================================
 
Partition Implementation Status
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : Synchronizer.ngr
Top Level Output File Name         : Synchronizer
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No
 
Design Statistics
# IOs                              : 28
 
Cell Usage :
# BELS                             : 164
#      GND                         : 1
#      INV                         : 3
#      LUT1                        : 20
#      LUT2                        : 15
#      LUT2_L                      : 5
#      LUT3                        : 17
#      LUT3_L                      : 4
#      LUT4                        : 40
#      LUT4_D                      : 10
#      LUT4_L                      : 4
#      MUXCY                       : 20
#      MUXF5                       : 3
#      VCC                         : 1
#      XORCY                       : 21
# FlipFlops/Latches                : 45
#      FD                          : 10
#      FDE                         : 2
#      FDR                         : 23
#      FDRE                        : 9
#      FDS                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 27
#      IBUF                        : 3
#      OBUF                        : 24
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : xa3s200ftg256-4
 
 Number of Slices:                       62  out of   1920     3%
 Number of Slice Flip Flops:             45  out of   3840     1%
 Number of 4 input LUTs:                118  out of   3840     3%
 Number of IOs:                          28
 Number of bonded IOBs:                  28  out of    173    16%
 Number of GCLKs:                         1  out of      8    12%
 
---------------------------
Partition Resource Summary:
---------------------------
 
  No Partitions were found in this design.
 
---------------------------
 
 
=========================================================================
TIMING REPORT
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
Clk                                | BUFGP                  | 45    |
-----------------------------------+------------------------+-------+
 
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
 
Timing Summary:
---------------
Speed Grade: -4
 
   Minimum period: 9.732ns (Maximum Frequency: 102.754MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 10.918ns
   Maximum combinational path delay: 8.957ns
 
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'Clk'
  Clock period: 9.732ns (frequency: 102.754MHz)
  Total number of paths / destination ports: 3100 / 89
-------------------------------------------------------------------------
Delay:               9.732ns (Levels of Logic = 5)
  Source:            Y_3 (FF)
  Destination:       Y_0 (FF)
  Source Clock:      Clk rising
  Destination Clock: Clk rising
 
  Data Path: Y_3 to Y_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.720   1.216  Y_3 (Y_3)
     LUT2_L:I0->LO         1   0.551   0.126  YState_cmp_eq00001_SW0 (N201)
     LUT4:I3->O            5   0.551   0.989  YState_cmp_eq00001 (N29)
     LUT4:I2->O           16   0.551   1.576  XState_FSM_FFd1-In15 (N2)
     LUT3:I0->O            1   0.551   0.000  Y_or0000_G (N51)
     MUXF5:I1->O          21   0.360   1.515  Y_or0000 (Y_or0000)
     FDR:R                     1.026          Y_0
    ----------------------------------------
    Total                      9.732ns (4.310ns logic, 5.422ns route)
                                       (44.3% logic, 55.7% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
  Total number of paths / destination ports: 64 / 24
-------------------------------------------------------------------------
Offset:              10.918ns (Levels of Logic = 3)
  Source:            AddressOfY_4 (FF)
  Destination:       AddressY<7> (PAD)
  Source Clock:      Clk rising
 
  Data Path: AddressOfY_4 to AddressY<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             3   0.720   1.246  AddressOfY_4 (AddressOfY_4)
     LUT4:I0->O            7   0.551   1.405  Madd_nAddressOfY_xor<5>1_SW0 (N01)
     LUT4:I0->O            1   0.551   0.801  Msub_AddressY_xor<7>11 (AddressY_7_OBUF)
     OBUF:I->O                 5.644          AddressY_7_OBUF (AddressY<7>)
    ----------------------------------------
    Total                     10.918ns (7.466ns logic, 3.452ns route)
                                       (68.4% logic, 31.6% route)
 
=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Delay:               8.957ns (Levels of Logic = 3)
  Source:            dataIn<1> (PAD)
  Destination:       B (PAD)
 
  Data Path: dataIn<1> to B
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.821   1.140  dataIn_1_IBUF (dataIn_1_IBUF)
     LUT2:I0->O            1   0.551   0.801  B2 (B_OBUF)
     OBUF:I->O                 5.644          B_OBUF (B)
    ----------------------------------------
    Total                      8.957ns (7.016ns logic, 1.941ns route)
                                       (78.3% logic, 21.7% route)
 
=========================================================================
 
 
Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.43 secs
 
-->
 
 
Total memory usage is 150684 kilobytes
 
Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)
 

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Subversion Repositories graphicsaccelerator

[/] [graphicsaccelerator/] [trunk/] [Synchronizer.syr] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	OmarMokhta	`Release 12.3 - xst M.70d (lin)`
2			`Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.`
3			`-->`
4			`Parameter TMPDIR set to xst/projnav.tmp`
5
6
7			`Total REAL time to Xst completion: 0.00 secs`
8			`Total CPU time to Xst completion: 0.08 secs`
9
10			`-->`
11			`Parameter xsthdpdir set to xst`
12
13
14			`Total REAL time to Xst completion: 0.00 secs`
15			`Total CPU time to Xst completion: 0.08 secs`
16
17			`-->`
18			`Reading design: Synchronizer.prj`
19
20			`TABLE OF CONTENTS`
21			`1) Synthesis Options Summary`
22			`2) HDL Compilation`
23			`3) Design Hierarchy Analysis`
24			`4) HDL Analysis`
25			`5) HDL Synthesis`
26			`5.1) HDL Synthesis Report`
27			`6) Advanced HDL Synthesis`
28			`6.1) Advanced HDL Synthesis Report`
29			`7) Low Level Synthesis`
30			`8) Partition Report`
31			`9) Final Report`
32			`9.1) Device utilization summary`
33			`9.2) Partition Resource Summary`
34			`9.3) TIMING REPORT`
35
36
37			`=========================================================================`
38			`* Synthesis Options Summary *`
39			`=========================================================================`
40			`---- Source Parameters`
41			`Input File Name : "Synchronizer.prj"`
42			`Input Format : mixed`
43			`Ignore Synthesis Constraint File : NO`
44
45			`---- Target Parameters`
46			`Output File Name : "Synchronizer"`
47			`Output Format : NGC`
48			`Target Device : xa3s200-4-ftg256`
49
50			`---- Source Options`
51			`Top Module Name : Synchronizer`
52			`Automatic FSM Extraction : YES`
53			`FSM Encoding Algorithm : Auto`
54			`Safe Implementation : No`
55			`FSM Style : LUT`
56			`RAM Extraction : Yes`
57			`RAM Style : Auto`
58			`ROM Extraction : Yes`
59			`Mux Style : Auto`
60			`Decoder Extraction : YES`
61			`Priority Encoder Extraction : Yes`
62			`Shift Register Extraction : YES`
63			`Logical Shifter Extraction : YES`
64			`XOR Collapsing : YES`
65			`ROM Style : Auto`
66			`Mux Extraction : Yes`
67			`Resource Sharing : YES`
68			`Asynchronous To Synchronous : NO`
69			`Multiplier Style : Auto`
70			`Automatic Register Balancing : No`
71
72			`---- Target Options`
73			`Add IO Buffers : YES`
74			`Global Maximum Fanout : 500`
75			`Add Generic Clock Buffer(BUFG) : 8`
76			`Register Duplication : YES`
77			`Slice Packing : YES`
78			`Optimize Instantiated Primitives : NO`
79			`Use Clock Enable : Yes`
80			`Use Synchronous Set : Yes`
81			`Use Synchronous Reset : Yes`
82			`Pack IO Registers into IOBs : Auto`
83			`Equivalent register Removal : YES`
84
85			`---- General Options`
86			`Optimization Goal : Speed`
87			`Optimization Effort : 1`
88			`Keep Hierarchy : No`
89			`Netlist Hierarchy : As_Optimized`
90			`RTL Output : Yes`
91			`Global Optimization : AllClockNets`
92			`Read Cores : YES`
93			`Write Timing Constraints : NO`
94			`Cross Clock Analysis : NO`
95			`Hierarchy Separator : /`
96			`Bus Delimiter : <>`
97			`Case Specifier : Maintain`
98			`Slice Utilization Ratio : 100`
99			`BRAM Utilization Ratio : 100`
100			`Verilog 2001 : YES`
101			`Auto BRAM Packing : NO`
102			`Slice Utilization Ratio Delta : 5`
103
104			`=========================================================================`
105
106
107			`=========================================================================`
108			`* HDL Compilation *`
109			`=========================================================================`
110			`Compiling vhdl file "/home/omar/LineFPGA/Synchronizer.vhd" in Library work.`
111			`Architecture behavioral of Entity synchronizer is up to date.`
112
113			`=========================================================================`
114			`* Design Hierarchy Analysis *`
115			`=========================================================================`
116			`Analyzing hierarchy for entity in library (architecture ).`
117
118
119			`=========================================================================`
120			`* HDL Analysis *`
121			`=========================================================================`
122			`Analyzing Entity in library (Architecture ).`
123			`Entity analyzed. Unit generated.`
124
125
126			`=========================================================================`
127			`* HDL Synthesis *`
128			`=========================================================================`
129
130			`Performing bidirectional port resolution...`
131
132			`Synthesizing Unit .`
133			`Related source file is "/home/omar/LineFPGA/Synchronizer.vhd".`
134			`Found finite state machine for signal .`
135			`-----------------------------------------------------------------------`
136			`\| States \| 4 \|`
137			`\| Transitions \| 43 \|`
138			`\| Inputs \| 5 \|`
139			`\| Outputs \| 8 \|`
140			`\| Clock \| Clk (rising_edge) \|`
141			`\| Reset \| YState$and0000 (positive) \|`
142			`\| Reset type \| synchronous \|`
143			`\| Reset State \| 01 \|`
144			`\| Power Up State \| 00 \|`
145			`\| Encoding \| automatic \|`
146			`\| Implementation \| LUT \|`
147			`-----------------------------------------------------------------------`
148			`Found finite state machine for signal .`
149			`-----------------------------------------------------------------------`
150			`\| States \| 4 \|`
151			`\| Transitions \| 48364 \|`
152			`\| Inputs \| 23 \|`
153			`\| Outputs \| 5 \|`
154			`\| Clock \| Clk (rising_edge) \|`
155			`\| Clock enable \| XState$not0000 (positive) \|`
156			`\| Power Up State \| 00 \|`
157			`\| Encoding \| automatic \|`
158			`\| Implementation \| LUT \|`
159			`-----------------------------------------------------------------------`
160			`Found 9-bit subtractor for signal .`
161			`Found 9-bit register for signal .`
162			`Found 9-bit adder for signal .`
163			`Found 11-bit adder for signal .`
164			`Found 11-bit register for signal .`
165			`Found 21-bit up counter for signal .`
166			`Summary:`
167			`inferred 2 Finite State Machine(s).`
168			`inferred 1 Counter(s).`
169			`inferred 20 D-type flip-flop(s).`
170			`inferred 3 Adder/Subtractor(s).`
171			`Unit synthesized.`
172
173
174			`=========================================================================`
175			`HDL Synthesis Report`
176
177			`Macro Statistics`
178			`# Adders/Subtractors : 3`
179			`11-bit adder : 1`
180			`9-bit adder : 1`
181			`9-bit subtractor : 1`
182			`# Counters : 1`
183			`21-bit up counter : 1`
184			`# Registers : 2`
185			`11-bit register : 1`
186			`9-bit register : 1`
187
188			`=========================================================================`
189
190			`=========================================================================`
191			`* Advanced HDL Synthesis *`
192			`=========================================================================`
193
194			`Analyzing FSM for best encoding.`
195			`Optimizing FSM on signal with gray encoding.`
196			`-------------------`
197			`State \| Encoding`
198			`-------------------`
199			`00 \| 00`
200			`01 \| 01`
201			`10 \| 11`
202			`11 \| 10`
203			`-------------------`
204			`Analyzing FSM for best encoding.`
205			`Optimizing FSM on signal with gray encoding.`
206			`-------------------`
207			`State \| Encoding`
208			`-------------------`
209			`00 \| 00`
210			`01 \| 01`
211			`10 \| 11`
212			`11 \| 10`
213			`-------------------`
214
215			`=========================================================================`
216			`Advanced HDL Synthesis Report`
217
218			`Macro Statistics`
219			`# FSMs : 2`
220			`# Adders/Subtractors : 3`
221			`11-bit adder : 1`
222			`9-bit adder : 1`
223			`9-bit subtractor : 1`
224			`# Counters : 1`
225			`21-bit up counter : 1`
226			`# Registers : 20`
227			`Flip-Flops : 20`
228
229			`=========================================================================`
230
231			`=========================================================================`
232			`* Low Level Synthesis *`
233			`=========================================================================`
234
235			`Optimizing unit ...`
236
237			`Mapping all equations...`
238			`Building and optimizing final netlist ...`
239			`Found area constraint ratio of 100 (+ 5) on block Synchronizer, actual ratio is 3.`
240
241			`Final Macro Processing ...`
242
243			`=========================================================================`
244			`Final Register Report`
245
246			`Macro Statistics`
247			`# Registers : 45`
248			`Flip-Flops : 45`
249
250			`=========================================================================`
251
252			`=========================================================================`
253			`* Partition Report *`
254			`=========================================================================`
255
256			`Partition Implementation Status`
257			`-------------------------------`
258
259			`No Partitions were found in this design.`
260
261			`-------------------------------`
262
263			`=========================================================================`
264			`* Final Report *`
265			`=========================================================================`
266			`Final Results`
267			`RTL Top Level Output File Name : Synchronizer.ngr`
268			`Top Level Output File Name : Synchronizer`
269			`Output Format : NGC`
270			`Optimization Goal : Speed`
271			`Keep Hierarchy : No`
272
273			`Design Statistics`
274			`# IOs : 28`
275
276			`Cell Usage :`
277			`# BELS : 164`
278			`# GND : 1`
279			`# INV : 3`
280			`# LUT1 : 20`
281			`# LUT2 : 15`
282			`# LUT2_L : 5`
283			`# LUT3 : 17`
284			`# LUT3_L : 4`
285			`# LUT4 : 40`
286			`# LUT4_D : 10`
287			`# LUT4_L : 4`
288			`# MUXCY : 20`
289			`# MUXF5 : 3`
290			`# VCC : 1`
291			`# XORCY : 21`
292			`# FlipFlops/Latches : 45`
293			`# FD : 10`
294			`# FDE : 2`
295			`# FDR : 23`
296			`# FDRE : 9`
297			`# FDS : 1`
298			`# Clock Buffers : 1`
299			`# BUFGP : 1`
300			`# IO Buffers : 27`
301			`# IBUF : 3`
302			`# OBUF : 24`
303			`=========================================================================`
304
305			`Device utilization summary:`
306			`---------------------------`
307
308			`Selected Device : xa3s200ftg256-4`
309
310			`Number of Slices: 62 out of 1920 3%`
311			`Number of Slice Flip Flops: 45 out of 3840 1%`
312			`Number of 4 input LUTs: 118 out of 3840 3%`
313			`Number of IOs: 28`
314			`Number of bonded IOBs: 28 out of 173 16%`
315			`Number of GCLKs: 1 out of 8 12%`
316
317			`---------------------------`
318			`Partition Resource Summary:`
319			`---------------------------`
320
321			`No Partitions were found in this design.`
322
323			`---------------------------`
324
325
326			`=========================================================================`
327			`TIMING REPORT`
328
329			`NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.`
330			`FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT`
331			`GENERATED AFTER PLACE-and-ROUTE.`
332
333			`Clock Information:`
334			`------------------`
335			`-----------------------------------+------------------------+-------+`
336			`Clock Signal \| Clock buffer(FF name) \| Load \|`
337			`-----------------------------------+------------------------+-------+`
338			`Clk \| BUFGP \| 45 \|`
339			`-----------------------------------+------------------------+-------+`
340
341			`Asynchronous Control Signals Information:`
342			`----------------------------------------`
343			`No asynchronous control signals found in this design`
344
345			`Timing Summary:`
346			`---------------`
347			`Speed Grade: -4`
348
349			`Minimum period: 9.732ns (Maximum Frequency: 102.754MHz)`
350			`Minimum input arrival time before clock: No path found`
351			`Maximum output required time after clock: 10.918ns`
352			`Maximum combinational path delay: 8.957ns`
353
354			`Timing Detail:`
355			`--------------`
356			`All values displayed in nanoseconds (ns)`
357
358			`=========================================================================`
359			`Timing constraint: Default period analysis for Clock 'Clk'`
360			`Clock period: 9.732ns (frequency: 102.754MHz)`
361			`Total number of paths / destination ports: 3100 / 89`
362			`-------------------------------------------------------------------------`
363			`Delay: 9.732ns (Levels of Logic = 5)`
364			`Source: Y_3 (FF)`
365			`Destination: Y_0 (FF)`
366			`Source Clock: Clk rising`
367			`Destination Clock: Clk rising`
368
369			`Data Path: Y_3 to Y_0`
370			`Gate Net`
371			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
372			`---------------------------------------- ------------`
373			`FDR:C->Q 2 0.720 1.216 Y_3 (Y_3)`
374			`LUT2_L:I0->LO 1 0.551 0.126 YState_cmp_eq00001_SW0 (N201)`
375			`LUT4:I3->O 5 0.551 0.989 YState_cmp_eq00001 (N29)`
376			`LUT4:I2->O 16 0.551 1.576 XState_FSM_FFd1-In15 (N2)`
377			`LUT3:I0->O 1 0.551 0.000 Y_or0000_G (N51)`
378			`MUXF5:I1->O 21 0.360 1.515 Y_or0000 (Y_or0000)`
379			`FDR:R 1.026 Y_0`
380			`----------------------------------------`
381			`Total 9.732ns (4.310ns logic, 5.422ns route)`
382			`(44.3% logic, 55.7% route)`
383
384			`=========================================================================`
385			`Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'`
386			`Total number of paths / destination ports: 64 / 24`
387			`-------------------------------------------------------------------------`
388			`Offset: 10.918ns (Levels of Logic = 3)`
389			`Source: AddressOfY_4 (FF)`
390			`Destination: AddressY<7> (PAD)`
391			`Source Clock: Clk rising`
392
393			`Data Path: AddressOfY_4 to AddressY<7>`
394			`Gate Net`
395			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
396			`---------------------------------------- ------------`
397			`FDRE:C->Q 3 0.720 1.246 AddressOfY_4 (AddressOfY_4)`
398			`LUT4:I0->O 7 0.551 1.405 Madd_nAddressOfY_xor<5>1_SW0 (N01)`
399			`LUT4:I0->O 1 0.551 0.801 Msub_AddressY_xor<7>11 (AddressY_7_OBUF)`
400			`OBUF:I->O 5.644 AddressY_7_OBUF (AddressY<7>)`
401			`----------------------------------------`
402			`Total 10.918ns (7.466ns logic, 3.452ns route)`
403			`(68.4% logic, 31.6% route)`
404
405			`=========================================================================`
406			`Timing constraint: Default path analysis`
407			`Total number of paths / destination ports: 3 / 3`
408			`-------------------------------------------------------------------------`
409			`Delay: 8.957ns (Levels of Logic = 3)`
410			`Source: dataIn<1> (PAD)`
411			`Destination: B (PAD)`
412
413			`Data Path: dataIn<1> to B`
414			`Gate Net`
415			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
416			`---------------------------------------- ------------`
417			`IBUF:I->O 1 0.821 1.140 dataIn_1_IBUF (dataIn_1_IBUF)`
418			`LUT2:I0->O 1 0.551 0.801 B2 (B_OBUF)`
419			`OBUF:I->O 5.644 B_OBUF (B)`
420			`----------------------------------------`
421			`Total 8.957ns (7.016ns logic, 1.941ns route)`
422			`(78.3% logic, 21.7% route)`
423
424			`=========================================================================`
425
426
427			`Total REAL time to Xst completion: 7.00 secs`
428			`Total CPU time to Xst completion: 6.43 secs`
429
430			`-->`
431
432
433			`Total memory usage is 150684 kilobytes`
434
435			`Number of errors : 0 ( 0 filtered)`
436			`Number of warnings : 0 ( 0 filtered)`
437			`Number of infos : 0 ( 0 filtered)`
438