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"/home/omar/LineFPGA/VGA_Top.vhd" line 127: Unconnected output port 'dbg' of component 'Bresenhamer'.
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Register <myX2<11>> in unit <Bresenhamer> has a constant value of 0 during circuit operation. The register is replaced by logic.
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Register <myX2<10>> in unit <Bresenhamer> has a constant value of 0 during circuit operation. The register is replaced by logic.
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Register <myY2<11>> in unit <Bresenhamer> has a constant value of 0 during circuit operation. The register is replaced by logic.
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Register <myY2<10>> in unit <Bresenhamer> has a constant value of 0 during circuit operation. The register is replaced by logic.
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Register <myY2<9>> in unit <Bresenhamer> has a constant value of 0 during circuit operation. The register is replaced by logic.
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Input <outX<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Input <outY<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Input <inX<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Input <inY<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Signal <minus_dx_plus_dy<10:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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Signal <minus_dx_minus_dy<10:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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Signal <dx_plus_dy<10:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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Signal <dx_minus_dy<10:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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Signal <condY1Y2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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Signal <condX1X2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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Input <syncX<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Input <syncY<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Input <syncX<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Input <syncY<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Signal <GPU_COLOR_TO_BUFFER> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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Signal <GIM> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
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The RAM <Mram_mybuffer> will be implemented as a BLOCK RAM, absorbing the following register(s):
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In block <VGA_Top>, Counter <Inst_FreqDiv/counter>
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The FF/Latch <dy_10> in Unit <Bresenhamer> is equivalent to the following FF/Latch, which will be removed : <dy_11>
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Node <Inst_Bresenhamer/p_0> of sequential type is unconnected in block <VGA_Top>.
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