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[/] [hd63701/] [trunk/] [HD63701_EXEC.v] - Blame information for rev 2

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1 2 thasega 
/***************************************************************************
2 
       This file is part of "HD63701V0 Compatible Processor Core".
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****************************************************************************/
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`timescale 1ps / 1ps
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`include "HD63701_defs.i"
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module HD63701_EXEC
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(
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        input                                           CLK,
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        input                                           RST,
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        input                   [7:0]            DI,
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        output    [15:0]         AD,
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        output reg                              RW,
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        output reg  [7:0]                DO,
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        input           `mcwidth                mcode,
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        output reg      [7:0]            vect,
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        output                                  inte,
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        input                                           fncu,
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        output  [15:0]           REG_D,
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        output  [15:0]           REG_X,
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        output  [15:0]           REG_S,
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        output   [5:0]           REG_C
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);
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// MicroCode Format
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wire       mcpi = mcode[0];
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wire [2:0] mcam = mcode[3:1];
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wire [2:0] mcph = mcode[6:4];
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wire [3:0] mcr2 = mcode[10:7];
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wire [3:0] mcr1 = mcode[14:11];
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wire [3:0] mcr0 = mcode[18:15];
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wire [4:0] mcop = mcode[23:19];
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wire              mcnw = (mcop==`mcCCB)|(mcop==`mcSCB)|(mcop==`mcAPC)|
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                                                (mcop==`mcLDV)|(mcop==`mcINT);
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wire [7:0] mccf = {mcr0,mcr1};   // case of mcCCB & mcSCB & mcAPC
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wire [7:0] mcva = {mcr0,mcr1};   // case of mcLDV & mcINT
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44 
 
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// Registers
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reg  [15:0] rT, rE, rD, rX, rS, rSp, rP;
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reg     [5:0]    rC;
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`define rA      rD[15:8]
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`define rB      rD[7:0]
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`define rU      rT[15:8]
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`define rV      rT[7:0]
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54 
 
55 
// ALU
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wire IsCCR   = (mcop==`mcCCB)|(mcop==`mcSCB);
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wire IsCChit = (({(rC[1]^rC[3]),rC} & mccf[6:0]) == 7'h0) ^ mccf[7];
58 
 
59 
wire [15:0] R0, R1, RR;
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wire  [5:0] CC;
61 
 
62 
HD63701_DSEL13 sR0(
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        .o(R0),
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        .f0((mcr0 == `mcrC)|IsCCR),.d0({10'b00000000_11,rC}),
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        .f1(mcr0 == `mcrA), .d1({8'h0,`rA}),
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        .f2(mcr0 == `mcrB), .d2({8'h0,`rB}),
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        .f3(mcr0 == `mcrD), .d3(rD),
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        .f4(mcr0 == `mcrX), .d4(rX),
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        .f5(mcr0 == `mcrS), .d5(rS),
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        .f6(mcr0 == `mcrP), .d6(rP),
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        .f7(mcr0 == `mcrU), .d7({8'h0,`rU}),
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        .f8(mcr0 == `mcrV), .d8({8'h0,`rV}),
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        .f9(mcr0 == `mcrN), .d9({DI,8'h0}),
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        .fA(mcr0 == `mcrM), .dA({8'h0,DI}),
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        .fB(mcr0 == `mcrT), .dB(rT),
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        .fC(mcr0 == `mcrE), .dC(rE)
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);
78 
 
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HD63701_DSEL13 sR1(
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        .o(R1),
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        .f0((mcr1 == `mcrC)|IsCCR),.d0({10'b00000000_11,rC}),
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        .f1(mcr1 == `mcrA), .d1({8'h0,`rA}),
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        .f2(mcr1 == `mcrB), .d2({8'h0,`rB}),
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        .f3(mcr1 == `mcrD), .d3(rD),
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        .f4(mcr1 == `mcrX), .d4(rX),
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        .f5(mcr1 == `mcrS), .d5(rS),
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        .f6(mcr1 == `mcrP), .d6(rP),
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        .f7(mcr1 == `mcrU), .d7({8'h0,`rU}),
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        .f8(mcr1 == `mcrV), .d8({8'h0,`rV}),
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        .f9(mcr1 == `mcrN), .d9({DI,8'h0}),
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        .fA(mcr1 == `mcrM), .dA({8'h0,DI}),
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        .fB(mcr1 == `mcrT), .dB(rT),
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        .fC(mcr1 == `mcrE), .dC(rE)
94 
);
95 
 
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HD63701_ALU ALU(
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        .op(mcop),.cf(mccf),.bw((mcr2==`mcrn) ? mcr0[2] : mcr2[2]),
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        .R0(R0),.R1(R1),.C(rC[0]),
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        .RR(RR),.RC(CC)
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);
101 
 
102 
 
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// Bus Control
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HD63701_DSEL8 sAB(
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        .o(AD),
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        .f0(mcam==`amPC), .d0(rP),
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        .f1(mcam==`amP1), .d1(rP+16'h1),
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        .f2(mcam==`amSP), .d2(rS),
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        .f3(mcam==`amS1), .d3(rS+16'h1),
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        .f4(mcam==`amX0), .d4(rX),
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        .f5(mcam==`amXT), .d5(rX+rT),
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        .f6(mcam==`amE0), .d6(rE),
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        .f7(mcam==`amE1), .d7(rE+16'h1)
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);
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116 
 
117 
// Update Registers
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reg [4:0] pmcop;
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always @( posedge CLK ) begin
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                  if (pmcop==`mcPSH) rS <= rSp-16'h1;
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        else if (pmcop==`mcPUL) rS <= rSp+16'h1;
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        else rS <= rSp;
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end
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wire noCCop = (mcop!=`mcLDV)&(mcop!=`mcLDN)&(mcop!=`mcPSH)&(mcop!=`mcPUL)&(mcop!=`mcAPC)&(mcop!=`mcTST)&(~fncu);
126 
wire noCCrg = (mcr2!=`mcrC )&(mcr2!=`mcrS )&(mcr2!=`mcrP )&(mcr0!=`mcrC );
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128 
always @( negedge CLK or posedge RST ) begin
129 
        if (RST) begin
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                pmcop <= 0;
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                vect <= 0;
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                rT   <= 0;
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                rE   <= 0;
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                rP   <= 0;
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                rC   <= 6'b010000;
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                DO   <= 0;
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        end
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        else begin
139 
                if ((mcr2!=`mcrP)&(mcpi==`pcI)) rP <= rP+16'h1;
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                if (noCCrg & noCCop) rC <= {CC[5],rC[4],CC[3:0]};
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                if (mcr2!=`mcrS) rSp <= rS;
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                case (mcop)
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                        `mcXTD: begin rT <= rX; rX <= rD; end
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                        `mcAPC: if (IsCChit) rP <= rP+{{8{rT[7]}},rT[7:0]};
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                        `mcINT: vect <= mcva;
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                        `mcLDV: rE   <= {8'hFF,mcva};
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                        `mcTST: rC   <= {rC[5:3],CC[2],rC[1:0]};
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                  default: case (mcr2)
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                                        `mcrA: `rA  <= RR[7:0];
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                                        `mcrB: `rB  <= RR[7:0];
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                                        `mcrC:  rC  <= RR[5:0];
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                                        `mcrD:  rD  <= RR;
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                                        `mcrX:  rX  <= RR;
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                                        `mcrS:  rSp <= RR;
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                                        `mcrP:  rP  <= RR;
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                                        `mcrU: `rU  <= RR[7:0];
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                                        `mcrV: `rV  <= RR[7:0];
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                                        `mcrT:  rT  <= RR;
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                                        `mcrE:  rE  <= RR;
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                                 default:;
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                        endcase
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                endcase
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                DO <=  mcnw ? 8'h0 :
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                                (mcr2==`mcrN) ? RR[15:8] :
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                           (mcr2==`mcrM) ? RR[ 7:0] :
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                                 8'h0;
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168 
                pmcop <= mcop;
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        end
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end
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wire RWRES = CLK;
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always @( negedge CLK or posedge RWRES ) begin
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        if (RWRES) RW <= 0;
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        else begin
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                RW <= ((mcr2==`mcrN)|(mcr2==`mcrM)) & (~mcnw);
177 
        end
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end
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180 
assign inte = ~rC[4];
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182 
 
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assign REG_D = rD;
184 
assign REG_X = rX;
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assign REG_S = rS;
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assign REG_C = rC;
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188 
endmodule
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190 
 
191 
module HD63701_DSEL13
192 
(
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        output [15:0] o,
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        input f0, input [15:0] d0,
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        input f1, input [15:0] d1,
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        input f2, input [15:0] d2,
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        input f3, input [15:0] d3,
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        input f4, input [15:0] d4,
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        input f5, input [15:0] d5,
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        input f6, input [15:0] d6,
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        input f7, input [15:0] d7,
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        input f8, input [15:0] d8,
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        input f9, input [15:0] d9,
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        input fA, input [15:0] dA,
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        input fB, input [15:0] dB,
207 
        input fC, input [15:0] dC
208 
);
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210 
assign o =
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                        f0 ? d0 :
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                        f1 ? d1 :
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                        f2 ? d2 :
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                        f3 ? d3 :
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                        f4 ? d4 :
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                        f5 ? d5 :
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                        f6 ? d6 :
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                        f7 ? d7 :
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                        f8 ? d8 :
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                        f9 ? d9 :
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                        fA ? dA :
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                        fB ? dB :
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                        fC ? dC :
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                        16'h0 ;
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226 
endmodule
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228 
 
229 
module HD63701_DSEL8
230 
(
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        output [15:0] o,
232 
 
233 
        input f0, input [15:0] d0,
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        input f1, input [15:0] d1,
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        input f2, input [15:0] d2,
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        input f3, input [15:0] d3,
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        input f4, input [15:0] d4,
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        input f5, input [15:0] d5,
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        input f6, input [15:0] d6,
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        input f7, input [15:0] d7
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);
242 
 
243 
assign o =
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                        f0 ? d0 :
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                        f1 ? d1 :
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                        f2 ? d2 :
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                        f3 ? d3 :
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                        f4 ? d4 :
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                        f5 ? d5 :
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                        f6 ? d6 :
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                        f7 ? d7 :
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                        16'h0 ;
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254 
endmodule
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