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[/] [hpdmc/] [trunk/] [hpdmc_ddr32/] [rtl/] [hpdmc_datactl.v] - Blame information for rev 21

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1 21 lekernel 
/*
2 
 * Milkymist VJ SoC
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 * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
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 *
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 * This program is free software: you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation, version 3 of the License.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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 */
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module hpdmc_datactl(
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        input sys_clk,
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        input sdram_rst,
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        input read,
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        input write,
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        input [3:0] concerned_bank,
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        output reg read_safe,
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        output reg write_safe,
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        output [3:0] precharge_safe,
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        output reg ack,
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        output reg direction,
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        output direction_r,
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        input tim_cas,
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        input [1:0] tim_wr
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);
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/*
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 * read_safe: whether it is safe to register a Read command
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 * into the SDRAM at the next cycle.
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 */
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reg [2:0] read_safe_counter;
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always @(posedge sys_clk) begin
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        if(sdram_rst) begin
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                read_safe_counter <= 3'd0;
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                read_safe <= 1'b1;
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        end else begin
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                if(read) begin
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                        read_safe_counter <= 3'd4;
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                        read_safe <= 1'b0;
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                end else if(write) begin
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                        /* after a write, read is unsafe for 5 cycles (4 transfers + tWTR=1) */
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                        read_safe_counter <= 3'd5;
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                        read_safe <= 1'b0;
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                end else begin
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                        if(read_safe_counter == 3'd1)
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                                read_safe <= 1'b1;
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                        if(~read_safe)
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                                read_safe_counter <= read_safe_counter - 3'd1;
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                end
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        end
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end
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/*
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 * write_safe: whether it is safe to register a Write command
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 * into the SDRAM at the next cycle.
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 */
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reg [2:0] write_safe_counter;
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always @(posedge sys_clk) begin
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        if(sdram_rst) begin
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                write_safe_counter <= 3'd0;
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                write_safe <= 1'b1;
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        end else begin
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                if(read) begin
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                        write_safe_counter <= {1'b1, tim_cas, ~tim_cas};
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                        write_safe <= 1'b0;
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                end else if(write) begin
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                        write_safe_counter <= 3'd3;
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                        write_safe <= 1'b0;
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                end else begin
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                        if(write_safe_counter == 3'd1)
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                                write_safe <= 1'b1;
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                        if(~write_safe)
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                                write_safe_counter <= write_safe_counter - 3'd1;
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                end
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        end
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end
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/* Generate ack signal.
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 * After write is asserted, it should pulse after 2 cycles.
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 * After read is asserted, it should pulse after CL+3 cycles, that is
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 * 5 cycles when tim_cas = 0
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 * 6 cycles when tim_cas = 1
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 */
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reg ack_read3;
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reg ack_read2;
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reg ack_read1;
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reg ack_read0;
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always @(posedge sys_clk) begin
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        if(sdram_rst) begin
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                ack_read3 <= 1'b0;
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                ack_read2 <= 1'b0;
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                ack_read1 <= 1'b0;
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                ack_read0 <= 1'b0;
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        end else begin
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                if(tim_cas) begin
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                        ack_read3 <= read;
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                        ack_read2 <= ack_read3;
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                        ack_read1 <= ack_read2;
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                        ack_read0 <= ack_read1;
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                end else begin
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                        ack_read2 <= read;
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                        ack_read1 <= ack_read2;
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                        ack_read0 <= ack_read1;
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                end
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        end
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end
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reg ack0;
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always @(posedge sys_clk) begin
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        if(sdram_rst) begin
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                ack0 <= 1'b0;
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                ack <= 1'b0;
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        end else begin
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                ack0 <= ack_read0|write;
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                ack <= ack0;
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        end
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end
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/* during a 4-word write, we drive the pins for 5 cycles
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 * and 1 cycle in advance (first word is invalid)
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 * so that we remove glitches on DQS without resorting
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 * to asynchronous logic.
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 */
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/* direction must be glitch-free, as it directly drives the
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 * tri-state enable for DQ and DQS.
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 */
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reg write_d;
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reg [2:0] counter_writedirection;
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always @(posedge sys_clk) begin
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        if(sdram_rst) begin
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                counter_writedirection <= 3'd0;
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                direction <= 1'b0;
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        end else begin
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                if(write_d) begin
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                        counter_writedirection <= 3'b101;
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                        direction <= 1'b1;
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                end else begin
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                        if(counter_writedirection == 3'b001)
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                                direction <= 1'b0;
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                        if(direction)
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                                counter_writedirection <= counter_writedirection - 3'd1;
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                end
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        end
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end
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assign direction_r = write_d|(|counter_writedirection);
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always @(posedge sys_clk) begin
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        if(sdram_rst)
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                write_d <= 1'b0;
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        else
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                write_d <= write;
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end
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/* Counters that prevent a busy bank from being precharged */
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hpdmc_banktimer banktimer0(
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        .sys_clk(sys_clk),
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        .sdram_rst(sdram_rst),
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        .tim_cas(tim_cas),
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        .tim_wr(tim_wr),
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        .read(read & concerned_bank[0]),
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        .write(write & concerned_bank[0]),
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        .precharge_safe(precharge_safe[0])
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);
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hpdmc_banktimer banktimer1(
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        .sys_clk(sys_clk),
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        .sdram_rst(sdram_rst),
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        .tim_cas(tim_cas),
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        .tim_wr(tim_wr),
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        .read(read & concerned_bank[1]),
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        .write(write & concerned_bank[1]),
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        .precharge_safe(precharge_safe[1])
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);
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hpdmc_banktimer banktimer2(
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        .sys_clk(sys_clk),
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        .sdram_rst(sdram_rst),
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197 
        .tim_cas(tim_cas),
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        .tim_wr(tim_wr),
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        .read(read & concerned_bank[2]),
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        .write(write & concerned_bank[2]),
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        .precharge_safe(precharge_safe[2])
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);
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hpdmc_banktimer banktimer3(
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        .sys_clk(sys_clk),
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        .sdram_rst(sdram_rst),
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        .tim_cas(tim_cas),
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        .tim_wr(tim_wr),
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        .read(read & concerned_bank[3]),
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        .write(write & concerned_bank[3]),
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        .precharge_safe(precharge_safe[3])
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);
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endmodule

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