OpenCores
URL https://opencores.org/ocsvn/hpdmc/hpdmc/trunk

Subversion Repositories hpdmc

[/] [hpdmc/] [trunk/] [hpdmc_ddr32/] [rtl/] [spartan6/] [hpdmc_iddr32.v] - Blame information for rev 21

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 21 lekernel 
/*
2 
 * Milkymist VJ SoC
3 
 * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
4 
 *
5 
 * This program is free software: you can redistribute it and/or modify
6 
 * it under the terms of the GNU General Public License as published by
7 
 * the Free Software Foundation, version 3 of the License.
8 
 *
9 
 * This program is distributed in the hope that it will be useful,
10 
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 
 * GNU General Public License for more details.
13 
 *
14 
 * You should have received a copy of the GNU General Public License
15 
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16 
 */
17 
 
18 
/*
19 
 * Verilog code that really should be replaced with a generate
20 
 * statement, but it does not work with some free simulators.
21 
 * So I put it in a module so as not to make other code unreadable,
22 
 * and keep compatibility with as many simulators as possible.
23 
 */
24 
 
25 
module hpdmc_iddr32 #(
26 
        parameter DDR_ALIGNMENT = "C0",
27 
        parameter INIT_Q0 = 1'b0,
28 
        parameter INIT_Q1 = 1'b0,
29 
        parameter SRTYPE = "ASYNC"
30 
) (
31 
        output [31:0] Q0,
32 
        output [31:0] Q1,
33 
        input C0,
34 
        input C1,
35 
        input CE,
36 
        input [31:0] D,
37 
        input R,
38 
        input S
39 
);
40 
 
41 
IDDR2 #(
42 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
43 
        .INIT_Q0(INIT_Q0),
44 
        .INIT_Q1(INIT_Q1),
45 
        .SRTYPE(SRTYPE)
46 
) iddr0 (
47 
        .Q0(Q0[0]),
48 
        .Q1(Q1[0]),
49 
        .C0(C0),
50 
        .C1(C1),
51 
        .CE(CE),
52 
        .D(D[0]),
53 
        .R(R),
54 
        .S(S)
55 
);
56 
IDDR2 #(
57 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
58 
        .INIT_Q0(INIT_Q0),
59 
        .INIT_Q1(INIT_Q1),
60 
        .SRTYPE(SRTYPE)
61 
) iddr1 (
62 
        .Q0(Q0[1]),
63 
        .Q1(Q1[1]),
64 
        .C0(C0),
65 
        .C1(C1),
66 
        .CE(CE),
67 
        .D(D[1]),
68 
        .R(R),
69 
        .S(S)
70 
);
71 
IDDR2 #(
72 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
73 
        .INIT_Q0(INIT_Q0),
74 
        .INIT_Q1(INIT_Q1),
75 
        .SRTYPE(SRTYPE)
76 
) iddr2 (
77 
        .Q0(Q0[2]),
78 
        .Q1(Q1[2]),
79 
        .C0(C0),
80 
        .C1(C1),
81 
        .CE(CE),
82 
        .D(D[2]),
83 
        .R(R),
84 
        .S(S)
85 
);
86 
IDDR2 #(
87 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
88 
        .INIT_Q0(INIT_Q0),
89 
        .INIT_Q1(INIT_Q1),
90 
        .SRTYPE(SRTYPE)
91 
) iddr3 (
92 
        .Q0(Q0[3]),
93 
        .Q1(Q1[3]),
94 
        .C0(C0),
95 
        .C1(C1),
96 
        .CE(CE),
97 
        .D(D[3]),
98 
        .R(R),
99 
        .S(S)
100 
);
101 
IDDR2 #(
102 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
103 
        .INIT_Q0(INIT_Q0),
104 
        .INIT_Q1(INIT_Q1),
105 
        .SRTYPE(SRTYPE)
106 
) iddr4 (
107 
        .Q0(Q0[4]),
108 
        .Q1(Q1[4]),
109 
        .C0(C0),
110 
        .C1(C1),
111 
        .CE(CE),
112 
        .D(D[4]),
113 
        .R(R),
114 
        .S(S)
115 
);
116 
IDDR2 #(
117 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
118 
        .INIT_Q0(INIT_Q0),
119 
        .INIT_Q1(INIT_Q1),
120 
        .SRTYPE(SRTYPE)
121 
) iddr5 (
122 
        .Q0(Q0[5]),
123 
        .Q1(Q1[5]),
124 
        .C0(C0),
125 
        .C1(C1),
126 
        .CE(CE),
127 
        .D(D[5]),
128 
        .R(R),
129 
        .S(S)
130 
);
131 
IDDR2 #(
132 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
133 
        .INIT_Q0(INIT_Q0),
134 
        .INIT_Q1(INIT_Q1),
135 
        .SRTYPE(SRTYPE)
136 
) iddr6 (
137 
        .Q0(Q0[6]),
138 
        .Q1(Q1[6]),
139 
        .C0(C0),
140 
        .C1(C1),
141 
        .CE(CE),
142 
        .D(D[6]),
143 
        .R(R),
144 
        .S(S)
145 
);
146 
IDDR2 #(
147 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
148 
        .INIT_Q0(INIT_Q0),
149 
        .INIT_Q1(INIT_Q1),
150 
        .SRTYPE(SRTYPE)
151 
) iddr7 (
152 
        .Q0(Q0[7]),
153 
        .Q1(Q1[7]),
154 
        .C0(C0),
155 
        .C1(C1),
156 
        .CE(CE),
157 
        .D(D[7]),
158 
        .R(R),
159 
        .S(S)
160 
);
161 
IDDR2 #(
162 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
163 
        .INIT_Q0(INIT_Q0),
164 
        .INIT_Q1(INIT_Q1),
165 
        .SRTYPE(SRTYPE)
166 
) iddr8 (
167 
        .Q0(Q0[8]),
168 
        .Q1(Q1[8]),
169 
        .C0(C0),
170 
        .C1(C1),
171 
        .CE(CE),
172 
        .D(D[8]),
173 
        .R(R),
174 
        .S(S)
175 
);
176 
IDDR2 #(
177 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
178 
        .INIT_Q0(INIT_Q0),
179 
        .INIT_Q1(INIT_Q1),
180 
        .SRTYPE(SRTYPE)
181 
) iddr9 (
182 
        .Q0(Q0[9]),
183 
        .Q1(Q1[9]),
184 
        .C0(C0),
185 
        .C1(C1),
186 
        .CE(CE),
187 
        .D(D[9]),
188 
        .R(R),
189 
        .S(S)
190 
);
191 
IDDR2 #(
192 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
193 
        .INIT_Q0(INIT_Q0),
194 
        .INIT_Q1(INIT_Q1),
195 
        .SRTYPE(SRTYPE)
196 
) iddr10 (
197 
        .Q0(Q0[10]),
198 
        .Q1(Q1[10]),
199 
        .C0(C0),
200 
        .C1(C1),
201 
        .CE(CE),
202 
        .D(D[10]),
203 
        .R(R),
204 
        .S(S)
205 
);
206 
IDDR2 #(
207 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
208 
        .INIT_Q0(INIT_Q0),
209 
        .INIT_Q1(INIT_Q1),
210 
        .SRTYPE(SRTYPE)
211 
) iddr11 (
212 
        .Q0(Q0[11]),
213 
        .Q1(Q1[11]),
214 
        .C0(C0),
215 
        .C1(C1),
216 
        .CE(CE),
217 
        .D(D[11]),
218 
        .R(R),
219 
        .S(S)
220 
);
221 
IDDR2 #(
222 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
223 
        .INIT_Q0(INIT_Q0),
224 
        .INIT_Q1(INIT_Q1),
225 
        .SRTYPE(SRTYPE)
226 
) iddr12 (
227 
        .Q0(Q0[12]),
228 
        .Q1(Q1[12]),
229 
        .C0(C0),
230 
        .C1(C1),
231 
        .CE(CE),
232 
        .D(D[12]),
233 
        .R(R),
234 
        .S(S)
235 
);
236 
IDDR2 #(
237 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
238 
        .INIT_Q0(INIT_Q0),
239 
        .INIT_Q1(INIT_Q1),
240 
        .SRTYPE(SRTYPE)
241 
) iddr13 (
242 
        .Q0(Q0[13]),
243 
        .Q1(Q1[13]),
244 
        .C0(C0),
245 
        .C1(C1),
246 
        .CE(CE),
247 
        .D(D[13]),
248 
        .R(R),
249 
        .S(S)
250 
);
251 
IDDR2 #(
252 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
253 
        .INIT_Q0(INIT_Q0),
254 
        .INIT_Q1(INIT_Q1),
255 
        .SRTYPE(SRTYPE)
256 
) iddr14 (
257 
        .Q0(Q0[14]),
258 
        .Q1(Q1[14]),
259 
        .C0(C0),
260 
        .C1(C1),
261 
        .CE(CE),
262 
        .D(D[14]),
263 
        .R(R),
264 
        .S(S)
265 
);
266 
IDDR2 #(
267 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
268 
        .INIT_Q0(INIT_Q0),
269 
        .INIT_Q1(INIT_Q1),
270 
        .SRTYPE(SRTYPE)
271 
) iddr15 (
272 
        .Q0(Q0[15]),
273 
        .Q1(Q1[15]),
274 
        .C0(C0),
275 
        .C1(C1),
276 
        .CE(CE),
277 
        .D(D[15]),
278 
        .R(R),
279 
        .S(S)
280 
);
281 
IDDR2 #(
282 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
283 
        .INIT_Q0(INIT_Q0),
284 
        .INIT_Q1(INIT_Q1),
285 
        .SRTYPE(SRTYPE)
286 
) iddr16 (
287 
        .Q0(Q0[16]),
288 
        .Q1(Q1[16]),
289 
        .C0(C0),
290 
        .C1(C1),
291 
        .CE(CE),
292 
        .D(D[16]),
293 
        .R(R),
294 
        .S(S)
295 
);
296 
IDDR2 #(
297 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
298 
        .INIT_Q0(INIT_Q0),
299 
        .INIT_Q1(INIT_Q1),
300 
        .SRTYPE(SRTYPE)
301 
) iddr17 (
302 
        .Q0(Q0[17]),
303 
        .Q1(Q1[17]),
304 
        .C0(C0),
305 
        .C1(C1),
306 
        .CE(CE),
307 
        .D(D[17]),
308 
        .R(R),
309 
        .S(S)
310 
);
311 
IDDR2 #(
312 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
313 
        .INIT_Q0(INIT_Q0),
314 
        .INIT_Q1(INIT_Q1),
315 
        .SRTYPE(SRTYPE)
316 
) iddr18 (
317 
        .Q0(Q0[18]),
318 
        .Q1(Q1[18]),
319 
        .C0(C0),
320 
        .C1(C1),
321 
        .CE(CE),
322 
        .D(D[18]),
323 
        .R(R),
324 
        .S(S)
325 
);
326 
IDDR2 #(
327 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
328 
        .INIT_Q0(INIT_Q0),
329 
        .INIT_Q1(INIT_Q1),
330 
        .SRTYPE(SRTYPE)
331 
) iddr19 (
332 
        .Q0(Q0[19]),
333 
        .Q1(Q1[19]),
334 
        .C0(C0),
335 
        .C1(C1),
336 
        .CE(CE),
337 
        .D(D[19]),
338 
        .R(R),
339 
        .S(S)
340 
);
341 
IDDR2 #(
342 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
343 
        .INIT_Q0(INIT_Q0),
344 
        .INIT_Q1(INIT_Q1),
345 
        .SRTYPE(SRTYPE)
346 
) iddr20 (
347 
        .Q0(Q0[20]),
348 
        .Q1(Q1[20]),
349 
        .C0(C0),
350 
        .C1(C1),
351 
        .CE(CE),
352 
        .D(D[20]),
353 
        .R(R),
354 
        .S(S)
355 
);
356 
IDDR2 #(
357 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
358 
        .INIT_Q0(INIT_Q0),
359 
        .INIT_Q1(INIT_Q1),
360 
        .SRTYPE(SRTYPE)
361 
) iddr21 (
362 
        .Q0(Q0[21]),
363 
        .Q1(Q1[21]),
364 
        .C0(C0),
365 
        .C1(C1),
366 
        .CE(CE),
367 
        .D(D[21]),
368 
        .R(R),
369 
        .S(S)
370 
);
371 
IDDR2 #(
372 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
373 
        .INIT_Q0(INIT_Q0),
374 
        .INIT_Q1(INIT_Q1),
375 
        .SRTYPE(SRTYPE)
376 
) iddr22 (
377 
        .Q0(Q0[22]),
378 
        .Q1(Q1[22]),
379 
        .C0(C0),
380 
        .C1(C1),
381 
        .CE(CE),
382 
        .D(D[22]),
383 
        .R(R),
384 
        .S(S)
385 
);
386 
IDDR2 #(
387 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
388 
        .INIT_Q0(INIT_Q0),
389 
        .INIT_Q1(INIT_Q1),
390 
        .SRTYPE(SRTYPE)
391 
) iddr23 (
392 
        .Q0(Q0[23]),
393 
        .Q1(Q1[23]),
394 
        .C0(C0),
395 
        .C1(C1),
396 
        .CE(CE),
397 
        .D(D[23]),
398 
        .R(R),
399 
        .S(S)
400 
);
401 
IDDR2 #(
402 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
403 
        .INIT_Q0(INIT_Q0),
404 
        .INIT_Q1(INIT_Q1),
405 
        .SRTYPE(SRTYPE)
406 
) iddr24 (
407 
        .Q0(Q0[24]),
408 
        .Q1(Q1[24]),
409 
        .C0(C0),
410 
        .C1(C1),
411 
        .CE(CE),
412 
        .D(D[24]),
413 
        .R(R),
414 
        .S(S)
415 
);
416 
IDDR2 #(
417 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
418 
        .INIT_Q0(INIT_Q0),
419 
        .INIT_Q1(INIT_Q1),
420 
        .SRTYPE(SRTYPE)
421 
) iddr25 (
422 
        .Q0(Q0[25]),
423 
        .Q1(Q1[25]),
424 
        .C0(C0),
425 
        .C1(C1),
426 
        .CE(CE),
427 
        .D(D[25]),
428 
        .R(R),
429 
        .S(S)
430 
);
431 
IDDR2 #(
432 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
433 
        .INIT_Q0(INIT_Q0),
434 
        .INIT_Q1(INIT_Q1),
435 
        .SRTYPE(SRTYPE)
436 
) iddr26 (
437 
        .Q0(Q0[26]),
438 
        .Q1(Q1[26]),
439 
        .C0(C0),
440 
        .C1(C1),
441 
        .CE(CE),
442 
        .D(D[26]),
443 
        .R(R),
444 
        .S(S)
445 
);
446 
IDDR2 #(
447 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
448 
        .INIT_Q0(INIT_Q0),
449 
        .INIT_Q1(INIT_Q1),
450 
        .SRTYPE(SRTYPE)
451 
) iddr27 (
452 
        .Q0(Q0[27]),
453 
        .Q1(Q1[27]),
454 
        .C0(C0),
455 
        .C1(C1),
456 
        .CE(CE),
457 
        .D(D[27]),
458 
        .R(R),
459 
        .S(S)
460 
);
461 
IDDR2 #(
462 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
463 
        .INIT_Q0(INIT_Q0),
464 
        .INIT_Q1(INIT_Q1),
465 
        .SRTYPE(SRTYPE)
466 
) iddr28 (
467 
        .Q0(Q0[28]),
468 
        .Q1(Q1[28]),
469 
        .C0(C0),
470 
        .C1(C1),
471 
        .CE(CE),
472 
        .D(D[28]),
473 
        .R(R),
474 
        .S(S)
475 
);
476 
IDDR2 #(
477 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
478 
        .INIT_Q0(INIT_Q0),
479 
        .INIT_Q1(INIT_Q1),
480 
        .SRTYPE(SRTYPE)
481 
) iddr29 (
482 
        .Q0(Q0[29]),
483 
        .Q1(Q1[29]),
484 
        .C0(C0),
485 
        .C1(C1),
486 
        .CE(CE),
487 
        .D(D[29]),
488 
        .R(R),
489 
        .S(S)
490 
);
491 
IDDR2 #(
492 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
493 
        .INIT_Q0(INIT_Q0),
494 
        .INIT_Q1(INIT_Q1),
495 
        .SRTYPE(SRTYPE)
496 
) iddr30 (
497 
        .Q0(Q0[30]),
498 
        .Q1(Q1[30]),
499 
        .C0(C0),
500 
        .C1(C1),
501 
        .CE(CE),
502 
        .D(D[30]),
503 
        .R(R),
504 
        .S(S)
505 
);
506 
IDDR2 #(
507 
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
508 
        .INIT_Q0(INIT_Q0),
509 
        .INIT_Q1(INIT_Q1),
510 
        .SRTYPE(SRTYPE)
511 
) iddr31 (
512 
        .Q0(Q0[31]),
513 
        .Q1(Q1[31]),
514 
        .C0(C0),
515 
        .C1(C1),
516 
        .CE(CE),
517 
        .D(D[31]),
518 
        .R(R),
519 
        .S(S)
520 
);
521 
 
522 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.