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[/] [hpdmc/] [trunk/] [hpdmc_ddr32/] [rtl/] [spartan6/] [hpdmc_oddr4.v] - Blame information for rev 21

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/*
 * Milkymist VJ SoC
 * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 3 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
 
/*
 * Verilog code that really should be replaced with a generate
 * statement, but it does not work with some free simulators.
 * So I put it in a module so as not to make other code unreadable,
 * and keep compatibility with as many simulators as possible.
 */
 
module hpdmc_oddr4 #(
        parameter DDR_ALIGNMENT = "C0",
        parameter INIT = 1'b0,
        parameter SRTYPE = "ASYNC"
) (
        output [3:0] Q,
        input C0,
        input C1,
        input CE,
        input [3:0] D0,
        input [3:0] D1,
        input R,
        input S
);
 
ODDR2 #(
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
) oddr0 (
        .Q(Q[0]),
        .C0(C0),
        .C1(C1),
        .CE(CE),
        .D0(D0[0]),
        .D1(D1[0]),
        .R(R),
        .S(S)
);
ODDR2 #(
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
) oddr1 (
        .Q(Q[1]),
        .C0(C0),
        .C1(C1),
        .CE(CE),
        .D0(D0[1]),
        .D1(D1[1]),
        .R(R),
        .S(S)
);
ODDR2 #(
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
) oddr2 (
        .Q(Q[2]),
        .C0(C0),
        .C1(C1),
        .CE(CE),
        .D0(D0[2]),
        .D1(D1[2]),
        .R(R),
        .S(S)
);
ODDR2 #(
        .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
) oddr3 (
        .Q(Q[3]),
        .C0(C0),
        .C1(C1),
        .CE(CE),
        .D0(D0[3]),
        .D1(D1[3]),
        .R(R),
        .S(S)
);
 
endmodule

Line No.	Rev	Author	Line
1	21	lekernel	`/*`
2			`* Milkymist VJ SoC`
3			`* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq`
4			`*`
5			`* This program is free software: you can redistribute it and/or modify`
6			`* it under the terms of the GNU General Public License as published by`
7			`* the Free Software Foundation, version 3 of the License.`
8			`*`
9			`* This program is distributed in the hope that it will be useful,`
10			`* but WITHOUT ANY WARRANTY; without even the implied warranty of`
11			`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
12			`* GNU General Public License for more details.`
13			`*`
14			`* You should have received a copy of the GNU General Public License`
15			`* along with this program. If not, see <http://www.gnu.org/licenses/>.`
16			`*/`
17
18			`/*`
19			`* Verilog code that really should be replaced with a generate`
20			`* statement, but it does not work with some free simulators.`
21			`* So I put it in a module so as not to make other code unreadable,`
22			`* and keep compatibility with as many simulators as possible.`
23			`*/`
24
25			`module hpdmc_oddr4 #(`
26			`parameter DDR_ALIGNMENT = "C0",`
27			`parameter INIT = 1'b0,`
28			`parameter SRTYPE = "ASYNC"`
29			`) (`
30			`output [3:0] Q,`
31			`input C0,`
32			`input C1,`
33			`input CE,`
34			`input [3:0] D0,`
35			`input [3:0] D1,`
36			`input R,`
37			`input S`
38			`);`
39
40			`ODDR2 #(`
41			`.DDR_ALIGNMENT(DDR_ALIGNMENT),`
42			`.INIT(INIT),`
43			`.SRTYPE(SRTYPE)`
44			`) oddr0 (`
45			`.Q(Q[0]),`
46			`.C0(C0),`
47			`.C1(C1),`
48			`.CE(CE),`
49			`.D0(D0[0]),`
50			`.D1(D1[0]),`
51			`.R(R),`
52			`.S(S)`
53			`);`
54			`ODDR2 #(`
55			`.DDR_ALIGNMENT(DDR_ALIGNMENT),`
56			`.INIT(INIT),`
57			`.SRTYPE(SRTYPE)`
58			`) oddr1 (`
59			`.Q(Q[1]),`
60			`.C0(C0),`
61			`.C1(C1),`
62			`.CE(CE),`
63			`.D0(D0[1]),`
64			`.D1(D1[1]),`
65			`.R(R),`
66			`.S(S)`
67			`);`
68			`ODDR2 #(`
69			`.DDR_ALIGNMENT(DDR_ALIGNMENT),`
70			`.INIT(INIT),`
71			`.SRTYPE(SRTYPE)`
72			`) oddr2 (`
73			`.Q(Q[2]),`
74			`.C0(C0),`
75			`.C1(C1),`
76			`.CE(CE),`
77			`.D0(D0[2]),`
78			`.D1(D1[2]),`
79			`.R(R),`
80			`.S(S)`
81			`);`
82			`ODDR2 #(`
83			`.DDR_ALIGNMENT(DDR_ALIGNMENT),`
84			`.INIT(INIT),`
85			`.SRTYPE(SRTYPE)`
86			`) oddr3 (`
87			`.Q(Q[3]),`
88			`.C0(C0),`
89			`.C1(C1),`
90			`.CE(CE),`
91			`.D0(D0[3]),`
92			`.D1(D1[3]),`
93			`.R(R),`
94			`.S(S)`
95			`);`
96
97			`endmodule`

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[/] [hpdmc/] [trunk/] [hpdmc_ddr32/] [rtl/] [spartan6/] [hpdmc_oddr4.v] - Blame information for rev 21