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[/] [hpdmc/] [trunk/] [hpdmc_ddr32/] [test/] [oddr2.v] - Blame information for rev 21

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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
 
// Modified for HPDMC simulation, based on Xilinx 01/12/09 revision
///////////////////////////////////////////////////////////////////////////////
 
`timescale 1 ps / 1 ps
 
module ODDR2 (Q, C0, C1, CE, D0, D1, R, S);
 
    output Q;
 
    input C0;
    input C1;
    input CE;
    input D0;
    input D1;
 
    input R;
    input S;
 
    parameter DDR_ALIGNMENT = "NONE";
    parameter INIT = 1'b0;
    parameter SRTYPE = "SYNC";
 
    pullup   P1 (CE);
    pulldown P2 (R);
    pulldown P3 (S);
 
    reg q_out, q_d1_c0_out_int;
    wire PC0, PC1;
 
    buf buf_q (Q, q_out);
 
 
    initial begin
 
        if ((INIT != 1'b0) && (INIT != 1'b1)) begin
            $display("Attribute Syntax Error : The attribute INIT on ODDR2 instance %m is set to %d.  Legal values for this attribute are 0 or 1.", INIT);
            $finish;
        end
 
        if ((DDR_ALIGNMENT != "NONE") && (DDR_ALIGNMENT != "C0") && (DDR_ALIGNMENT != "C1")) begin
            $display("Attribute Syntax Error : The attribute DDR_ALIGNMENT on ODDR2 instance %m is set to %s.  Legal values for this attribute are NONE, C0 or C1.", DDR_ALIGNMENT);
            $finish;
        end
 
        if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
            $display("Attribute Syntax Error : The attribute SRTYPE on ODDR2 instance %m is set to %s.  Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
            $finish;
        end
 
    end // initial begin
 
    initial begin
        assign q_out = INIT;
        assign q_d1_c0_out_int = INIT;
    end
 
    always @(R or S) begin
 
            deassign q_out;
            deassign q_d1_c0_out_int;
 
            if (SRTYPE == "ASYNC") begin
                if (R == 1) begin
                    assign q_out = 0;
                    assign q_d1_c0_out_int = 0;
                end
                else if (R == 0 && S == 1) begin
                    assign q_out = 1;
                    assign q_d1_c0_out_int = 1;
                end
            end // if (SRTYPE == "ASYNC")
 
    end // always @ (GSR or R or S)
 
    assign PC0 = ((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))?  C0 : C1;
    assign PC1 = ((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))?  C1 : C0;
 
    always @(posedge PC0) begin
 
        if (R == 1 && SRTYPE == "SYNC") begin
            q_out <= 0;
            q_d1_c0_out_int <= 0;
        end
        else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
            q_out <= 1;
            q_d1_c0_out_int <= 1;
        end
        else if (CE == 1 && R == 0 && S == 0) begin
                q_out <= D0;
                q_d1_c0_out_int <= D1 ;
        end // if (CE == 1 && R == 0 && S == 0)
 
    end // always @ (posedge C0)
 
 
    always @(posedge PC1) begin
 
        if (R == 1 && SRTYPE == "SYNC") begin
            q_out <= 0;
        end
        else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
            q_out <= 1;
            end
        else if (CE == 1 && R == 0 && S == 0) begin
 
            if (DDR_ALIGNMENT == "NONE")
                q_out <= D1;
            else
                q_out <= q_d1_c0_out_int;
 
 
        end // if (CE == 1 && R == 0 && S == 0)
 
    end // always @ (negedge c_in)
 
 
    specify
 
        if (C0) (C0 => Q) = (100, 100);
        if (C1) (C1 => Q) = (100, 100);
        specparam PATHPULSE$ = 0;
 
    endspecify
 
endmodule // ODDR2
 

Line No.	Rev	Author	Line
1	21	lekernel	`///////////////////////////////////////////////////////////////////////////////`
2			`// Copyright (c) 1995/2004 Xilinx, Inc.`
3			`// All Right Reserved.`
4			`///////////////////////////////////////////////////////////////////////////////`
5
6			`// Modified for HPDMC simulation, based on Xilinx 01/12/09 revision`
7			`///////////////////////////////////////////////////////////////////////////////`
8
9			`timescale 1 ps / 1 ps
10
11			`module ODDR2 (Q, C0, C1, CE, D0, D1, R, S);`
12
13			`output Q;`
14
15			`input C0;`
16			`input C1;`
17			`input CE;`
18			`input D0;`
19			`input D1;`
20
21			`input R;`
22			`input S;`
23
24			`parameter DDR_ALIGNMENT = "NONE";`
25			`parameter INIT = 1'b0;`
26			`parameter SRTYPE = "SYNC";`
27
28			`pullup P1 (CE);`
29			`pulldown P2 (R);`
30			`pulldown P3 (S);`
31
32			`reg q_out, q_d1_c0_out_int;`
33			`wire PC0, PC1;`
34
35			`buf buf_q (Q, q_out);`
36
37
38			`initial begin`
39
40			`if ((INIT != 1'b0) && (INIT != 1'b1)) begin`
41			`$display("Attribute Syntax Error : The attribute INIT on ODDR2 instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT);`
42			`$finish;`
43			`end`
44
45			`if ((DDR_ALIGNMENT != "NONE") && (DDR_ALIGNMENT != "C0") && (DDR_ALIGNMENT != "C1")) begin`
46			`$display("Attribute Syntax Error : The attribute DDR_ALIGNMENT on ODDR2 instance %m is set to %s. Legal values for this attribute are NONE, C0 or C1.", DDR_ALIGNMENT);`
47			`$finish;`
48			`end`
49
50			`if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin`
51			`$display("Attribute Syntax Error : The attribute SRTYPE on ODDR2 instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE);`
52			`$finish;`
53			`end`
54
55			`end // initial begin`
56
57			`initial begin`
58			`assign q_out = INIT;`
59			`assign q_d1_c0_out_int = INIT;`
60			`end`
61
62			`always @(R or S) begin`
63
64			`deassign q_out;`
65			`deassign q_d1_c0_out_int;`
66
67			`if (SRTYPE == "ASYNC") begin`
68			`if (R == 1) begin`
69			`assign q_out = 0;`
70			`assign q_d1_c0_out_int = 0;`
71			`end`
72			`else if (R == 0 && S == 1) begin`
73			`assign q_out = 1;`
74			`assign q_d1_c0_out_int = 1;`
75			`end`
76			`end // if (SRTYPE == "ASYNC")`
77
78			`end // always @ (GSR or R or S)`
79
80			`assign PC0 = ((DDR_ALIGNMENT== "C0") \|\| (DDR_ALIGNMENT== "NONE"))? C0 : C1;`
81			`assign PC1 = ((DDR_ALIGNMENT== "C0") \|\| (DDR_ALIGNMENT== "NONE"))? C1 : C0;`
82
83			`always @(posedge PC0) begin`
84
85			`if (R == 1 && SRTYPE == "SYNC") begin`
86			`q_out <= 0;`
87			`q_d1_c0_out_int <= 0;`
88			`end`
89			`else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin`
90			`q_out <= 1;`
91			`q_d1_c0_out_int <= 1;`
92			`end`
93			`else if (CE == 1 && R == 0 && S == 0) begin`
94			`q_out <= D0;`
95			`q_d1_c0_out_int <= D1 ;`
96			`end // if (CE == 1 && R == 0 && S == 0)`
97
98			`end // always @ (posedge C0)`
99
100
101			`always @(posedge PC1) begin`
102
103			`if (R == 1 && SRTYPE == "SYNC") begin`
104			`q_out <= 0;`
105			`end`
106			`else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin`
107			`q_out <= 1;`
108			`end`
109			`else if (CE == 1 && R == 0 && S == 0) begin`
110
111			`if (DDR_ALIGNMENT == "NONE")`
112			`q_out <= D1;`
113			`else`
114			`q_out <= q_d1_c0_out_int;`
115
116
117			`end // if (CE == 1 && R == 0 && S == 0)`
118
119			`end // always @ (negedge c_in)`
120
121
122			`specify`
123
124			`if (C0) (C0 => Q) = (100, 100);`
125			`if (C1) (C1 => Q) = (100, 100);`
126			`specparam PATHPULSE$ = 0;`
127
128			`endspecify`
129
130			`endmodule // ODDR2`
131

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[/] [hpdmc/] [trunk/] [hpdmc_ddr32/] [test/] [oddr2.v] - Blame information for rev 21