URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_3/] [rtl/] [verilog/] [i2c_master_byte_ctrl.v] - Blame information for rev 69

Go to most recent revision | Details | Compare with Previous | View Log


/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE rev.B2 compliant I2C Master byte-controller       ////
////                                                             ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: i2c_master_byte_ctrl.v,v 1.6 2003-08-09 07:01:33 rherveille Exp $
//
//  $Date: 2003-08-09 07:01:33 $
//  $Revision: 1.6 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.5  2002/12/26 15:02:32  rherveille
//               Core is now a Multimaster I2C controller
//
//               Revision 1.4  2002/11/30 22:24:40  rherveille
//               Cleaned up code
//
//               Revision 1.3  2001/11/05 11:59:25  rherveille
//               Fixed wb_ack_o generation bug.
//               Fixed bug in the byte_controller statemachine.
//               Added headers.
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`include "i2c_master_defines.v"
 
module i2c_master_byte_ctrl (
        clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,
        cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
 
        //
        // inputs & outputs
        //
        input clk;     // master clock
        input rst;     // synchronous active high reset
        input nReset;  // asynchronous active low reset
        input ena;     // core enable signal
 
        input [15:0] clk_cnt; // 4x SCL
 
        // control inputs
        input       start;
        input       stop;
        input       read;
        input       write;
        input       ack_in;
        input [7:0] din;
 
        // status outputs
        output       cmd_ack;
        reg cmd_ack;
        output       ack_out;
        reg ack_out;
        output       i2c_busy;
        output       i2c_al;
        output [7:0] dout;
 
        // I2C signals
        input  scl_i;
        output scl_o;
        output scl_oen;
        input  sda_i;
        output sda_o;
        output sda_oen;
 
 
        //
        // Variable declarations
        //
 
        // statemachine
        parameter [4:0] ST_IDLE  = 5'b0_0000;
        parameter [4:0] ST_START = 5'b0_0001;
        parameter [4:0] ST_READ  = 5'b0_0010;
        parameter [4:0] ST_WRITE = 5'b0_0100;
        parameter [4:0] ST_ACK   = 5'b0_1000;
        parameter [4:0] ST_STOP  = 5'b1_0000;
 
        // signals for bit_controller
        reg  [3:0] core_cmd;
        reg        core_txd;
        wire       core_ack, core_rxd;
 
        // signals for shift register
        reg [7:0] sr; //8bit shift register
        reg       shift, ld;
 
        // signals for state machine
        wire       go;
        reg  [2:0] dcnt;
        wire       cnt_done;
 
        //
        // Module body
        //
 
        // hookup bit_controller
        i2c_master_bit_ctrl bit_controller (
                .clk     ( clk      ),
                .rst     ( rst      ),
                .nReset  ( nReset   ),
                .ena     ( ena      ),
                .clk_cnt ( clk_cnt  ),
                .cmd     ( core_cmd ),
                .cmd_ack ( core_ack ),
                .busy    ( i2c_busy ),
                .al      ( i2c_al   ),
                .din     ( core_txd ),
                .dout    ( core_rxd ),
                .scl_i   ( scl_i    ),
                .scl_o   ( scl_o    ),
                .scl_oen ( scl_oen  ),
                .sda_i   ( sda_i    ),
                .sda_o   ( sda_o    ),
                .sda_oen ( sda_oen  )
        );
 
        // generate go-signal
        assign go = (read | write | stop) & ~cmd_ack;
 
        // assign dout output to shift-register
        assign dout = sr;
 
        // generate shift register
        always @(posedge clk or negedge nReset)
          if (!nReset)
            sr <= #1 8'h0;
          else if (rst)
            sr <= #1 8'h0;
          else if (ld)
            sr <= #1 din;
          else if (shift)
            sr <= #1 {sr[6:0], core_rxd};
 
        // generate counter
        always @(posedge clk or negedge nReset)
          if (!nReset)
            dcnt <= #1 3'h0;
          else if (rst)
            dcnt <= #1 3'h0;
          else if (ld)
            dcnt <= #1 3'h7;
          else if (shift)
            dcnt <= #1 dcnt - 3'h1;
 
        assign cnt_done = ~(|dcnt);
 
        //
        // state machine
        //
        reg [4:0] c_state; // synopsis enum_state
 
        always @(posedge clk or negedge nReset)
          if (!nReset)
            begin
                core_cmd <= #1 `I2C_CMD_NOP;
                core_txd <= #1 1'b0;
                shift    <= #1 1'b0;
                ld       <= #1 1'b0;
                cmd_ack  <= #1 1'b0;
                c_state  <= #1 ST_IDLE;
                ack_out  <= #1 1'b0;
            end
          else if (rst | i2c_al)
           begin
               core_cmd <= #1 `I2C_CMD_NOP;
               core_txd <= #1 1'b0;
               shift    <= #1 1'b0;
               ld       <= #1 1'b0;
               cmd_ack  <= #1 1'b0;
               c_state  <= #1 ST_IDLE;
               ack_out  <= #1 1'b0;
           end
        else
          begin
              // initially reset all signals
              core_txd <= #1 sr[7];
              shift    <= #1 1'b0;
              ld       <= #1 1'b0;
              cmd_ack  <= #1 1'b0;
 
              case (c_state) // synopsis full_case parallel_case
                ST_IDLE:
                  if (go)
                    begin
                        if (start)
                          begin
                              c_state  <= #1 ST_START;
                              core_cmd <= #1 `I2C_CMD_START;
                          end
                        else if (read)
                          begin
                              c_state  <= #1 ST_READ;
                              core_cmd <= #1 `I2C_CMD_READ;
                          end
                        else if (write)
                          begin
                              c_state  <= #1 ST_WRITE;
                              core_cmd <= #1 `I2C_CMD_WRITE;
                          end
                        else // stop
                          begin
                              c_state  <= #1 ST_STOP;
                              core_cmd <= #1 `I2C_CMD_STOP;
 
                              // generate command acknowledge signal
                              cmd_ack  <= #1 1'b1;
                          end
 
                        ld <= #1 1'b1;
                    end
 
                ST_START:
                  if (core_ack)
                    begin
                        if (read)
                          begin
                              c_state  <= #1 ST_READ;
                              core_cmd <= #1 `I2C_CMD_READ;
                          end
                        else
                          begin
                              c_state  <= #1 ST_WRITE;
                              core_cmd <= #1 `I2C_CMD_WRITE;
                          end
 
                        ld <= #1 1'b1;
                    end
 
                ST_WRITE:
                  if (core_ack)
                    if (cnt_done)
                      begin
                          c_state  <= #1 ST_ACK;
                          core_cmd <= #1 `I2C_CMD_READ;
                      end
                    else
                      begin
                          c_state  <= #1 ST_WRITE;       // stay in same state
                          core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
                          shift    <= #1 1'b1;
                      end
 
                ST_READ:
                  if (core_ack)
                    begin
                        if (cnt_done)
                          begin
                              c_state  <= #1 ST_ACK;
                              core_cmd <= #1 `I2C_CMD_WRITE;
                          end
                        else
                          begin
                              c_state  <= #1 ST_READ;       // stay in same state
                              core_cmd <= #1 `I2C_CMD_READ; // read next bit
                          end
 
                        shift    <= #1 1'b1;
                        core_txd <= #1 ack_in;
                    end
 
                ST_ACK:
                  if (core_ack)
                    begin
                       if (stop)
                         begin
                             c_state  <= #1 ST_STOP;
                             core_cmd <= #1 `I2C_CMD_STOP;
                         end
                       else
                         begin
                             c_state  <= #1 ST_IDLE;
                             core_cmd <= #1 `I2C_CMD_NOP;
 
                             // generate command acknowledge signal
                             cmd_ack  <= #1 1'b1;
                         end
 
                         // assign ack_out output to bit_controller_rxd (contains last received bit)
                         ack_out <= #1 core_rxd;
 
//                       // generate command acknowledge signal
//                       cmd_ack  <= #1 1'b1;
 
                         core_txd <= #1 1'b1;
                     end
                   else
                     core_txd <= #1 ack_in;
 
                ST_STOP:
                  if (core_ack)
                    begin
                        c_state  <= #1 ST_IDLE;
                        core_cmd <= #1 `I2C_CMD_NOP;
 
                        // generate command acknowledge signal
                        cmd_ack  <= #1 1'b1;
                    end
 
              endcase
          end
endmodule

Line No.	Rev	Author	Line
1	14	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE rev.B2 compliant I2C Master byte-controller ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/i2c/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	10	rherveille	`//`
40	38	rherveille	`// $Id: i2c_master_byte_ctrl.v,v 1.6 2003-08-09 07:01:33 rherveille Exp $`
41	10	rherveille	`//`
42	38	rherveille	`// $Date: 2003-08-09 07:01:33 $`
43			`// $Revision: 1.6 $`
44	14	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47	10	rherveille	`//`
48	14	rherveille	`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	38	rherveille	`// Revision 1.5 2002/12/26 15:02:32 rherveille`
51			`// Core is now a Multimaster I2C controller`
52			`//`
53	29	rherveille	`// Revision 1.4 2002/11/30 22:24:40 rherveille`
54			`// Cleaned up code`
55			`//`
56	27	rherveille	`// Revision 1.3 2001/11/05 11:59:25 rherveille`
57			`// Fixed wb_ack_o generation bug.`
58			`// Fixed bug in the byte_controller statemachine.`
59			`// Added headers.`
60			`//`
61	10	rherveille
62	29	rherveille	`// synopsys translate_off`
63	10	rherveille	`include "timescale.v"
64	29	rherveille	`// synopsys translate_on`
65
66	10	rherveille	`include "i2c_master_defines.v"
67
68			`module i2c_master_byte_ctrl (`
69			`clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,`
70	29	rherveille	`cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );`
71	10	rherveille
72			`//`
73			`// inputs & outputs`
74			`//`
75			`input clk; // master clock`
76			`input rst; // synchronous active high reset`
77			`input nReset; // asynchronous active low reset`
78			`input ena; // core enable signal`
79
80			`input [15:0] clk_cnt; // 4x SCL`
81
82			`// control inputs`
83			`input start;`
84			`input stop;`
85			`input read;`
86			`input write;`
87			`input ack_in;`
88			`input [7:0] din;`
89
90			`// status outputs`
91			`output cmd_ack;`
92			`reg cmd_ack;`
93			`output ack_out;`
94			`reg ack_out;`
95			`output i2c_busy;`
96	29	rherveille	`output i2c_al;`
97	10	rherveille	`output [7:0] dout;`
98
99			`// I2C signals`
100			`input scl_i;`
101			`output scl_o;`
102			`output scl_oen;`
103			`input sda_i;`
104			`output sda_o;`
105			`output sda_oen;`
106
107
108			`//`
109			`// Variable declarations`
110			`//`
111
112			`// statemachine`
113			`parameter [4:0] ST_IDLE = 5'b0_0000;`
114			`parameter [4:0] ST_START = 5'b0_0001;`
115			`parameter [4:0] ST_READ = 5'b0_0010;`
116			`parameter [4:0] ST_WRITE = 5'b0_0100;`
117			`parameter [4:0] ST_ACK = 5'b0_1000;`
118			`parameter [4:0] ST_STOP = 5'b1_0000;`
119
120			`// signals for bit_controller`
121			`reg [3:0] core_cmd;`
122			`reg core_txd;`
123			`wire core_ack, core_rxd;`
124
125			`// signals for shift register`
126			`reg [7:0] sr; //8bit shift register`
127			`reg shift, ld;`
128
129			`// signals for state machine`
130			`wire go;`
131	14	rherveille	`reg [2:0] dcnt;`
132	10	rherveille	`wire cnt_done;`
133
134			`//`
135			`// Module body`
136			`//`
137
138			`// hookup bit_controller`
139			`i2c_master_bit_ctrl bit_controller (`
140	27	rherveille	`.clk ( clk ),`
141			`.rst ( rst ),`
142			`.nReset ( nReset ),`
143			`.ena ( ena ),`
144			`.clk_cnt ( clk_cnt ),`
145			`.cmd ( core_cmd ),`
146			`.cmd_ack ( core_ack ),`
147			`.busy ( i2c_busy ),`
148	29	rherveille	`.al ( i2c_al ),`
149	27	rherveille	`.din ( core_txd ),`
150			`.dout ( core_rxd ),`
151			`.scl_i ( scl_i ),`
152			`.scl_o ( scl_o ),`
153			`.scl_oen ( scl_oen ),`
154			`.sda_i ( sda_i ),`
155			`.sda_o ( sda_o ),`
156			`.sda_oen ( sda_oen )`
157	10	rherveille	`);`
158
159			`// generate go-signal`
160	27	rherveille	`assign go = (read \| write \| stop) & ~cmd_ack;`
161	10	rherveille
162			`// assign dout output to shift-register`
163			`assign dout = sr;`
164
165			`// generate shift register`
166	27	rherveille	`always @(posedge clk or negedge nReset)`
167			`if (!nReset)`
168			`sr <= #1 8'h0;`
169			`else if (rst)`
170			`sr <= #1 8'h0;`
171			`else if (ld)`
172			`sr <= #1 din;`
173			`else if (shift)`
174			`sr <= #1 {sr[6:0], core_rxd};`
175	10	rherveille
176			`// generate counter`
177	27	rherveille	`always @(posedge clk or negedge nReset)`
178			`if (!nReset)`
179			`dcnt <= #1 3'h0;`
180			`else if (rst)`
181			`dcnt <= #1 3'h0;`
182			`else if (ld)`
183			`dcnt <= #1 3'h7;`
184			`else if (shift)`
185			`dcnt <= #1 dcnt - 3'h1;`
186	10	rherveille
187	29	rherveille	`assign cnt_done = ~(\|dcnt);`
188	10	rherveille
189			`//`
190			`// state machine`
191			`//`
192			`reg [4:0] c_state; // synopsis enum_state`
193
194	27	rherveille	`always @(posedge clk or negedge nReset)`
195			`if (!nReset)`
196			`begin`
197			core_cmd <= #1 `I2C_CMD_NOP;
198			`core_txd <= #1 1'b0;`
199			`shift <= #1 1'b0;`
200			`ld <= #1 1'b0;`
201			`cmd_ack <= #1 1'b0;`
202			`c_state <= #1 ST_IDLE;`
203			`ack_out <= #1 1'b0;`
204			`end`
205	29	rherveille	`else if (rst \| i2c_al)`
206	27	rherveille	`begin`
207			core_cmd <= #1 `I2C_CMD_NOP;
208			`core_txd <= #1 1'b0;`
209			`shift <= #1 1'b0;`
210			`ld <= #1 1'b0;`
211			`cmd_ack <= #1 1'b0;`
212			`c_state <= #1 ST_IDLE;`
213			`ack_out <= #1 1'b0;`
214			`end`
215	10	rherveille	`else`
216	27	rherveille	`begin`
217			`// initially reset all signals`
218			`core_txd <= #1 sr[7];`
219			`shift <= #1 1'b0;`
220			`ld <= #1 1'b0;`
221			`cmd_ack <= #1 1'b0;`
222	10	rherveille
223	27	rherveille	`case (c_state) // synopsis full_case parallel_case`
224			`ST_IDLE:`
225			`if (go)`
226			`begin`
227			`if (start)`
228			`begin`
229			`c_state <= #1 ST_START;`
230			core_cmd <= #1 `I2C_CMD_START;
231			`end`
232			`else if (read)`
233			`begin`
234			`c_state <= #1 ST_READ;`
235			core_cmd <= #1 `I2C_CMD_READ;
236			`end`
237			`else if (write)`
238			`begin`
239			`c_state <= #1 ST_WRITE;`
240			core_cmd <= #1 `I2C_CMD_WRITE;
241			`end`
242			`else // stop`
243			`begin`
244			`c_state <= #1 ST_STOP;`
245			core_cmd <= #1 `I2C_CMD_STOP;
246	10	rherveille
247	27	rherveille	`// generate command acknowledge signal`
248			`cmd_ack <= #1 1'b1;`
249			`end`
250	10	rherveille
251	29	rherveille	`ld <= #1 1'b1;`
252	27	rherveille	`end`
253	10	rherveille
254	27	rherveille	`ST_START:`
255			`if (core_ack)`
256			`begin`
257			`if (read)`
258			`begin`
259			`c_state <= #1 ST_READ;`
260			core_cmd <= #1 `I2C_CMD_READ;
261			`end`
262			`else`
263			`begin`
264			`c_state <= #1 ST_WRITE;`
265			core_cmd <= #1 `I2C_CMD_WRITE;
266			`end`
267	10	rherveille
268	29	rherveille	`ld <= #1 1'b1;`
269	27	rherveille	`end`
270	13	rherveille
271	27	rherveille	`ST_WRITE:`
272			`if (core_ack)`
273			`if (cnt_done)`
274			`begin`
275			`c_state <= #1 ST_ACK;`
276			core_cmd <= #1 `I2C_CMD_READ;
277			`end`
278			`else`
279			`begin`
280			`c_state <= #1 ST_WRITE; // stay in same state`
281			core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
282			`shift <= #1 1'b1;`
283			`end`
284	13	rherveille
285	27	rherveille	`ST_READ:`
286			`if (core_ack)`
287			`begin`
288			`if (cnt_done)`
289			`begin`
290			`c_state <= #1 ST_ACK;`
291			core_cmd <= #1 `I2C_CMD_WRITE;
292			`end`
293			`else`
294			`begin`
295			`c_state <= #1 ST_READ; // stay in same state`
296			core_cmd <= #1 `I2C_CMD_READ; // read next bit
297			`end`
298	13	rherveille
299	27	rherveille	`shift <= #1 1'b1;`
300			`core_txd <= #1 ack_in;`
301			`end`
302	10	rherveille
303	27	rherveille	`ST_ACK:`
304			`if (core_ack)`
305			`begin`
306			`if (stop)`
307			`begin`
308			`c_state <= #1 ST_STOP;`
309			core_cmd <= #1 `I2C_CMD_STOP;
310			`end`
311			`else`
312			`begin`
313			`c_state <= #1 ST_IDLE;`
314			core_cmd <= #1 `I2C_CMD_NOP;
315	38	rherveille
316			`// generate command acknowledge signal`
317			`cmd_ack <= #1 1'b1;`
318	27	rherveille	`end`
319	10	rherveille
320	27	rherveille	`// assign ack_out output to bit_controller_rxd (contains last received bit)`
321			`ack_out <= #1 core_rxd;`
322	10	rherveille
323	38	rherveille	`// // generate command acknowledge signal`
324			`// cmd_ack <= #1 1'b1;`
325	10	rherveille
326	27	rherveille	`core_txd <= #1 1'b1;`
327			`end`
328			`else`
329			`core_txd <= #1 ack_in;`
330	10	rherveille
331	27	rherveille	`ST_STOP:`
332			`if (core_ack)`
333			`begin`
334			`c_state <= #1 ST_IDLE;`
335			core_cmd <= #1 `I2C_CMD_NOP;
336	38	rherveille
337			`// generate command acknowledge signal`
338			`cmd_ack <= #1 1'b1;`
339	27	rherveille	`end`
340	10	rherveille
341	27	rherveille	`endcase`
342			`end`
343	10	rherveille	`endmodule`

Browse

Tools

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_3/] [rtl/] [verilog/] [i2c_master_byte_ctrl.v] - Blame information for rev 69