URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Blame information for rev 68

Details | Compare with Previous | View Log


/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE rev.B2 compliant I2C Master controller Testbench  ////
////                                                             ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: tst_bench_top.v,v 1.8 2006-09-04 09:08:51 rherveille Exp $
//
//  $Date: 2006-09-04 09:08:51 $
//  $Revision: 1.8 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.7  2005/02/27 09:24:18  rherveille
//               Fixed scl, sda delay.
//
//               Revision 1.6  2004/02/28 15:40:42  rherveille
//               *** empty log message ***
//
//               Revision 1.4  2003/12/05 11:04:38  rherveille
//               Added slave address configurability
//
//               Revision 1.3  2002/10/30 18:11:06  rherveille
//               Added timing tests to i2c_model.
//               Updated testbench.
//
//               Revision 1.2  2002/03/17 10:26:38  rherveille
//               Fixed some race conditions in the i2c-slave model.
//               Added debug information.
//               Added headers.
//
 
`include "timescale.v"
 
module tst_bench_top();
 
        //
        // wires && regs
        //
        reg  clk;
        reg  rstn;
 
        wire [31:0] adr;
        wire [ 7:0] dat_i, dat_o, dat0_i, dat1_i;
        wire we;
        wire stb;
        wire cyc;
        wire ack;
        wire inta;
 
        reg [7:0] q, qq;
 
        wire scl, scl0_o, scl0_oen, scl1_o, scl1_oen;
        wire sda, sda0_o, sda0_oen, sda1_o, sda1_oen;
 
        parameter PRER_LO = 3'b000;
        parameter PRER_HI = 3'b001;
        parameter CTR     = 3'b010;
        parameter RXR     = 3'b011;
        parameter TXR     = 3'b011;
        parameter CR      = 3'b100;
        parameter SR      = 3'b100;
 
        parameter TXR_R   = 3'b101; // undocumented / reserved output
        parameter CR_R    = 3'b110; // undocumented / reserved output
 
        parameter RD      = 1'b1;
        parameter WR      = 1'b0;
        parameter SADR    = 7'b0010_000;
 
        //
        // Module body
        //
 
        // generate clock
        always #5 clk = ~clk;
 
        // hookup wishbone master model
        wb_master_model #(8, 32) u0 (
                .clk(clk),
                .rst(rstn),
                .adr(adr),
                .din(dat_i),
                .dout(dat_o),
                .cyc(cyc),
                .stb(stb),
                .we(we),
                .sel(),
                .ack(ack),
                .err(1'b0),
                .rty(1'b0)
        );
 
        wire stb0 = stb & ~adr[3];
        wire stb1 = stb &  adr[3];
 
        assign dat_i = ({{8'd8}{stb0}} & dat0_i) | ({{8'd8}{stb1}} & dat1_i);
 
        // hookup wishbone_i2c_master core
        i2c_master_top i2c_top (
 
                // wishbone interface
                .wb_clk_i(clk),
                .wb_rst_i(1'b0),
                .arst_i(rstn),
                .wb_adr_i(adr[2:0]),
                .wb_dat_i(dat_o),
                .wb_dat_o(dat0_i),
                .wb_we_i(we),
                .wb_stb_i(stb0),
                .wb_cyc_i(cyc),
                .wb_ack_o(ack),
                .wb_inta_o(inta),
 
                // i2c signals
                .scl_pad_i(scl),
                .scl_pad_o(scl0_o),
                .scl_padoen_o(scl0_oen),
                .sda_pad_i(sda),
                .sda_pad_o(sda0_o),
                .sda_padoen_o(sda0_oen)
        ),
        i2c_top2 (
 
                // wishbone interface
                .wb_clk_i(clk),
                .wb_rst_i(1'b0),
                .arst_i(rstn),
                .wb_adr_i(adr[2:0]),
                .wb_dat_i(dat_o),
                .wb_dat_o(dat1_i),
                .wb_we_i(we),
                .wb_stb_i(stb1),
                .wb_cyc_i(cyc),
                .wb_ack_o(ack),
                .wb_inta_o(inta),
 
                // i2c signals
                .scl_pad_i(scl),
                .scl_pad_o(scl1_o),
                .scl_padoen_o(scl1_oen),
                .sda_pad_i(sda),
                .sda_pad_o(sda1_o),
                .sda_padoen_o(sda1_oen)
        );
 
 
        // hookup i2c slave model
        i2c_slave_model #(SADR) i2c_slave (
                .scl(scl),
                .sda(sda)
        );
 
        // create i2c lines
        delay m0_scl (scl0_oen ? 1'bz : scl0_o, scl),
              m1_scl (scl1_oen ? 1'bz : scl1_o, scl),
              m0_sda (sda0_oen ? 1'bz : sda0_o, sda),
              m1_sda (sda1_oen ? 1'bz : sda1_o, sda);
 
        pullup p1(scl); // pullup scl line
        pullup p2(sda); // pullup sda line
 
        initial
          begin
              `ifdef WAVES
                 $shm_open("waves");
                 $shm_probe("AS",tst_bench_top,"AS");
                 $display("INFO: Signal dump enabled ...\n\n");
              `endif
 
//            force i2c_slave.debug = 1'b1; // enable i2c_slave debug information
              force i2c_slave.debug = 1'b0; // disable i2c_slave debug information
 
              $display("\nstatus: %t Testbench started\n\n", $time);
 
//            $dumpfile("bench.vcd");
//            $dumpvars(1, tst_bench_top);
//            $dumpvars(1, tst_bench_top.i2c_slave);
 
              // initially values
              clk = 0;
 
              // reset system
              rstn = 1'b1; // negate reset
              #2;
              rstn = 1'b0; // assert reset
              repeat(1) @(posedge clk);
              rstn = 1'b1; // negate reset
 
              $display("status: %t done reset", $time);
 
              @(posedge clk);
 
              //
              // program core
              //
 
              // program internal registers
              u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte
              u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte
              u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte
              $display("status: %t programmed registers", $time);
 
              u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte
              u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte
              $display("status: %t verified registers", $time);
 
              u0.wb_write(1, CTR,     8'h80); // enable core
              $display("status: %t core enabled", $time);
 
              //
              // access slave (write)
              //
 
              // drive slave address
              u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
              u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
              $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(0, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory address
              u0.wb_write(1, TXR,     8'h01); // present slave's memory address
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write slave memory address 01", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(0, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory contents
              u0.wb_write(1, TXR,     8'ha5); // present data
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write data a5", $time);
 
while (scl) #1;
force scl= 1'b0;
#100000;
release scl;
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory contents for next memory address (auto_inc)
              u0.wb_write(1, TXR,     8'h5a); // present data
              u0.wb_write(0, CR,      8'h50); // set command (stop, write)
              $display("status: %t write next data 5a, generate 'stop'", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              //
              // delay
              //
//            #100000; // wait for 100us.
//            $display("status: %t wait 100us", $time);
 
              //
              // access slave (read)
              //
 
              // drive slave address
              u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit
              u0.wb_write(0, CR,     8'h90 ); // set command (start, write)
              $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory address
              u0.wb_write(1, TXR,     8'h01); // present slave's memory address
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write slave address 01", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // drive slave address
              u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit
              u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
              $display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} );
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
              $display("status: %t read + ack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              if(qq !== 8'ha5)
                $display("\nERROR: Expected a5, received %x at time %t", qq, $time);
              else
                $display("status: %t received %x", $time, qq);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
              $display("status: %t read + ack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              if(qq !== 8'h5a)
                $display("\nERROR: Expected 5a, received %x at time %t", qq, $time);
              else
                $display("status: %t received %x", $time, qq);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
              $display("status: %t read + ack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              $display("status: %t received %x from 3rd read address", $time, qq);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h28); // set command (read, nack_read)
              $display("status: %t read + nack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              $display("status: %t received %x from 4th read address", $time, qq);
 
              //
              // check invalid slave memory address
              //
 
              // drive slave address
              u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
              u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
              $display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} );
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory address
              u0.wb_write(1, TXR,     8'h10); // present slave's memory address
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write slave memory address 10", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // slave should have send NACK
              $display("status: %t Check for nack", $time);
              if(!q[7])
                $display("\nERROR: Expected NACK, received ACK\n");
 
              // read data from slave
              u0.wb_write(1, CR,      8'h40); // set command (stop)
              $display("status: %t generate 'stop'", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
              u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              #250000; // wait 250us
              $display("\n\nstatus: %t Testbench done", $time);
              $finish;
          end
 
endmodule
 
module delay (in, out);
  input  in;
  output out;
 
  assign out = in;
 
  specify
    (in => out) = (600,600);
  endspecify
endmodule
 
 

Line No.	Rev	Author	Line
1	19	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE rev.B2 compliant I2C Master controller Testbench ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/i2c/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	10	rherveille	`//`
40	58	rherveille	`// $Id: tst_bench_top.v,v 1.8 2006-09-04 09:08:51 rherveille Exp $`
41	10	rherveille	`//`
42	58	rherveille	`// $Date: 2006-09-04 09:08:51 $`
43			`// $Revision: 1.8 $`
44	19	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	58	rherveille	`// Revision 1.7 2005/02/27 09:24:18 rherveille`
51			`// Fixed scl, sda delay.`
52			`//`
53	54	rherveille	`// Revision 1.6 2004/02/28 15:40:42 rherveille`
54			`// * empty log message *`
55			`//`
56	50	rherveille	`// Revision 1.4 2003/12/05 11:04:38 rherveille`
57			`// Added slave address configurability`
58	45	rherveille	`//`
59	50	rherveille	`// Revision 1.3 2002/10/30 18:11:06 rherveille`
60			`// Added timing tests to i2c_model.`
61			`// Updated testbench.`
62			`//`
63			`// Revision 1.2 2002/03/17 10:26:38 rherveille`
64			`// Fixed some race conditions in the i2c-slave model.`
65			`// Added debug information.`
66			`// Added headers.`
67			`//`
68	10	rherveille
69			`include "timescale.v"
70
71			`module tst_bench_top();`
72
73			`//`
74			`// wires && regs`
75			`//`
76			`reg clk;`
77			`reg rstn;`
78
79			`wire [31:0] adr;`
80	54	rherveille	`wire [ 7:0] dat_i, dat_o, dat0_i, dat1_i;`
81	10	rherveille	`wire we;`
82			`wire stb;`
83			`wire cyc;`
84			`wire ack;`
85			`wire inta;`
86
87	50	rherveille	`reg [7:0] q, qq;`
88	10	rherveille
89	54	rherveille	`wire scl, scl0_o, scl0_oen, scl1_o, scl1_oen;`
90			`wire sda, sda0_o, sda0_oen, sda1_o, sda1_oen;`
91	10	rherveille
92	50	rherveille	`parameter PRER_LO = 3'b000;`
93			`parameter PRER_HI = 3'b001;`
94			`parameter CTR = 3'b010;`
95			`parameter RXR = 3'b011;`
96			`parameter TXR = 3'b011;`
97			`parameter CR = 3'b100;`
98			`parameter SR = 3'b100;`
99	10	rherveille
100	50	rherveille	`parameter TXR_R = 3'b101; // undocumented / reserved output`
101			`parameter CR_R = 3'b110; // undocumented / reserved output`
102
103			`parameter RD = 1'b1;`
104			`parameter WR = 1'b0;`
105			`parameter SADR = 7'b0010_000;`
106
107	10	rherveille	`//`
108			`// Module body`
109			`//`
110
111			`// generate clock`
112			`always #5 clk = ~clk;`
113
114			`// hookup wishbone master model`
115	19	rherveille	`wb_master_model #(8, 32) u0 (`
116	50	rherveille	`.clk(clk),`
117			`.rst(rstn),`
118			`.adr(adr),`
119			`.din(dat_i),`
120	10	rherveille	`.dout(dat_o),`
121	50	rherveille	`.cyc(cyc),`
122			`.stb(stb),`
123			`.we(we),`
124			`.sel(),`
125			`.ack(ack),`
126			`.err(1'b0),`
127			`.rty(1'b0)`
128	10	rherveille	`);`
129
130	54	rherveille	`wire stb0 = stb & ~adr[3];`
131			`wire stb1 = stb & adr[3];`
132
133			`assign dat_i = ({{8'd8}{stb0}} & dat0_i) \| ({{8'd8}{stb1}} & dat1_i);`
134
135	50	rherveille	`// hookup wishbone_i2c_master core`
136			`i2c_master_top i2c_top (`
137
138	10	rherveille	`// wishbone interface`
139	50	rherveille	`.wb_clk_i(clk),`
140			`.wb_rst_i(1'b0),`
141			`.arst_i(rstn),`
142			`.wb_adr_i(adr[2:0]),`
143			`.wb_dat_i(dat_o),`
144	54	rherveille	`.wb_dat_o(dat0_i),`
145	50	rherveille	`.wb_we_i(we),`
146	54	rherveille	`.wb_stb_i(stb0),`
147	50	rherveille	`.wb_cyc_i(cyc),`
148			`.wb_ack_o(ack),`
149			`.wb_inta_o(inta),`
150	10	rherveille
151	50	rherveille	`// i2c signals`
152			`.scl_pad_i(scl),`
153	54	rherveille	`.scl_pad_o(scl0_o),`
154			`.scl_padoen_o(scl0_oen),`
155	50	rherveille	`.sda_pad_i(sda),`
156	54	rherveille	`.sda_pad_o(sda0_o),`
157			`.sda_padoen_o(sda0_oen)`
158			`),`
159			`i2c_top2 (`
160
161			`// wishbone interface`
162			`.wb_clk_i(clk),`
163			`.wb_rst_i(1'b0),`
164			`.arst_i(rstn),`
165			`.wb_adr_i(adr[2:0]),`
166			`.wb_dat_i(dat_o),`
167			`.wb_dat_o(dat1_i),`
168			`.wb_we_i(we),`
169			`.wb_stb_i(stb1),`
170			`.wb_cyc_i(cyc),`
171			`.wb_ack_o(ack),`
172			`.wb_inta_o(inta),`
173
174			`// i2c signals`
175			`.scl_pad_i(scl),`
176			`.scl_pad_o(scl1_o),`
177			`.scl_padoen_o(scl1_oen),`
178			`.sda_pad_i(sda),`
179			`.sda_pad_o(sda1_o),`
180			`.sda_padoen_o(sda1_oen)`
181	10	rherveille	`);`
182
183	54	rherveille
184	50	rherveille	`// hookup i2c slave model`
185			`i2c_slave_model #(SADR) i2c_slave (`
186			`.scl(scl),`
187			`.sda(sda)`
188	10	rherveille	`);`
189
190	54	rherveille	`// create i2c lines`
191			`delay m0_scl (scl0_oen ? 1'bz : scl0_o, scl),`
192			`m1_scl (scl1_oen ? 1'bz : scl1_o, scl),`
193			`m0_sda (sda0_oen ? 1'bz : sda0_o, sda),`
194			`m1_sda (sda1_oen ? 1'bz : sda1_o, sda);`
195	50	rherveille
196			`pullup p1(scl); // pullup scl line`
197			`pullup p2(sda); // pullup sda line`
198
199	10	rherveille	`initial`
200	25	rherveille	`begin`
201			`ifdef WAVES
202			`$shm_open("waves");`
203			`$shm_probe("AS",tst_bench_top,"AS");`
204			`$display("INFO: Signal dump enabled ...\n\n");`
205			`endif
206	19	rherveille
207	50	rherveille	`// force i2c_slave.debug = 1'b1; // enable i2c_slave debug information`
208			`force i2c_slave.debug = 1'b0; // disable i2c_slave debug information`
209	19	rherveille
210	25	rherveille	`$display("\nstatus: %t Testbench started\n\n", $time);`
211	19	rherveille
212	50	rherveille	`// $dumpfile("bench.vcd");`
213			`// $dumpvars(1, tst_bench_top);`
214			`// $dumpvars(1, tst_bench_top.i2c_slave);`
215	10	rherveille
216	25	rherveille	`// initially values`
217			`clk = 0;`
218	19	rherveille
219	25	rherveille	`// reset system`
220			`rstn = 1'b1; // negate reset`
221			`#2;`
222			`rstn = 1'b0; // assert reset`
223	45	rherveille	`repeat(1) @(posedge clk);`
224	25	rherveille	`rstn = 1'b1; // negate reset`
225	10	rherveille
226	25	rherveille	`$display("status: %t done reset", $time);`
227	10	rherveille
228	25	rherveille	`@(posedge clk);`
229	10	rherveille
230	25	rherveille	`//`
231			`// program core`
232			`//`
233	19	rherveille
234	50	rherveille	`// program internal registers`
235			`u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte`
236			`u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte`
237			`u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte`
238			`$display("status: %t programmed registers", $time);`
239	19	rherveille
240	50	rherveille	`u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte`
241			`u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte`
242			`$display("status: %t verified registers", $time);`
243	19	rherveille
244	50	rherveille	`u0.wb_write(1, CTR, 8'h80); // enable core`
245			`$display("status: %t core enabled", $time);`
246	10	rherveille
247	50	rherveille	`//`
248			`// access slave (write)`
249			`//`
250	19	rherveille
251	50	rherveille	`// drive slave address`
252			`u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit`
253			`u0.wb_write(0, CR, 8'h90 ); // set command (start, write)`
254			`$display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );`
255	10	rherveille
256	25	rherveille	`// check tip bit`
257	50	rherveille	`u0.wb_read(1, SR, q);`
258			`while(q[1])`
259			`u0.wb_read(0, SR, q); // poll it until it is zero`
260			`$display("status: %t tip==0", $time);`
261	10	rherveille
262	50	rherveille	`// send memory address`
263			`u0.wb_write(1, TXR, 8'h01); // present slave's memory address`
264			`u0.wb_write(0, CR, 8'h10); // set command (write)`
265			`$display("status: %t write slave memory address 01", $time);`
266
267			`// check tip bit`
268			`u0.wb_read(1, SR, q);`
269			`while(q[1])`
270			`u0.wb_read(0, SR, q); // poll it until it is zero`
271			`$display("status: %t tip==0", $time);`
272
273			`// send memory contents`
274			`u0.wb_write(1, TXR, 8'ha5); // present data`
275			`u0.wb_write(0, CR, 8'h10); // set command (write)`
276			`$display("status: %t write data a5", $time);`
277
278	58	rherveille	`while (scl) #1;`
279			`force scl= 1'b0;`
280			`#100000;`
281			`release scl;`
282
283	50	rherveille	`// check tip bit`
284			`u0.wb_read(1, SR, q);`
285			`while(q[1])`
286			`u0.wb_read(1, SR, q); // poll it until it is zero`
287			`$display("status: %t tip==0", $time);`
288
289			`// send memory contents for next memory address (auto_inc)`
290			`u0.wb_write(1, TXR, 8'h5a); // present data`
291			`u0.wb_write(0, CR, 8'h50); // set command (stop, write)`
292			`$display("status: %t write next data 5a, generate 'stop'", $time);`
293
294			`// check tip bit`
295			`u0.wb_read(1, SR, q);`
296			`while(q[1])`
297			`u0.wb_read(1, SR, q); // poll it until it is zero`
298			`$display("status: %t tip==0", $time);`
299
300			`//`
301			`// delay`
302			`//`
303			`// #100000; // wait for 100us.`
304			`// $display("status: %t wait 100us", $time);`
305
306			`//`
307			`// access slave (read)`
308			`//`
309
310			`// drive slave address`
311			`u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit`
312			`u0.wb_write(0, CR, 8'h90 ); // set command (start, write)`
313			`$display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );`
314
315			`// check tip bit`
316			`u0.wb_read(1, SR, q);`
317			`while(q[1])`
318			`u0.wb_read(1, SR, q); // poll it until it is zero`
319			`$display("status: %t tip==0", $time);`
320
321			`// send memory address`
322			`u0.wb_write(1, TXR, 8'h01); // present slave's memory address`
323			`u0.wb_write(0, CR, 8'h10); // set command (write)`
324			`$display("status: %t write slave address 01", $time);`
325
326			`// check tip bit`
327			`u0.wb_read(1, SR, q);`
328			`while(q[1])`
329			`u0.wb_read(1, SR, q); // poll it until it is zero`
330			`$display("status: %t tip==0", $time);`
331
332			`// drive slave address`
333			`u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit`
334			`u0.wb_write(0, CR, 8'h90 ); // set command (start, write)`
335			`$display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} );`
336
337			`// check tip bit`
338			`u0.wb_read(1, SR, q);`
339			`while(q[1])`
340			`u0.wb_read(1, SR, q); // poll it until it is zero`
341			`$display("status: %t tip==0", $time);`
342
343			`// read data from slave`
344			`u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)`
345			`$display("status: %t read + ack", $time);`
346
347			`// check tip bit`
348			`u0.wb_read(1, SR, q);`
349			`while(q[1])`
350			`u0.wb_read(1, SR, q); // poll it until it is zero`
351			`$display("status: %t tip==0", $time);`
352
353			`// check data just received`
354			`u0.wb_read(1, RXR, qq);`
355			`if(qq !== 8'ha5)`
356			`$display("\nERROR: Expected a5, received %x at time %t", qq, $time);`
357			`else`
358			`$display("status: %t received %x", $time, qq);`
359
360			`// read data from slave`
361			`u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)`
362			`$display("status: %t read + ack", $time);`
363
364			`// check tip bit`
365			`u0.wb_read(1, SR, q);`
366			`while(q[1])`
367			`u0.wb_read(1, SR, q); // poll it until it is zero`
368			`$display("status: %t tip==0", $time);`
369
370			`// check data just received`
371			`u0.wb_read(1, RXR, qq);`
372			`if(qq !== 8'h5a)`
373			`$display("\nERROR: Expected 5a, received %x at time %t", qq, $time);`
374			`else`
375			`$display("status: %t received %x", $time, qq);`
376
377			`// read data from slave`
378			`u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)`
379			`$display("status: %t read + ack", $time);`
380
381			`// check tip bit`
382			`u0.wb_read(1, SR, q);`
383			`while(q[1])`
384			`u0.wb_read(1, SR, q); // poll it until it is zero`
385			`$display("status: %t tip==0", $time);`
386
387			`// check data just received`
388			`u0.wb_read(1, RXR, qq);`
389			`$display("status: %t received %x from 3rd read address", $time, qq);`
390
391			`// read data from slave`
392			`u0.wb_write(1, CR, 8'h28); // set command (read, nack_read)`
393			`$display("status: %t read + nack", $time);`
394
395			`// check tip bit`
396			`u0.wb_read(1, SR, q);`
397			`while(q[1])`
398			`u0.wb_read(1, SR, q); // poll it until it is zero`
399			`$display("status: %t tip==0", $time);`
400
401			`// check data just received`
402			`u0.wb_read(1, RXR, qq);`
403			`$display("status: %t received %x from 4th read address", $time, qq);`
404
405			`//`
406			`// check invalid slave memory address`
407			`//`
408
409			`// drive slave address`
410			`u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit`
411			`u0.wb_write(0, CR, 8'h90 ); // set command (start, write)`
412			`$display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} );`
413
414			`// check tip bit`
415			`u0.wb_read(1, SR, q);`
416			`while(q[1])`
417			`u0.wb_read(1, SR, q); // poll it until it is zero`
418			`$display("status: %t tip==0", $time);`
419
420			`// send memory address`
421			`u0.wb_write(1, TXR, 8'h10); // present slave's memory address`
422			`u0.wb_write(0, CR, 8'h10); // set command (write)`
423			`$display("status: %t write slave memory address 10", $time);`
424
425			`// check tip bit`
426			`u0.wb_read(1, SR, q);`
427			`while(q[1])`
428			`u0.wb_read(1, SR, q); // poll it until it is zero`
429			`$display("status: %t tip==0", $time);`
430
431			`// slave should have send NACK`
432			`$display("status: %t Check for nack", $time);`
433			`if(!q[7])`
434			`$display("\nERROR: Expected NACK, received ACK\n");`
435
436			`// read data from slave`
437			`u0.wb_write(1, CR, 8'h40); // set command (stop)`
438			`$display("status: %t generate 'stop'", $time);`
439
440			`// check tip bit`
441			`u0.wb_read(1, SR, q);`
442			`while(q[1])`
443			`u0.wb_read(1, SR, q); // poll it until it is zero`
444			`$display("status: %t tip==0", $time);`
445
446	45	rherveille	`#250000; // wait 250us`
447	25	rherveille	`$display("\n\nstatus: %t Testbench done", $time);`
448			`$finish;`
449			`end`
450	19	rherveille
451	10	rherveille	`endmodule`
452
453	54	rherveille	`module delay (in, out);`
454			`input in;`
455			`output out;`
456	50	rherveille
457	54	rherveille	`assign out = in;`
458	50	rherveille
459	54	rherveille	`specify`
460			`(in => out) = (600,600);`
461			`endspecify`
462			`endmodule`
463
464

Browse

Tools

Subversion Repositories i2c

[/] [i2c/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Blame information for rev 68