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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE rev.B2 compliant I2C Master bit-controller        ////
////                                                             ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: i2c_master_bit_ctrl.v,v 1.13 2009-01-19 20:29:26 rherveille Exp $
//
//  $Date: 2009-01-19 20:29:26 $
//  $Revision: 1.13 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.12  2006/09/04 09:08:13  rherveille
//               fixed short scl high pulse after clock stretch
//               fixed slave model not returning correct '(n)ack' signal
//
//               Revision 1.11  2004/05/07 11:02:26  rherveille
//               Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
//
//               Revision 1.10  2003/08/09 07:01:33  rherveille
//               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
//               Fixed a potential bug in the byte controller's host-acknowledge generation.
//
//               Revision 1.9  2003/03/10 14:26:37  rherveille
//               Fixed cmd_ack generation item (no bug).
//
//               Revision 1.8  2003/02/05 00:06:10  rherveille
//               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
//
//               Revision 1.7  2002/12/26 16:05:12  rherveille
//               Small code simplifications
//
//               Revision 1.6  2002/12/26 15:02:32  rherveille
//               Core is now a Multimaster I2C controller
//
//               Revision 1.5  2002/11/30 22:24:40  rherveille
//               Cleaned up code
//
//               Revision 1.4  2002/10/30 18:10:07  rherveille
//               Fixed some reported minor start/stop generation timing issuess.
//
//               Revision 1.3  2002/06/15 07:37:03  rherveille
//               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
//
//               Revision 1.2  2001/11/05 11:59:25  rherveille
//               Fixed wb_ack_o generation bug.
//               Fixed bug in the byte_controller statemachine.
//               Added headers.
//
 
//
/////////////////////////////////////
// Bit controller section
/////////////////////////////////////
//
// Translate simple commands into SCL/SDA transitions
// Each command has 5 states, A/B/C/D/idle
//
// start:       SCL     ~~~~~~~~~~\____
//      SDA     ~~~~~~~~\______
//               x | A | B | C | D | i
//
// repstart     SCL     ____/~~~~\___
//      SDA     __/~~~\______
//               x | A | B | C | D | i
//
// stop SCL     ____/~~~~~~~~
//      SDA     ==\____/~~~~~
//               x | A | B | C | D | i
//
//- write       SCL     ____/~~~~\____
//      SDA     ==X=========X=
//               x | A | B | C | D | i
//
//- read        SCL     ____/~~~~\____
//      SDA     XXXX=====XXXX
//               x | A | B | C | D | i
//
 
// Timing:     Normal mode      Fast mode
///////////////////////////////////////////////////////////////////////
// Fscl        100KHz           400KHz
// Th_scl      4.0us            0.6us   High period of SCL
// Tl_scl      4.7us            1.3us   Low period of SCL
// Tsu:sta     4.7us            0.6us   setup time for a repeated start condition
// Tsu:sto     4.0us            0.6us   setup time for a stop conditon
// Tbuf        4.7us            1.3us   Bus free time between a stop and start condition
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`include "i2c_master_defines.v"
 
module i2c_master_bit_ctrl(
        clk, rst, nReset,
        clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout,
        scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen
        );
 
        //
        // inputs & outputs
        //
        input clk;
        input rst;
        input nReset;
        input ena;            // core enable signal
 
        input [15:0] clk_cnt; // clock prescale value
 
        input  [3:0] cmd;
        output       cmd_ack; // command complete acknowledge
        reg cmd_ack;
        output       busy;    // i2c bus busy
        reg busy;
        output       al;      // i2c bus arbitration lost
        reg al;
 
        input  din;
        output dout;
        reg dout;
 
        // I2C lines
        input  scl_i;         // i2c clock line input
        output scl_o;         // i2c clock line output
        output scl_oen;       // i2c clock line output enable (active low)
        reg scl_oen;
        input  sda_i;         // i2c data line input
        output sda_o;         // i2c data line output
        output sda_oen;       // i2c data line output enable (active low)
        reg sda_oen;
 
 
        //
        // variable declarations
        //
 
        reg sSCL, sSDA;             // synchronized SCL and SDA inputs
        reg dscl_oen;               // delayed scl_oen
        reg sda_chk;                // check SDA output (Multi-master arbitration)
        reg clk_en;                 // clock generation signals
        wire slave_wait;
//      reg [15:0] cnt = clk_cnt;   // clock divider counter (simulation)
        reg [15:0] cnt;             // clock divider counter (synthesis)
 
        // state machine variable
        reg [17:0] c_state; // synopsys enum_state
 
        //
        // module body
        //
 
        // whenever the slave is not ready it can delay the cycle by pulling SCL low
        // delay scl_oen
        always @(posedge clk)
          dscl_oen <= #1 scl_oen;
 
        assign slave_wait = dscl_oen && !sSCL;
 
 
        // generate clk enable signal
        always @(posedge clk or negedge nReset)
          if(~nReset)
            begin
                cnt    <= #1 16'h0;
                clk_en <= #1 1'b1;
            end
          else if (rst)
            begin
                cnt    <= #1 16'h0;
                clk_en <= #1 1'b1;
            end
          else if ( ~|cnt || !ena)
            begin
                cnt    <= #1 clk_cnt;
                clk_en <= #1 1'b1;
            end
          else if (slave_wait)
            begin
                cnt    <= #1 cnt;
                clk_en <= #1 1'b0;
            end
          else
            begin
                cnt    <= #1 cnt - 16'h1;
                clk_en <= #1 1'b0;
            end
 
 
        // generate bus status controller
        reg dSCL, dSDA;
        reg sta_condition;
        reg sto_condition;
 
        // synchronize SCL and SDA inputs
        // reduce metastability risc
        always @(posedge clk or negedge nReset)
          if (~nReset)
            begin
                sSCL <= #1 1'b1;
                sSDA <= #1 1'b1;
 
                dSCL <= #1 1'b1;
                dSDA <= #1 1'b1;
            end
          else if (rst)
            begin
                sSCL <= #1 1'b1;
                sSDA <= #1 1'b1;
 
                dSCL <= #1 1'b1;
                dSDA <= #1 1'b1;
            end
          else
            begin
                sSCL <= #1 scl_i;
                sSDA <= #1 sda_i;
 
                dSCL <= #1 sSCL;
                dSDA <= #1 sSDA;
            end
 
        // detect start condition => detect falling edge on SDA while SCL is high
        // detect stop condition => detect rising edge on SDA while SCL is high
        always @(posedge clk or negedge nReset)
          if (~nReset)
            begin
                sta_condition <= #1 1'b0;
                sto_condition <= #1 1'b0;
            end
          else if (rst)
            begin
                sta_condition <= #1 1'b0;
                sto_condition <= #1 1'b0;
            end
          else
            begin
                sta_condition <= #1 ~sSDA &  dSDA & sSCL;
                sto_condition <= #1  sSDA & ~dSDA & sSCL;
            end
 
        // generate i2c bus busy signal
        always @(posedge clk or negedge nReset)
          if(!nReset)
            busy <= #1 1'b0;
          else if (rst)
            busy <= #1 1'b0;
          else
            busy <= #1 (sta_condition | busy) & ~sto_condition;
 
        // generate arbitration lost signal
        // aribitration lost when:
        // 1) master drives SDA high, but the i2c bus is low
        // 2) stop detected while not requested
        reg cmd_stop;
        always @(posedge clk or negedge nReset)
          if (~nReset)
            cmd_stop <= #1 1'b0;
          else if (rst)
            cmd_stop <= #1 1'b0;
          else if (clk_en)
            cmd_stop <= #1 cmd == `I2C_CMD_STOP;
 
        always @(posedge clk or negedge nReset)
          if (~nReset)
            al <= #1 1'b0;
          else if (rst)
            al <= #1 1'b0;
          else
            al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
 
 
        // generate dout signal (store SDA on rising edge of SCL)
        always @(posedge clk)
          if(sSCL & ~dSCL)
            dout <= #1 sSDA;
 
        // generate statemachine
 
        // nxt_state decoder
        parameter [17:0] idle    = 18'b0_0000_0000_0000_0000;
        parameter [17:0] start_a = 18'b0_0000_0000_0000_0001;
        parameter [17:0] start_b = 18'b0_0000_0000_0000_0010;
        parameter [17:0] start_c = 18'b0_0000_0000_0000_0100;
        parameter [17:0] start_d = 18'b0_0000_0000_0000_1000;
        parameter [17:0] start_e = 18'b0_0000_0000_0001_0000;
        parameter [17:0] stop_a  = 18'b0_0000_0000_0010_0000;
        parameter [17:0] stop_b  = 18'b0_0000_0000_0100_0000;
        parameter [17:0] stop_c  = 18'b0_0000_0000_1000_0000;
        parameter [17:0] stop_d  = 18'b0_0000_0001_0000_0000;
        parameter [17:0] rd_a    = 18'b0_0000_0010_0000_0000;
        parameter [17:0] rd_b    = 18'b0_0000_0100_0000_0000;
        parameter [17:0] rd_c    = 18'b0_0000_1000_0000_0000;
        parameter [17:0] rd_d    = 18'b0_0001_0000_0000_0000;
        parameter [17:0] wr_a    = 18'b0_0010_0000_0000_0000;
        parameter [17:0] wr_b    = 18'b0_0100_0000_0000_0000;
        parameter [17:0] wr_c    = 18'b0_1000_0000_0000_0000;
        parameter [17:0] wr_d    = 18'b1_0000_0000_0000_0000;
 
        always @(posedge clk or negedge nReset)
          if (!nReset)
            begin
                c_state <= #1 idle;
                cmd_ack <= #1 1'b0;
                scl_oen <= #1 1'b1;
                sda_oen <= #1 1'b1;
                sda_chk <= #1 1'b0;
            end
          else if (rst | al)
            begin
                c_state <= #1 idle;
                cmd_ack <= #1 1'b0;
                scl_oen <= #1 1'b1;
                sda_oen <= #1 1'b1;
                sda_chk <= #1 1'b0;
            end
          else
            begin
                cmd_ack   <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
 
                if (clk_en)
                  case (c_state) // synopsys full_case parallel_case
                    // idle state
                    idle:
                    begin
                        case (cmd) // synopsys full_case parallel_case
                          `I2C_CMD_START:
                             c_state <= #1 start_a;
 
                          `I2C_CMD_STOP:
                             c_state <= #1 stop_a;
 
                          `I2C_CMD_WRITE:
                             c_state <= #1 wr_a;
 
                          `I2C_CMD_READ:
                             c_state <= #1 rd_a;
 
                          default:
                            c_state <= #1 idle;
                        endcase
 
                        scl_oen <= #1 scl_oen; // keep SCL in same state
                        sda_oen <= #1 sda_oen; // keep SDA in same state
                        sda_chk <= #1 1'b0;    // don't check SDA output
                    end
 
                    // start
                    start_a:
                    begin
                        c_state <= #1 start_b;
                        scl_oen <= #1 scl_oen; // keep SCL in same state
                        sda_oen <= #1 1'b1;    // set SDA high
                        sda_chk <= #1 1'b0;    // don't check SDA output
                    end
 
                    start_b:
                    begin
                        c_state <= #1 start_c;
                        scl_oen <= #1 1'b1; // set SCL high
                        sda_oen <= #1 1'b1; // keep SDA high
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    start_c:
                    begin
                        c_state <= #1 start_d;
                        scl_oen <= #1 1'b1; // keep SCL high
                        sda_oen <= #1 1'b0; // set SDA low
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    start_d:
                    begin
                        c_state <= #1 start_e;
                        scl_oen <= #1 1'b1; // keep SCL high
                        sda_oen <= #1 1'b0; // keep SDA low
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    start_e:
                    begin
                        c_state <= #1 idle;
                        cmd_ack <= #1 1'b1;
                        scl_oen <= #1 1'b0; // set SCL low
                        sda_oen <= #1 1'b0; // keep SDA low
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    // stop
                    stop_a:
                    begin
                        c_state <= #1 stop_b;
                        scl_oen <= #1 1'b0; // keep SCL low
                        sda_oen <= #1 1'b0; // set SDA low
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    stop_b:
                    begin
                        c_state <= #1 stop_c;
                        scl_oen <= #1 1'b1; // set SCL high
                        sda_oen <= #1 1'b0; // keep SDA low
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    stop_c:
                    begin
                        c_state <= #1 stop_d;
                        scl_oen <= #1 1'b1; // keep SCL high
                        sda_oen <= #1 1'b0; // keep SDA low
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    stop_d:
                    begin
                        c_state <= #1 idle;
                        cmd_ack <= #1 1'b1;
                        scl_oen <= #1 1'b1; // keep SCL high
                        sda_oen <= #1 1'b1; // set SDA high
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    // read
                    rd_a:
                    begin
                        c_state <= #1 rd_b;
                        scl_oen <= #1 1'b0; // keep SCL low
                        sda_oen <= #1 1'b1; // tri-state SDA
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    rd_b:
                    begin
                        c_state <= #1 rd_c;
                        scl_oen <= #1 1'b1; // set SCL high
                        sda_oen <= #1 1'b1; // keep SDA tri-stated
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    rd_c:
                    begin
                        c_state <= #1 rd_d;
                        scl_oen <= #1 1'b1; // keep SCL high
                        sda_oen <= #1 1'b1; // keep SDA tri-stated
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    rd_d:
                    begin
                        c_state <= #1 idle;
                        cmd_ack <= #1 1'b1;
                        scl_oen <= #1 1'b0; // set SCL low
                        sda_oen <= #1 1'b1; // keep SDA tri-stated
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    // write
                    wr_a:
                    begin
                        c_state <= #1 wr_b;
                        scl_oen <= #1 1'b0; // keep SCL low
                        sda_oen <= #1 din;  // set SDA
                        sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
                    end
 
                    wr_b:
                    begin
                        c_state <= #1 wr_c;
                        scl_oen <= #1 1'b1; // set SCL high
                        sda_oen <= #1 din;  // keep SDA
                        sda_chk <= #1 1'b1; // check SDA output
                    end
 
                    wr_c:
                    begin
                        c_state <= #1 wr_d;
                        scl_oen <= #1 1'b1; // keep SCL high
                        sda_oen <= #1 din;
                        sda_chk <= #1 1'b1; // check SDA output
                    end
 
                    wr_d:
                    begin
                        c_state <= #1 idle;
                        cmd_ack <= #1 1'b1;
                        scl_oen <= #1 1'b0; // set SCL low
                        sda_oen <= #1 din;
                        sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
                    end
 
                  endcase
            end
 
 
        // assign scl and sda output (always gnd)
        assign scl_o = 1'b0;
        assign sda_o = 1'b0;
 
endmodule

Line No.	Rev	Author	Line
1	14	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE rev.B2 compliant I2C Master bit-controller ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/i2c/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	10	rherveille	`//`
40	62	rherveille	`// $Id: i2c_master_bit_ctrl.v,v 1.13 2009-01-19 20:29:26 rherveille Exp $`
41	10	rherveille	`//`
42	62	rherveille	`// $Date: 2009-01-19 20:29:26 $`
43			`// $Revision: 1.13 $`
44	14	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47	10	rherveille	`//`
48	14	rherveille	`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	62	rherveille	`// Revision 1.12 2006/09/04 09:08:13 rherveille`
51			`// fixed short scl high pulse after clock stretch`
52			`// fixed slave model not returning correct '(n)ack' signal`
53			`//`
54	57	rherveille	`// Revision 1.11 2004/05/07 11:02:26 rherveille`
55			`// Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.`
56			`//`
57	52	rherveille	`// Revision 1.10 2003/08/09 07:01:33 rherveille`
58			`// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.`
59			`// Fixed a potential bug in the byte controller's host-acknowledge generation.`
60			`//`
61	38	rherveille	`// Revision 1.9 2003/03/10 14:26:37 rherveille`
62			`// Fixed cmd_ack generation item (no bug).`
63			`//`
64	36	rherveille	`// Revision 1.8 2003/02/05 00:06:10 rherveille`
65			`// Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.`
66			`//`
67	35	rherveille	`// Revision 1.7 2002/12/26 16:05:12 rherveille`
68			`// Small code simplifications`
69			`//`
70	30	rherveille	`// Revision 1.6 2002/12/26 15:02:32 rherveille`
71			`// Core is now a Multimaster I2C controller`
72			`//`
73	29	rherveille	`// Revision 1.5 2002/11/30 22:24:40 rherveille`
74			`// Cleaned up code`
75			`//`
76	27	rherveille	`// Revision 1.4 2002/10/30 18:10:07 rherveille`
77			`// Fixed some reported minor start/stop generation timing issuess.`
78			`//`
79	24	rherveille	`// Revision 1.3 2002/06/15 07:37:03 rherveille`
80			`// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.`
81			`//`
82	22	rherveille	`// Revision 1.2 2001/11/05 11:59:25 rherveille`
83			`// Fixed wb_ack_o generation bug.`
84			`// Fixed bug in the byte_controller statemachine.`
85			`// Added headers.`
86			`//`
87	10	rherveille
88			`//`
89			`/////////////////////////////////////`
90			`// Bit controller section`
91			`/////////////////////////////////////`
92			`//`
93			`// Translate simple commands into SCL/SDA transitions`
94			`// Each command has 5 states, A/B/C/D/idle`
95			`//`
96			`// start: SCL ~~~~~~~~~~\____`
97			`// SDA ~~~~~~~~\______`
98			`// x \| A \| B \| C \| D \| i`
99			`//`
100			`// repstart SCL ____/~~~~\___`
101			`// SDA __/~~~\______`
102			`// x \| A \| B \| C \| D \| i`
103			`//`
104			`// stop SCL ____/~~~~~~~~`
105			`// SDA ==\____/~~~~~`
106			`// x \| A \| B \| C \| D \| i`
107			`//`
108			`//- write SCL ____/~~~~\____`
109			`// SDA ==X=========X=`
110			`// x \| A \| B \| C \| D \| i`
111			`//`
112			`//- read SCL ____/~~~~\____`
113			`// SDA XXXX=====XXXX`
114			`// x \| A \| B \| C \| D \| i`
115			`//`
116
117	24	rherveille	`// Timing: Normal mode Fast mode`
118	10	rherveille	`///////////////////////////////////////////////////////////////////////`
119	24	rherveille	`// Fscl 100KHz 400KHz`
120			`// Th_scl 4.0us 0.6us High period of SCL`
121			`// Tl_scl 4.7us 1.3us Low period of SCL`
122			`// Tsu:sta 4.7us 0.6us setup time for a repeated start condition`
123			`// Tsu:sto 4.0us 0.6us setup time for a stop conditon`
124			`// Tbuf 4.7us 1.3us Bus free time between a stop and start condition`
125	10	rherveille	`//`
126
127	29	rherveille	`// synopsys translate_off`
128	10	rherveille	`include "timescale.v"
129	29	rherveille	`// synopsys translate_on`
130
131	10	rherveille	`include "i2c_master_defines.v"
132
133	29	rherveille	`module i2c_master_bit_ctrl(`
134			`clk, rst, nReset,`
135			`clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout,`
136			`scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen`
137			`);`
138	10	rherveille
139			`//`
140			`// inputs & outputs`
141			`//`
142			`input clk;`
143			`input rst;`
144			`input nReset;`
145			`input ena; // core enable signal`
146
147			`input [15:0] clk_cnt; // clock prescale value`
148
149			`input [3:0] cmd;`
150	29	rherveille	`output cmd_ack; // command complete acknowledge`
151	10	rherveille	`reg cmd_ack;`
152	29	rherveille	`output busy; // i2c bus busy`
153	10	rherveille	`reg busy;`
154	29	rherveille	`output al; // i2c bus arbitration lost`
155			`reg al;`
156	10	rherveille
157			`input din;`
158			`output dout;`
159			`reg dout;`
160
161			`// I2C lines`
162	29	rherveille	`input scl_i; // i2c clock line input`
163			`output scl_o; // i2c clock line output`
164			`output scl_oen; // i2c clock line output enable (active low)`
165	10	rherveille	`reg scl_oen;`
166	29	rherveille	`input sda_i; // i2c data line input`
167			`output sda_o; // i2c data line output`
168			`output sda_oen; // i2c data line output enable (active low)`
169	10	rherveille	`reg sda_oen;`
170
171
172			`//`
173			`// variable declarations`
174			`//`
175
176	22	rherveille	`reg sSCL, sSDA; // synchronized SCL and SDA inputs`
177			`reg dscl_oen; // delayed scl_oen`
178	29	rherveille	`reg sda_chk; // check SDA output (Multi-master arbitration)`
179	10	rherveille	`reg clk_en; // clock generation signals`
180			`wire slave_wait;`
181	22	rherveille	`// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)`
182	10	rherveille	`reg [15:0] cnt; // clock divider counter (synthesis)`
183
184	52	rherveille	`// state machine variable`
185	62	rherveille	`reg [17:0] c_state; // synopsys enum_state`
186	52	rherveille
187	10	rherveille	`//`
188			`// module body`
189			`//`
190
191	29	rherveille	`// whenever the slave is not ready it can delay the cycle by pulling SCL low`
192	22	rherveille	`// delay scl_oen`
193			`always @(posedge clk)`
194	24	rherveille	`dscl_oen <= #1 scl_oen;`
195	22	rherveille
196			`assign slave_wait = dscl_oen && !sSCL;`
197	10	rherveille
198	29	rherveille
199	10	rherveille	`// generate clk enable signal`
200	24	rherveille	`always @(posedge clk or negedge nReset)`
201			`if(~nReset)`
202			`begin`
203			`cnt <= #1 16'h0;`
204			`clk_en <= #1 1'b1;`
205			`end`
206			`else if (rst)`
207			`begin`
208			`cnt <= #1 16'h0;`
209			`clk_en <= #1 1'b1;`
210			`end`
211	57	rherveille	`else if ( ~\|cnt \|\| !ena)`
212			`begin`
213			`cnt <= #1 clk_cnt;`
214			`clk_en <= #1 1'b1;`
215			`end`
216			`else if (slave_wait)`
217			`begin`
218			`cnt <= #1 cnt;`
219			`clk_en <= #1 1'b0;`
220			`end`
221	24	rherveille	`else`
222			`begin`
223	57	rherveille	`cnt <= #1 cnt - 16'h1;`
224	24	rherveille	`clk_en <= #1 1'b0;`
225			`end`
226	10	rherveille
227
228			`// generate bus status controller`
229	29	rherveille	`reg dSCL, dSDA;`
230	10	rherveille	`reg sta_condition;`
231			`reg sto_condition;`
232
233	29	rherveille	`// synchronize SCL and SDA inputs`
234			`// reduce metastability risc`
235	35	rherveille	`always @(posedge clk or negedge nReset)`
236			`if (~nReset)`
237			`begin`
238			`sSCL <= #1 1'b1;`
239			`sSDA <= #1 1'b1;`
240	29	rherveille
241	35	rherveille	`dSCL <= #1 1'b1;`
242			`dSDA <= #1 1'b1;`
243			`end`
244			`else if (rst)`
245			`begin`
246			`sSCL <= #1 1'b1;`
247			`sSDA <= #1 1'b1;`
248	29	rherveille
249	35	rherveille	`dSCL <= #1 1'b1;`
250			`dSDA <= #1 1'b1;`
251			`end`
252			`else`
253			`begin`
254			`sSCL <= #1 scl_i;`
255			`sSDA <= #1 sda_i;`
256
257			`dSCL <= #1 sSCL;`
258			`dSDA <= #1 sSDA;`
259			`end`
260
261	10	rherveille	`// detect start condition => detect falling edge on SDA while SCL is high`
262			`// detect stop condition => detect rising edge on SDA while SCL is high`
263	35	rherveille	`always @(posedge clk or negedge nReset)`
264			`if (~nReset)`
265			`begin`
266			`sta_condition <= #1 1'b0;`
267			`sto_condition <= #1 1'b0;`
268			`end`
269			`else if (rst)`
270			`begin`
271			`sta_condition <= #1 1'b0;`
272			`sto_condition <= #1 1'b0;`
273			`end`
274			`else`
275			`begin`
276			`sta_condition <= #1 ~sSDA & dSDA & sSCL;`
277			`sto_condition <= #1 sSDA & ~dSDA & sSCL;`
278			`end`
279	10	rherveille
280	30	rherveille	`// generate i2c bus busy signal`
281	24	rherveille	`always @(posedge clk or negedge nReset)`
282			`if(!nReset)`
283			`busy <= #1 1'b0;`
284			`else if (rst)`
285			`busy <= #1 1'b0;`
286			`else`
287	27	rherveille	`busy <= #1 (sta_condition \| busy) & ~sto_condition;`
288	10	rherveille
289	29	rherveille	`// generate arbitration lost signal`
290			`// aribitration lost when:`
291			`// 1) master drives SDA high, but the i2c bus is low`
292			`// 2) stop detected while not requested`
293	38	rherveille	`reg cmd_stop;`
294	35	rherveille	`always @(posedge clk or negedge nReset)`
295			`if (~nReset)`
296	38	rherveille	`cmd_stop <= #1 1'b0;`
297	35	rherveille	`else if (rst)`
298	38	rherveille	`cmd_stop <= #1 1'b0;`
299			`else if (clk_en)`
300			cmd_stop <= #1 cmd == `I2C_CMD_STOP;
301
302			`always @(posedge clk or negedge nReset)`
303			`if (~nReset)`
304			`al <= #1 1'b0;`
305			`else if (rst)`
306			`al <= #1 1'b0;`
307	35	rherveille	`else`
308	52	rherveille	`al <= #1 (sda_chk & ~sSDA & sda_oen) \| (\|c_state & sto_condition & ~cmd_stop);`
309	10	rherveille
310	29	rherveille
311			`// generate dout signal (store SDA on rising edge of SCL)`
312			`always @(posedge clk)`
313			`if(sSCL & ~dSCL)`
314			`dout <= #1 sSDA;`
315
316	10	rherveille	`// generate statemachine`
317
318			`// nxt_state decoder`
319	62	rherveille	`parameter [17:0] idle = 18'b0_0000_0000_0000_0000;`
320			`parameter [17:0] start_a = 18'b0_0000_0000_0000_0001;`
321			`parameter [17:0] start_b = 18'b0_0000_0000_0000_0010;`
322			`parameter [17:0] start_c = 18'b0_0000_0000_0000_0100;`
323			`parameter [17:0] start_d = 18'b0_0000_0000_0000_1000;`
324			`parameter [17:0] start_e = 18'b0_0000_0000_0001_0000;`
325			`parameter [17:0] stop_a = 18'b0_0000_0000_0010_0000;`
326			`parameter [17:0] stop_b = 18'b0_0000_0000_0100_0000;`
327			`parameter [17:0] stop_c = 18'b0_0000_0000_1000_0000;`
328			`parameter [17:0] stop_d = 18'b0_0000_0001_0000_0000;`
329			`parameter [17:0] rd_a = 18'b0_0000_0010_0000_0000;`
330			`parameter [17:0] rd_b = 18'b0_0000_0100_0000_0000;`
331			`parameter [17:0] rd_c = 18'b0_0000_1000_0000_0000;`
332			`parameter [17:0] rd_d = 18'b0_0001_0000_0000_0000;`
333			`parameter [17:0] wr_a = 18'b0_0010_0000_0000_0000;`
334			`parameter [17:0] wr_b = 18'b0_0100_0000_0000_0000;`
335			`parameter [17:0] wr_c = 18'b0_1000_0000_0000_0000;`
336			`parameter [17:0] wr_d = 18'b1_0000_0000_0000_0000;`
337	10	rherveille
338	24	rherveille	`always @(posedge clk or negedge nReset)`
339			`if (!nReset)`
340			`begin`
341			`c_state <= #1 idle;`
342			`cmd_ack <= #1 1'b0;`
343	27	rherveille	`scl_oen <= #1 1'b1;`
344			`sda_oen <= #1 1'b1;`
345	29	rherveille	`sda_chk <= #1 1'b0;`
346	24	rherveille	`end`
347	29	rherveille	`else if (rst \| al)`
348	24	rherveille	`begin`
349			`c_state <= #1 idle;`
350			`cmd_ack <= #1 1'b0;`
351	27	rherveille	`scl_oen <= #1 1'b1;`
352			`sda_oen <= #1 1'b1;`
353	29	rherveille	`sda_chk <= #1 1'b0;`
354	24	rherveille	`end`
355			`else`
356			`begin`
357	27	rherveille	`cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle`
358
359	24	rherveille	`if (clk_en)`
360	52	rherveille	`case (c_state) // synopsys full_case parallel_case`
361	27	rherveille	`// idle state`
362			`idle:`
363			`begin`
364	52	rherveille	`case (cmd) // synopsys full_case parallel_case`
365	27	rherveille	`I2C_CMD_START:
366			`c_state <= #1 start_a;`
367	10	rherveille
368	27	rherveille	`I2C_CMD_STOP:
369			`c_state <= #1 stop_a;`
370	10	rherveille
371	27	rherveille	`I2C_CMD_WRITE:
372			`c_state <= #1 wr_a;`
373	10	rherveille
374	27	rherveille	`I2C_CMD_READ:
375			`c_state <= #1 rd_a;`
376	10	rherveille
377	27	rherveille	`default:`
378			`c_state <= #1 idle;`
379			`endcase`
380	10	rherveille
381	27	rherveille	`scl_oen <= #1 scl_oen; // keep SCL in same state`
382			`sda_oen <= #1 sda_oen; // keep SDA in same state`
383	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
384	27	rherveille	`end`
385	10	rherveille
386	27	rherveille	`// start`
387			`start_a:`
388			`begin`
389			`c_state <= #1 start_b;`
390			`scl_oen <= #1 scl_oen; // keep SCL in same state`
391			`sda_oen <= #1 1'b1; // set SDA high`
392	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
393	27	rherveille	`end`
394	10	rherveille
395	27	rherveille	`start_b:`
396			`begin`
397			`c_state <= #1 start_c;`
398			`scl_oen <= #1 1'b1; // set SCL high`
399			`sda_oen <= #1 1'b1; // keep SDA high`
400	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
401	27	rherveille	`end`
402	10	rherveille
403	27	rherveille	`start_c:`
404			`begin`
405			`c_state <= #1 start_d;`
406			`scl_oen <= #1 1'b1; // keep SCL high`
407			`sda_oen <= #1 1'b0; // set SDA low`
408	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
409	27	rherveille	`end`
410	10	rherveille
411	27	rherveille	`start_d:`
412			`begin`
413			`c_state <= #1 start_e;`
414			`scl_oen <= #1 1'b1; // keep SCL high`
415			`sda_oen <= #1 1'b0; // keep SDA low`
416	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
417	27	rherveille	`end`
418	10	rherveille
419	27	rherveille	`start_e:`
420			`begin`
421			`c_state <= #1 idle;`
422			`cmd_ack <= #1 1'b1;`
423			`scl_oen <= #1 1'b0; // set SCL low`
424			`sda_oen <= #1 1'b0; // keep SDA low`
425	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
426	27	rherveille	`end`
427	10	rherveille
428	27	rherveille	`// stop`
429			`stop_a:`
430			`begin`
431			`c_state <= #1 stop_b;`
432			`scl_oen <= #1 1'b0; // keep SCL low`
433			`sda_oen <= #1 1'b0; // set SDA low`
434	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
435	27	rherveille	`end`
436	10	rherveille
437	27	rherveille	`stop_b:`
438			`begin`
439			`c_state <= #1 stop_c;`
440			`scl_oen <= #1 1'b1; // set SCL high`
441			`sda_oen <= #1 1'b0; // keep SDA low`
442	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
443	27	rherveille	`end`
444	10	rherveille
445	27	rherveille	`stop_c:`
446			`begin`
447			`c_state <= #1 stop_d;`
448			`scl_oen <= #1 1'b1; // keep SCL high`
449			`sda_oen <= #1 1'b0; // keep SDA low`
450	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
451	27	rherveille	`end`
452	10	rherveille
453	27	rherveille	`stop_d:`
454			`begin`
455			`c_state <= #1 idle;`
456	36	rherveille	`cmd_ack <= #1 1'b1;`
457	27	rherveille	`scl_oen <= #1 1'b1; // keep SCL high`
458			`sda_oen <= #1 1'b1; // set SDA high`
459	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
460	27	rherveille	`end`
461	10	rherveille
462	27	rherveille	`// read`
463			`rd_a:`
464			`begin`
465			`c_state <= #1 rd_b;`
466			`scl_oen <= #1 1'b0; // keep SCL low`
467			`sda_oen <= #1 1'b1; // tri-state SDA`
468	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
469	27	rherveille	`end`
470	10	rherveille
471	27	rherveille	`rd_b:`
472			`begin`
473			`c_state <= #1 rd_c;`
474			`scl_oen <= #1 1'b1; // set SCL high`
475			`sda_oen <= #1 1'b1; // keep SDA tri-stated`
476	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
477	27	rherveille	`end`
478	10	rherveille
479	27	rherveille	`rd_c:`
480			`begin`
481			`c_state <= #1 rd_d;`
482			`scl_oen <= #1 1'b1; // keep SCL high`
483	29	rherveille	`sda_oen <= #1 1'b1; // keep SDA tri-stated`
484			`sda_chk <= #1 1'b0; // don't check SDA output`
485	27	rherveille	`end`
486	10	rherveille
487	27	rherveille	`rd_d:`
488			`begin`
489			`c_state <= #1 idle;`
490	36	rherveille	`cmd_ack <= #1 1'b1;`
491	27	rherveille	`scl_oen <= #1 1'b0; // set SCL low`
492	29	rherveille	`sda_oen <= #1 1'b1; // keep SDA tri-stated`
493			`sda_chk <= #1 1'b0; // don't check SDA output`
494	27	rherveille	`end`
495	10	rherveille
496	27	rherveille	`// write`
497			`wr_a:`
498			`begin`
499			`c_state <= #1 wr_b;`
500			`scl_oen <= #1 1'b0; // keep SCL low`

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