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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE rev.B2 compliant I2C Master bit-controller        ////
////                                                             ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: i2c_master_bit_ctrl.v,v 1.14 2009-01-20 10:25:29 rherveille Exp $
//
//  $Date: 2009-01-20 10:25:29 $
//  $Revision: 1.14 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.13  2009/01/19 20:29:26  rherveille
//               Fixed synopsys miss spell (synopsis)
//               Fixed cr[0] register width
//               Fixed ! usage instead of ~
//               Fixed bit controller parameter width to 18bits
//
//               Revision 1.12  2006/09/04 09:08:13  rherveille
//               fixed short scl high pulse after clock stretch
//               fixed slave model not returning correct '(n)ack' signal
//
//               Revision 1.11  2004/05/07 11:02:26  rherveille
//               Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
//
//               Revision 1.10  2003/08/09 07:01:33  rherveille
//               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
//               Fixed a potential bug in the byte controller's host-acknowledge generation.
//
//               Revision 1.9  2003/03/10 14:26:37  rherveille
//               Fixed cmd_ack generation item (no bug).
//
//               Revision 1.8  2003/02/05 00:06:10  rherveille
//               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
//
//               Revision 1.7  2002/12/26 16:05:12  rherveille
//               Small code simplifications
//
//               Revision 1.6  2002/12/26 15:02:32  rherveille
//               Core is now a Multimaster I2C controller
//
//               Revision 1.5  2002/11/30 22:24:40  rherveille
//               Cleaned up code
//
//               Revision 1.4  2002/10/30 18:10:07  rherveille
//               Fixed some reported minor start/stop generation timing issuess.
//
//               Revision 1.3  2002/06/15 07:37:03  rherveille
//               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
//
//               Revision 1.2  2001/11/05 11:59:25  rherveille
//               Fixed wb_ack_o generation bug.
//               Fixed bug in the byte_controller statemachine.
//               Added headers.
//
 
//
/////////////////////////////////////
// Bit controller section
/////////////////////////////////////
//
// Translate simple commands into SCL/SDA transitions
// Each command has 5 states, A/B/C/D/idle
//
// start:       SCL     ~~~~~~~~~~\____
//      SDA     ~~~~~~~~\______
//               x | A | B | C | D | i
//
// repstart     SCL     ____/~~~~\___
//      SDA     __/~~~\______
//               x | A | B | C | D | i
//
// stop SCL     ____/~~~~~~~~
//      SDA     ==\____/~~~~~
//               x | A | B | C | D | i
//
//- write       SCL     ____/~~~~\____
//      SDA     ==X=========X=
//               x | A | B | C | D | i
//
//- read        SCL     ____/~~~~\____
//      SDA     XXXX=====XXXX
//               x | A | B | C | D | i
//
 
// Timing:     Normal mode      Fast mode
///////////////////////////////////////////////////////////////////////
// Fscl        100KHz           400KHz
// Th_scl      4.0us            0.6us   High period of SCL
// Tl_scl      4.7us            1.3us   Low period of SCL
// Tsu:sta     4.7us            0.6us   setup time for a repeated start condition
// Tsu:sto     4.0us            0.6us   setup time for a stop conditon
// Tbuf        4.7us            1.3us   Bus free time between a stop and start condition
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`include "i2c_master_defines.v"
 
module i2c_master_bit_ctrl(
        clk, rst, nReset,
        clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout,
        scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen
        );
 
        //
        // inputs & outputs
        //
        input clk;
        input rst;
        input nReset;
        input ena;            // core enable signal
 
        input [15:0] clk_cnt; // clock prescale value
 
        input  [3:0] cmd;
        output       cmd_ack; // command complete acknowledge
        reg cmd_ack;
        output       busy;    // i2c bus busy
        reg busy;
        output       al;      // i2c bus arbitration lost
        reg al;
 
        input  din;
        output dout;
        reg dout;
 
        // I2C lines
        input  scl_i;         // i2c clock line input
        output scl_o;         // i2c clock line output
        output scl_oen;       // i2c clock line output enable (active low)
        reg scl_oen;
        input  sda_i;         // i2c data line input
        output sda_o;         // i2c data line output
        output sda_oen;       // i2c data line output enable (active low)
        reg sda_oen;
 
 
        //
        // variable declarations
        //
 
        reg sSCL, sSDA;             // synchronized SCL and SDA inputs
        reg dSCL, dSDA;             // delayed versions of sSCL and sSDA
        reg dscl_oen;               // delayed scl_oen
        reg sda_chk;                // check SDA output (Multi-master arbitration)
        reg clk_en;                 // clock generation signals
        reg slave_wait;             // slave inserts wait states
//      reg [15:0] cnt = clk_cnt;   // clock divider counter (simulation)
        reg [15:0] cnt;             // clock divider counter (synthesis)
 
        // state machine variable
        reg [17:0] c_state; // synopsys enum_state
 
        //
        // module body
        //
 
        // whenever the slave is not ready it can delay the cycle by pulling SCL low
        // delay scl_oen
        always @(posedge clk)
          dscl_oen <= #1 scl_oen;
 
        // slave_wait is asserted when master wants to drive SCL high, but the slave (another master) pulls it low
        // slave_wait remains asserted until the slave (other master) releases SCL
        always @(posedge clk or negedge nReset)
          if (!nReset) slave_wait <= 1'b0;
          else         slave_wait = (scl_oen & ~dscl_oen & ~sSCL) | (slave_wait & ~sSCL);
 
        // master drives SCL high, but another master pulls it low
        // master start counting down its low cycle now (clock synchronization)
        wire scl_sync   = dSCL & ~sSCL & scl_oen;
 
        // generate clk enable signal
        always @(posedge clk or negedge nReset)
          if(~nReset)
            begin
                cnt    <= #1 16'h0;
                clk_en <= #1 1'b1;
            end
          else if (rst)
            begin
                cnt    <= #1 16'h0;
                clk_en <= #1 1'b1;
            end
          else if ( ~|cnt || !ena || scl_sync)
            begin
                cnt    <= #1 clk_cnt;
                clk_en <= #1 1'b1;
            end
          else if (slave_wait)
            begin
                cnt    <= #1 cnt;
                clk_en <= #1 1'b0;
            end
          else
            begin
                cnt    <= #1 cnt - 16'h1;
                clk_en <= #1 1'b0;
            end
 
 
        // generate bus status controller
        reg sta_condition;
        reg sto_condition;
 
        // synchronize SCL and SDA inputs
        // reduce metastability risc
        always @(posedge clk or negedge nReset)
          if (~nReset)
            begin
                sSCL <= #1 1'b1;
                sSDA <= #1 1'b1;
 
                dSCL <= #1 1'b1;
                dSDA <= #1 1'b1;
            end
          else if (rst)
            begin
                sSCL <= #1 1'b1;
                sSDA <= #1 1'b1;
 
                dSCL <= #1 1'b1;
                dSDA <= #1 1'b1;
            end
          else
            begin
                sSCL <= #1 scl_i;
                sSDA <= #1 sda_i;
 
                dSCL <= #1 sSCL;
                dSDA <= #1 sSDA;
            end
 
        // detect start condition => detect falling edge on SDA while SCL is high
        // detect stop condition => detect rising edge on SDA while SCL is high
        always @(posedge clk or negedge nReset)
          if (~nReset)
            begin
                sta_condition <= #1 1'b0;
                sto_condition <= #1 1'b0;
            end
          else if (rst)
            begin
                sta_condition <= #1 1'b0;
                sto_condition <= #1 1'b0;
            end
          else
            begin
                sta_condition <= #1 ~sSDA &  dSDA & sSCL;
                sto_condition <= #1  sSDA & ~dSDA & sSCL;
            end
 
        // generate i2c bus busy signal
        always @(posedge clk or negedge nReset)
          if(!nReset)
            busy <= #1 1'b0;
          else if (rst)
            busy <= #1 1'b0;
          else
            busy <= #1 (sta_condition | busy) & ~sto_condition;
 
        // generate arbitration lost signal
        // aribitration lost when:
        // 1) master drives SDA high, but the i2c bus is low
        // 2) stop detected while not requested
        reg cmd_stop;
        always @(posedge clk or negedge nReset)
          if (~nReset)
            cmd_stop <= #1 1'b0;
          else if (rst)
            cmd_stop <= #1 1'b0;
          else if (clk_en)
            cmd_stop <= #1 cmd == `I2C_CMD_STOP;
 
        always @(posedge clk or negedge nReset)
          if (~nReset)
            al <= #1 1'b0;
          else if (rst)
            al <= #1 1'b0;
          else
            al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
 
 
        // generate dout signal (store SDA on rising edge of SCL)
        always @(posedge clk)
          if(sSCL & ~dSCL)
            dout <= #1 sSDA;
 
        // generate statemachine
 
        // nxt_state decoder
        parameter [17:0] idle    = 18'b0_0000_0000_0000_0000;
        parameter [17:0] start_a = 18'b0_0000_0000_0000_0001;
        parameter [17:0] start_b = 18'b0_0000_0000_0000_0010;
        parameter [17:0] start_c = 18'b0_0000_0000_0000_0100;
        parameter [17:0] start_d = 18'b0_0000_0000_0000_1000;
        parameter [17:0] start_e = 18'b0_0000_0000_0001_0000;
        parameter [17:0] stop_a  = 18'b0_0000_0000_0010_0000;
        parameter [17:0] stop_b  = 18'b0_0000_0000_0100_0000;
        parameter [17:0] stop_c  = 18'b0_0000_0000_1000_0000;
        parameter [17:0] stop_d  = 18'b0_0000_0001_0000_0000;
        parameter [17:0] rd_a    = 18'b0_0000_0010_0000_0000;
        parameter [17:0] rd_b    = 18'b0_0000_0100_0000_0000;
        parameter [17:0] rd_c    = 18'b0_0000_1000_0000_0000;
        parameter [17:0] rd_d    = 18'b0_0001_0000_0000_0000;
        parameter [17:0] wr_a    = 18'b0_0010_0000_0000_0000;
        parameter [17:0] wr_b    = 18'b0_0100_0000_0000_0000;
        parameter [17:0] wr_c    = 18'b0_1000_0000_0000_0000;
        parameter [17:0] wr_d    = 18'b1_0000_0000_0000_0000;
 
        always @(posedge clk or negedge nReset)
          if (!nReset)
            begin
                c_state <= #1 idle;
                cmd_ack <= #1 1'b0;
                scl_oen <= #1 1'b1;
                sda_oen <= #1 1'b1;
                sda_chk <= #1 1'b0;
            end
          else if (rst | al)
            begin
                c_state <= #1 idle;
                cmd_ack <= #1 1'b0;
                scl_oen <= #1 1'b1;
                sda_oen <= #1 1'b1;
                sda_chk <= #1 1'b0;
            end
          else
            begin
                cmd_ack   <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
 
                if (clk_en)
                  case (c_state) // synopsys full_case parallel_case
                    // idle state
                    idle:
                    begin
                        case (cmd) // synopsys full_case parallel_case
                          `I2C_CMD_START:
                             c_state <= #1 start_a;
 
                          `I2C_CMD_STOP:
                             c_state <= #1 stop_a;
 
                          `I2C_CMD_WRITE:
                             c_state <= #1 wr_a;
 
                          `I2C_CMD_READ:
                             c_state <= #1 rd_a;
 
                          default:
                            c_state <= #1 idle;
                        endcase
 
                        scl_oen <= #1 scl_oen; // keep SCL in same state
                        sda_oen <= #1 sda_oen; // keep SDA in same state
                        sda_chk <= #1 1'b0;    // don't check SDA output
                    end
 
                    // start
                    start_a:
                    begin
                        c_state <= #1 start_b;
                        scl_oen <= #1 scl_oen; // keep SCL in same state
                        sda_oen <= #1 1'b1;    // set SDA high
                        sda_chk <= #1 1'b0;    // don't check SDA output
                    end
 
                    start_b:
                    begin
                        c_state <= #1 start_c;
                        scl_oen <= #1 1'b1; // set SCL high
                        sda_oen <= #1 1'b1; // keep SDA high
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    start_c:
                    begin
                        c_state <= #1 start_d;
                        scl_oen <= #1 1'b1; // keep SCL high
                        sda_oen <= #1 1'b0; // set SDA low
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    start_d:
                    begin
                        c_state <= #1 start_e;
                        scl_oen <= #1 1'b1; // keep SCL high
                        sda_oen <= #1 1'b0; // keep SDA low
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    start_e:
                    begin
                        c_state <= #1 idle;
                        cmd_ack <= #1 1'b1;
                        scl_oen <= #1 1'b0; // set SCL low
                        sda_oen <= #1 1'b0; // keep SDA low
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    // stop
                    stop_a:
                    begin
                        c_state <= #1 stop_b;
                        scl_oen <= #1 1'b0; // keep SCL low
                        sda_oen <= #1 1'b0; // set SDA low
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    stop_b:
                    begin
                        c_state <= #1 stop_c;
                        scl_oen <= #1 1'b1; // set SCL high
                        sda_oen <= #1 1'b0; // keep SDA low
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    stop_c:
                    begin
                        c_state <= #1 stop_d;
                        scl_oen <= #1 1'b1; // keep SCL high
                        sda_oen <= #1 1'b0; // keep SDA low
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    stop_d:
                    begin
                        c_state <= #1 idle;
                        cmd_ack <= #1 1'b1;
                        scl_oen <= #1 1'b1; // keep SCL high
                        sda_oen <= #1 1'b1; // set SDA high
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    // read
                    rd_a:
                    begin
                        c_state <= #1 rd_b;
                        scl_oen <= #1 1'b0; // keep SCL low
                        sda_oen <= #1 1'b1; // tri-state SDA
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    rd_b:
                    begin
                        c_state <= #1 rd_c;
                        scl_oen <= #1 1'b1; // set SCL high
                        sda_oen <= #1 1'b1; // keep SDA tri-stated
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    rd_c:
                    begin
                        c_state <= #1 rd_d;
                        scl_oen <= #1 1'b1; // keep SCL high
                        sda_oen <= #1 1'b1; // keep SDA tri-stated
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    rd_d:
                    begin
                        c_state <= #1 idle;
                        cmd_ack <= #1 1'b1;
                        scl_oen <= #1 1'b0; // set SCL low
                        sda_oen <= #1 1'b1; // keep SDA tri-stated
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    // write
                    wr_a:
                    begin
                        c_state <= #1 wr_b;
                        scl_oen <= #1 1'b0; // keep SCL low
                        sda_oen <= #1 din;  // set SDA
                        sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
                    end
 
                    wr_b:
                    begin
                        c_state <= #1 wr_c;
                        scl_oen <= #1 1'b1; // set SCL high
                        sda_oen <= #1 din;  // keep SDA
                        sda_chk <= #1 1'b1; // check SDA output
                    end
 
                    wr_c:
                    begin
                        c_state <= #1 wr_d;
                        scl_oen <= #1 1'b1; // keep SCL high
                        sda_oen <= #1 din;
                        sda_chk <= #1 1'b1; // check SDA output
                    end
 
                    wr_d:
                    begin
                        c_state <= #1 idle;
                        cmd_ack <= #1 1'b1;
                        scl_oen <= #1 1'b0; // set SCL low
                        sda_oen <= #1 din;
                        sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
                    end
 
                  endcase
            end
 
 
        // assign scl and sda output (always gnd)
        assign scl_o = 1'b0;
        assign sda_o = 1'b0;
 
endmodule

Line No.	Rev	Author	Line
1	14	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE rev.B2 compliant I2C Master bit-controller ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/i2c/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	10	rherveille	`//`
40	63	rherveille	`// $Id: i2c_master_bit_ctrl.v,v 1.14 2009-01-20 10:25:29 rherveille Exp $`
41	10	rherveille	`//`
42	63	rherveille	`// $Date: 2009-01-20 10:25:29 $`
43			`// $Revision: 1.14 $`
44	14	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47	10	rherveille	`//`
48	14	rherveille	`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	63	rherveille	`// Revision 1.13 2009/01/19 20:29:26 rherveille`
51			`// Fixed synopsys miss spell (synopsis)`
52			`// Fixed cr[0] register width`
53			`// Fixed ! usage instead of ~`
54			`// Fixed bit controller parameter width to 18bits`
55			`//`
56	62	rherveille	`// Revision 1.12 2006/09/04 09:08:13 rherveille`
57			`// fixed short scl high pulse after clock stretch`
58			`// fixed slave model not returning correct '(n)ack' signal`
59			`//`
60	57	rherveille	`// Revision 1.11 2004/05/07 11:02:26 rherveille`
61			`// Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.`
62			`//`
63	52	rherveille	`// Revision 1.10 2003/08/09 07:01:33 rherveille`
64			`// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.`
65			`// Fixed a potential bug in the byte controller's host-acknowledge generation.`
66			`//`
67	38	rherveille	`// Revision 1.9 2003/03/10 14:26:37 rherveille`
68			`// Fixed cmd_ack generation item (no bug).`
69			`//`
70	36	rherveille	`// Revision 1.8 2003/02/05 00:06:10 rherveille`
71			`// Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.`
72			`//`
73	35	rherveille	`// Revision 1.7 2002/12/26 16:05:12 rherveille`
74			`// Small code simplifications`
75			`//`
76	30	rherveille	`// Revision 1.6 2002/12/26 15:02:32 rherveille`
77			`// Core is now a Multimaster I2C controller`
78			`//`
79	29	rherveille	`// Revision 1.5 2002/11/30 22:24:40 rherveille`
80			`// Cleaned up code`
81			`//`
82	27	rherveille	`// Revision 1.4 2002/10/30 18:10:07 rherveille`
83			`// Fixed some reported minor start/stop generation timing issuess.`
84			`//`
85	24	rherveille	`// Revision 1.3 2002/06/15 07:37:03 rherveille`
86			`// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.`
87			`//`
88	22	rherveille	`// Revision 1.2 2001/11/05 11:59:25 rherveille`
89			`// Fixed wb_ack_o generation bug.`
90			`// Fixed bug in the byte_controller statemachine.`
91			`// Added headers.`
92			`//`
93	10	rherveille
94			`//`
95			`/////////////////////////////////////`
96			`// Bit controller section`
97			`/////////////////////////////////////`
98			`//`
99			`// Translate simple commands into SCL/SDA transitions`
100			`// Each command has 5 states, A/B/C/D/idle`
101			`//`
102			`// start: SCL ~~~~~~~~~~\____`
103			`// SDA ~~~~~~~~\______`
104			`// x \| A \| B \| C \| D \| i`
105			`//`
106			`// repstart SCL ____/~~~~\___`
107			`// SDA __/~~~\______`
108			`// x \| A \| B \| C \| D \| i`
109			`//`
110			`// stop SCL ____/~~~~~~~~`
111			`// SDA ==\____/~~~~~`
112			`// x \| A \| B \| C \| D \| i`
113			`//`
114			`//- write SCL ____/~~~~\____`
115			`// SDA ==X=========X=`
116			`// x \| A \| B \| C \| D \| i`
117			`//`
118			`//- read SCL ____/~~~~\____`
119			`// SDA XXXX=====XXXX`
120			`// x \| A \| B \| C \| D \| i`
121			`//`
122
123	24	rherveille	`// Timing: Normal mode Fast mode`
124	10	rherveille	`///////////////////////////////////////////////////////////////////////`
125	24	rherveille	`// Fscl 100KHz 400KHz`
126			`// Th_scl 4.0us 0.6us High period of SCL`
127			`// Tl_scl 4.7us 1.3us Low period of SCL`
128			`// Tsu:sta 4.7us 0.6us setup time for a repeated start condition`
129			`// Tsu:sto 4.0us 0.6us setup time for a stop conditon`
130			`// Tbuf 4.7us 1.3us Bus free time between a stop and start condition`
131	10	rherveille	`//`
132
133	29	rherveille	`// synopsys translate_off`
134	10	rherveille	`include "timescale.v"
135	29	rherveille	`// synopsys translate_on`
136
137	10	rherveille	`include "i2c_master_defines.v"
138
139	29	rherveille	`module i2c_master_bit_ctrl(`
140			`clk, rst, nReset,`
141			`clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout,`
142			`scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen`
143			`);`
144	10	rherveille
145			`//`
146			`// inputs & outputs`
147			`//`
148			`input clk;`
149			`input rst;`
150			`input nReset;`
151			`input ena; // core enable signal`
152
153			`input [15:0] clk_cnt; // clock prescale value`
154
155			`input [3:0] cmd;`
156	29	rherveille	`output cmd_ack; // command complete acknowledge`
157	10	rherveille	`reg cmd_ack;`
158	29	rherveille	`output busy; // i2c bus busy`
159	10	rherveille	`reg busy;`
160	29	rherveille	`output al; // i2c bus arbitration lost`
161			`reg al;`
162	10	rherveille
163			`input din;`
164			`output dout;`
165			`reg dout;`
166
167			`// I2C lines`
168	29	rherveille	`input scl_i; // i2c clock line input`
169			`output scl_o; // i2c clock line output`
170			`output scl_oen; // i2c clock line output enable (active low)`
171	10	rherveille	`reg scl_oen;`
172	29	rherveille	`input sda_i; // i2c data line input`
173			`output sda_o; // i2c data line output`
174			`output sda_oen; // i2c data line output enable (active low)`
175	10	rherveille	`reg sda_oen;`
176
177
178			`//`
179			`// variable declarations`
180			`//`
181
182	22	rherveille	`reg sSCL, sSDA; // synchronized SCL and SDA inputs`
183	63	rherveille	`reg dSCL, dSDA; // delayed versions of sSCL and sSDA`
184	22	rherveille	`reg dscl_oen; // delayed scl_oen`
185	29	rherveille	`reg sda_chk; // check SDA output (Multi-master arbitration)`
186	10	rherveille	`reg clk_en; // clock generation signals`
187	63	rherveille	`reg slave_wait; // slave inserts wait states`
188	22	rherveille	`// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)`
189	10	rherveille	`reg [15:0] cnt; // clock divider counter (synthesis)`
190
191	52	rherveille	`// state machine variable`
192	62	rherveille	`reg [17:0] c_state; // synopsys enum_state`
193	52	rherveille
194	10	rherveille	`//`
195			`// module body`
196			`//`
197
198	29	rherveille	`// whenever the slave is not ready it can delay the cycle by pulling SCL low`
199	22	rherveille	`// delay scl_oen`
200			`always @(posedge clk)`
201	24	rherveille	`dscl_oen <= #1 scl_oen;`
202	22	rherveille
203	63	rherveille	`// slave_wait is asserted when master wants to drive SCL high, but the slave (another master) pulls it low`
204			`// slave_wait remains asserted until the slave (other master) releases SCL`
205			`always @(posedge clk or negedge nReset)`
206			`if (!nReset) slave_wait <= 1'b0;`
207			`else slave_wait = (scl_oen & ~dscl_oen & ~sSCL) \| (slave_wait & ~sSCL);`
208	10	rherveille
209	63	rherveille	`// master drives SCL high, but another master pulls it low`
210			`// master start counting down its low cycle now (clock synchronization)`
211			`wire scl_sync = dSCL & ~sSCL & scl_oen;`
212	29	rherveille
213	10	rherveille	`// generate clk enable signal`
214	24	rherveille	`always @(posedge clk or negedge nReset)`
215			`if(~nReset)`
216			`begin`
217			`cnt <= #1 16'h0;`
218			`clk_en <= #1 1'b1;`
219			`end`
220			`else if (rst)`
221			`begin`
222			`cnt <= #1 16'h0;`
223			`clk_en <= #1 1'b1;`
224			`end`
225	63	rherveille	`else if ( ~\|cnt \|\| !ena \|\| scl_sync)`
226	57	rherveille	`begin`
227			`cnt <= #1 clk_cnt;`
228			`clk_en <= #1 1'b1;`
229			`end`
230			`else if (slave_wait)`
231			`begin`
232			`cnt <= #1 cnt;`
233			`clk_en <= #1 1'b0;`
234			`end`
235	24	rherveille	`else`
236			`begin`
237	57	rherveille	`cnt <= #1 cnt - 16'h1;`
238	24	rherveille	`clk_en <= #1 1'b0;`
239			`end`
240	10	rherveille
241
242			`// generate bus status controller`
243			`reg sta_condition;`
244			`reg sto_condition;`
245
246	29	rherveille	`// synchronize SCL and SDA inputs`
247			`// reduce metastability risc`
248	35	rherveille	`always @(posedge clk or negedge nReset)`
249			`if (~nReset)`
250			`begin`
251			`sSCL <= #1 1'b1;`
252			`sSDA <= #1 1'b1;`
253	29	rherveille
254	35	rherveille	`dSCL <= #1 1'b1;`
255			`dSDA <= #1 1'b1;`
256			`end`
257			`else if (rst)`
258			`begin`
259			`sSCL <= #1 1'b1;`
260			`sSDA <= #1 1'b1;`
261	29	rherveille
262	35	rherveille	`dSCL <= #1 1'b1;`
263			`dSDA <= #1 1'b1;`
264			`end`
265			`else`
266			`begin`
267			`sSCL <= #1 scl_i;`
268			`sSDA <= #1 sda_i;`
269
270			`dSCL <= #1 sSCL;`
271			`dSDA <= #1 sSDA;`
272			`end`
273
274	10	rherveille	`// detect start condition => detect falling edge on SDA while SCL is high`
275			`// detect stop condition => detect rising edge on SDA while SCL is high`
276	35	rherveille	`always @(posedge clk or negedge nReset)`
277			`if (~nReset)`
278			`begin`
279			`sta_condition <= #1 1'b0;`
280			`sto_condition <= #1 1'b0;`
281			`end`
282			`else if (rst)`
283			`begin`
284			`sta_condition <= #1 1'b0;`
285			`sto_condition <= #1 1'b0;`
286			`end`
287			`else`
288			`begin`
289			`sta_condition <= #1 ~sSDA & dSDA & sSCL;`
290			`sto_condition <= #1 sSDA & ~dSDA & sSCL;`
291			`end`
292	10	rherveille
293	30	rherveille	`// generate i2c bus busy signal`
294	24	rherveille	`always @(posedge clk or negedge nReset)`
295			`if(!nReset)`
296			`busy <= #1 1'b0;`
297			`else if (rst)`
298			`busy <= #1 1'b0;`
299			`else`
300	27	rherveille	`busy <= #1 (sta_condition \| busy) & ~sto_condition;`
301	10	rherveille
302	29	rherveille	`// generate arbitration lost signal`
303			`// aribitration lost when:`
304			`// 1) master drives SDA high, but the i2c bus is low`
305			`// 2) stop detected while not requested`
306	38	rherveille	`reg cmd_stop;`
307	35	rherveille	`always @(posedge clk or negedge nReset)`
308			`if (~nReset)`
309	38	rherveille	`cmd_stop <= #1 1'b0;`
310	35	rherveille	`else if (rst)`
311	38	rherveille	`cmd_stop <= #1 1'b0;`
312			`else if (clk_en)`
313			cmd_stop <= #1 cmd == `I2C_CMD_STOP;
314
315			`always @(posedge clk or negedge nReset)`
316			`if (~nReset)`
317			`al <= #1 1'b0;`
318			`else if (rst)`
319			`al <= #1 1'b0;`
320	35	rherveille	`else`
321	52	rherveille	`al <= #1 (sda_chk & ~sSDA & sda_oen) \| (\|c_state & sto_condition & ~cmd_stop);`
322	10	rherveille
323	29	rherveille
324			`// generate dout signal (store SDA on rising edge of SCL)`
325			`always @(posedge clk)`
326			`if(sSCL & ~dSCL)`
327			`dout <= #1 sSDA;`
328
329	10	rherveille	`// generate statemachine`
330
331			`// nxt_state decoder`
332	62	rherveille	`parameter [17:0] idle = 18'b0_0000_0000_0000_0000;`
333			`parameter [17:0] start_a = 18'b0_0000_0000_0000_0001;`
334			`parameter [17:0] start_b = 18'b0_0000_0000_0000_0010;`
335			`parameter [17:0] start_c = 18'b0_0000_0000_0000_0100;`
336			`parameter [17:0] start_d = 18'b0_0000_0000_0000_1000;`
337			`parameter [17:0] start_e = 18'b0_0000_0000_0001_0000;`
338			`parameter [17:0] stop_a = 18'b0_0000_0000_0010_0000;`
339			`parameter [17:0] stop_b = 18'b0_0000_0000_0100_0000;`
340			`parameter [17:0] stop_c = 18'b0_0000_0000_1000_0000;`
341			`parameter [17:0] stop_d = 18'b0_0000_0001_0000_0000;`
342			`parameter [17:0] rd_a = 18'b0_0000_0010_0000_0000;`
343			`parameter [17:0] rd_b = 18'b0_0000_0100_0000_0000;`
344			`parameter [17:0] rd_c = 18'b0_0000_1000_0000_0000;`
345			`parameter [17:0] rd_d = 18'b0_0001_0000_0000_0000;`
346			`parameter [17:0] wr_a = 18'b0_0010_0000_0000_0000;`
347			`parameter [17:0] wr_b = 18'b0_0100_0000_0000_0000;`
348			`parameter [17:0] wr_c = 18'b0_1000_0000_0000_0000;`
349			`parameter [17:0] wr_d = 18'b1_0000_0000_0000_0000;`
350	10	rherveille
351	24	rherveille	`always @(posedge clk or negedge nReset)`
352			`if (!nReset)`
353			`begin`
354			`c_state <= #1 idle;`
355			`cmd_ack <= #1 1'b0;`
356	27	rherveille	`scl_oen <= #1 1'b1;`
357			`sda_oen <= #1 1'b1;`
358	29	rherveille	`sda_chk <= #1 1'b0;`
359	24	rherveille	`end`
360	29	rherveille	`else if (rst \| al)`
361	24	rherveille	`begin`
362			`c_state <= #1 idle;`
363			`cmd_ack <= #1 1'b0;`
364	27	rherveille	`scl_oen <= #1 1'b1;`
365			`sda_oen <= #1 1'b1;`
366	29	rherveille	`sda_chk <= #1 1'b0;`
367	24	rherveille	`end`
368			`else`
369			`begin`
370	27	rherveille	`cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle`
371
372	24	rherveille	`if (clk_en)`
373	52	rherveille	`case (c_state) // synopsys full_case parallel_case`
374	27	rherveille	`// idle state`
375			`idle:`
376			`begin`
377	52	rherveille	`case (cmd) // synopsys full_case parallel_case`
378	27	rherveille	`I2C_CMD_START:
379			`c_state <= #1 start_a;`
380	10	rherveille
381	27	rherveille	`I2C_CMD_STOP:
382			`c_state <= #1 stop_a;`
383	10	rherveille
384	27	rherveille	`I2C_CMD_WRITE:
385			`c_state <= #1 wr_a;`
386	10	rherveille
387	27	rherveille	`I2C_CMD_READ:
388			`c_state <= #1 rd_a;`
389	10	rherveille
390	27	rherveille	`default:`
391			`c_state <= #1 idle;`
392			`endcase`
393	10	rherveille
394	27	rherveille	`scl_oen <= #1 scl_oen; // keep SCL in same state`
395			`sda_oen <= #1 sda_oen; // keep SDA in same state`
396	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
397	27	rherveille	`end`
398	10	rherveille
399	27	rherveille	`// start`
400			`start_a:`
401			`begin`
402			`c_state <= #1 start_b;`
403			`scl_oen <= #1 scl_oen; // keep SCL in same state`
404			`sda_oen <= #1 1'b1; // set SDA high`
405	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
406	27	rherveille	`end`
407	10	rherveille
408	27	rherveille	`start_b:`
409			`begin`
410			`c_state <= #1 start_c;`
411			`scl_oen <= #1 1'b1; // set SCL high`
412			`sda_oen <= #1 1'b1; // keep SDA high`
413	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
414	27	rherveille	`end`
415	10	rherveille
416	27	rherveille	`start_c:`
417			`begin`
418			`c_state <= #1 start_d;`
419			`scl_oen <= #1 1'b1; // keep SCL high`
420			`sda_oen <= #1 1'b0; // set SDA low`
421	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
422	27	rherveille	`end`
423	10	rherveille
424	27	rherveille	`start_d:`
425			`begin`
426			`c_state <= #1 start_e;`
427			`scl_oen <= #1 1'b1; // keep SCL high`
428			`sda_oen <= #1 1'b0; // keep SDA low`
429	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
430	27	rherveille	`end`
431	10	rherveille
432	27	rherveille	`start_e:`
433			`begin`
434			`c_state <= #1 idle;`
435			`cmd_ack <= #1 1'b1;`
436			`scl_oen <= #1 1'b0; // set SCL low`
437			`sda_oen <= #1 1'b0; // keep SDA low`
438	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
439	27	rherveille	`end`
440	10	rherveille
441	27	rherveille	`// stop`
442			`stop_a:`
443			`begin`
444			`c_state <= #1 stop_b;`
445			`scl_oen <= #1 1'b0; // keep SCL low`
446			`sda_oen <= #1 1'b0; // set SDA low`
447	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
448	27	rherveille	`end`
449	10	rherveille
450	27	rherveille	`stop_b:`
451			`begin`
452			`c_state <= #1 stop_c;`
453			`scl_oen <= #1 1'b1; // set SCL high`
454			`sda_oen <= #1 1'b0; // keep SDA low`
455	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
456	27	rherveille	`end`
457	10	rherveille
458	27	rherveille	`stop_c:`
459			`begin`
460			`c_state <= #1 stop_d;`
461			`scl_oen <= #1 1'b1; // keep SCL high`
462			`sda_oen <= #1 1'b0; // keep SDA low`
463	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
464	27	rherveille	`end`
465	10	rherveille
466	27	rherveille	`stop_d:`
467			`begin`
468			`c_state <= #1 idle;`
469	36	rherveille	`cmd_ack <= #1 1'b1;`
470	27	rherveille	`scl_oen <= #1 1'b1; // keep SCL high`
471			`sda_oen <= #1 1'b1; // set SDA high`
472	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
473	27	rherveille	`end`
474	10	rherveille
475	27	rherveille	`// read`
476			`rd_a:`
477			`begin`
478			`c_state <= #1 rd_b;`
479			`scl_oen <= #1 1'b0; // keep SCL low`
480			`sda_oen <= #1 1'b1; // tri-state SDA`
481	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
482	27	rherveille	`end`
483	10	rherveille
484	27	rherveille	`rd_b:`
485			`begin`
486			`c_state <= #1 rd_c;`
487			`scl_oen <= #1 1'b1; // set SCL high`
488			`sda_oen <= #1 1'b1; // keep SDA tri-stated`
489	29	rherveille	`sda_chk <= #1 1'b0; // don't check SDA output`
490	27	rherveille	`end`
491	10	rherveille
492	27	rherveille	`rd_c:`
493			`begin`
494			`c_state <= #1 rd_d;`
495			`scl_oen <= #1 1'b1; // keep SCL high`
496	29	rherveille	`sda_oen <= #1 1'b1; // keep SDA tri-stated`
497			`sda_chk <= #1 1'b0; // don't check SDA output`
498	27	rherveille	`end`
499	10	rherveille
500	27	rherveille	`rd_d:`

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