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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_defines.v] - Blame information for rev 11

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// I2C registers wishbone addresses
 
// bitcontroller states
`define I2C_CMD_NOP   4'b0000
`define I2C_CMD_START 4'b0001
`define I2C_CMD_STOP  4'b0010
`define I2C_CMD_WRITE 4'b0100
`define I2C_CMD_READ  4'b1000

Line No.	Rev	Author	Line
1	10	rherveille	`// I2C registers wishbone addresses`
2
3			`// bitcontroller states`
4			`define I2C_CMD_NOP 4'b0000
5			`define I2C_CMD_START 4'b0001
6			`define I2C_CMD_STOP 4'b0010
7			`define I2C_CMD_WRITE 4'b0100
8			`define I2C_CMD_READ 4'b1000

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Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_defines.v] - Blame information for rev 11