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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_top.v] - Blame information for rev 11

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//
// WISHBONE revB2 compiant I2C master core
//
// author: Richard Herveille
// rev. 0.1 26-08-2001. Iinitial Verilog release
//
 
`include "timescale.v"
`include "i2c_master_defines.v"
 
module i2c_master_top(
        wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
        wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
        scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
 
        // parameters
        parameter ARST_LVL = 1'b0; // asynchronous reset level
 
        //
        // inputs & outputs
        //
 
        // wishbone signals
        input        wb_clk_i;     // master clock input
        input        wb_rst_i;     // synchronous active high reset
        input        arst_i;       // asynchronous reset
        input  [2:0] wb_adr_i;     // lower address bits
        input  [7:0] wb_dat_i;     // databus input
        output [7:0] wb_dat_o;     // databus output
        reg [7:0] wb_dat_o;
        input        wb_we_i;      // write enable input
        input        wb_stb_i;     // stobe/core select signal
        input        wb_cyc_i;     // valid bus cycle input
        output       wb_ack_o;     // bus cycle acknowledge output
        output       wb_inta_o;    // interrupt request signal output
        reg wb_inta_o;
 
        // I2C signals
        // i2c clock line
        input  scl_pad_i;       // SCL-line input
        output scl_pad_o;       // SCL-line output (always 1'b0)
        output scl_padoen_o;    // SCL-line output enable (active low)
        // i2c data line
        input  sda_pad_i;       // SDA-line input
        output sda_pad_o;       // SDA-line output (always 1'b0)
        output sda_padoen_o;    // SDA-line output enable (active low)
 
 
        //
        // variable declarations
        //
 
        // registers
        reg  [15:0] prer; // clock prescale register
        reg  [ 7:0] ctr;  // control register
        reg  [ 7:0] txr;  // transmit register
        wire [ 7:0] rxr;  // receive register
        reg  [ 7:0] cr;   // command register
        wire [ 7:0] sr;   // status register
 
        // done signal: command completed, clear command register
        wire done;
 
        // core enable signal
        wire core_en;
 
        // status register signals
        wire irxack;
        reg  rxack;       // received aknowledge from slave
        reg  tip;         // transfer in progress
        reg  irq_flag;    // interrupt pending flag
        wire i2c_busy;    // bus busy (start signal detected)
 
        //
        // module body
        //
 
        // generate internal reset
        wire rst_i = arst_i ^ ARST_LVL;
 
        // generate acknowledge output signal
        assign wb_ack_o = wb_cyc_i && wb_stb_i; // because timing is always honored
 
        // assign DAT_O
        always@(wb_adr_i or prer or ctr or txr or cr or rxr or sr)
        begin
                case (wb_adr_i) // synopsis full_case parallel_case
                        3'b000: wb_dat_o = prer[ 7:0];
                        3'b001: wb_dat_o = prer[15:8];
                        3'b010: wb_dat_o = ctr;
                        3'b011: wb_dat_o = rxr; // write is transmit register (txr)
                        3'b100: wb_dat_o = sr;  // write is command register (cr)
                        3'b101: wb_dat_o = txr;
                        3'b110: wb_dat_o = cr;
                endcase
        end
 
 
        // generate registers
        always@(posedge wb_clk_i or negedge rst_i)
                if (!rst_i)
                        begin
                                prer <= #1 16'h0;
                                ctr  <= #1  8'h0;
                                txr  <= #1  8'h0;
                                cr   <= #1  8'h0;
                        end
                else if (wb_rst_i)
                        begin
                                prer <= #1 16'h0;
                                ctr  <= #1  8'h0;
                                txr  <= #1  8'h0;
                                cr   <= #1  8'h0;
                        end
                else
                        if (wb_cyc_i && wb_stb_i && wb_we_i)
                                begin
                                        if (!wb_adr_i[2])
                                                case (wb_adr_i[1:0]) // synopsis full_case parallel_case
                                                        2'b00 : prer [ 7:0] <= #1 wb_dat_i;
                                                        2'b01 : prer [15:8] <= #1 wb_dat_i;
                                                        2'b10 : ctr         <= #1 wb_dat_i;
                                                        2'b11 : txr         <= #1 wb_dat_i;
                                                endcase
                                        else
                                                if (core_en && (wb_adr_i[1:0] == 2'b00) ) // only take new commands when i2c core enabled, pending commands are finished
                                                        cr <= #1 wb_dat_i;
                                end
                        else
                                begin
                                        if (done)
                                                cr[7:4] <= #1 4'h0; // clear command bits when done
 
                                        cr[2:1] <= #1 2'b00;  // reserved bits
                                        cr[0]   <= #1 cr[0] && irq_flag; // clear when irq_flag cleared
                                end
 
 
        // decode command register
        wire sta  = cr[7];
        wire sto  = cr[6];
        wire rd   = cr[5];
        wire wr   = cr[4];
        wire ack  = cr[3];
        wire iack = cr[0];
 
        // decode control register
        assign core_en = ctr[7];
 
        // hookup byte controller block
        i2c_master_byte_ctrl byte_controller (
                .clk(wb_clk_i),
                .rst(wb_rst_i),
                .nReset(rst_i),
                .ena(core_en),
                .clk_cnt(prer),
                .start(sta),
                .stop(sto),
                .read(rd),
                .write(wr),
                .ack_in(ack),
                .din(txr),
                .cmd_ack(done),
                .ack_out(irxack),
                .dout(rxr),
                .i2c_busy(i2c_busy),
                .scl_i(scl_pad_i),
                .scl_o(scl_pad_o),
                .scl_oen(scl_padoen_o),
                .sda_i(sda_pad_i),
                .sda_o(sda_pad_o),
                .sda_oen(sda_padoen_o)
        );
 
 
        // status register block + interrupt request signal
        always@(posedge wb_clk_i or negedge rst_i)
                if (!rst_i)
                        begin
                                rxack    <= #1 1'b0;
                                tip      <= #1 1'b0;
                                irq_flag <= #1 1'b0;
                        end
                else if (wb_rst_i)
                        begin
                                rxack    <= #1 1'b0;
                                tip      <= #1 1'b0;
                                irq_flag <= #1 1'b0;
                        end
                else
                        begin
                                rxack    <= #1 irxack;
                                tip      <= #1 (rd || wr);
                                irq_flag <= #1 (done || irq_flag) && !iack; // interrupt request flag is always generated
                        end
 
                // generate interrupt request signals
                always@(posedge wb_clk_i or negedge rst_i)
                        if (!rst_i)
                                wb_inta_o <= #1 1'b0;
                        else if (wb_rst_i)
                                wb_inta_o <= #1 1'b0;
                        else
                                wb_inta_o <= #1 irq_flag && ctr[6]; // interrupt signal is only generated when IEN (interrupt enable bit is set)
 
                // assign status register bits
                assign sr[7]   = rxack;
                assign sr[6]   = i2c_busy;
                assign sr[5:2] = 4'h0; // reserved
                assign sr[1]   = tip;
                assign sr[0]   = irq_flag;
 
endmodule
 
 
 
 
 
 
 
 
 

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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_top.v] - Blame information for rev 11

Line No.	Rev	Author	Line
1	10	rherveille	`//`
2			`// WISHBONE revB2 compiant I2C master core`
3			`//`
4			`// author: Richard Herveille`
5			`// rev. 0.1 26-08-2001. Iinitial Verilog release`
6			`//`
7
8			`include "timescale.v"
9			`include "i2c_master_defines.v"
10
11			`module i2c_master_top(`
12			`wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,`
13			`wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,`
14			`scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );`
15
16	11	rherveille	`// parameters`
17			`parameter ARST_LVL = 1'b0; // asynchronous reset level`
18
19	10	rherveille	`//`
20			`// inputs & outputs`
21			`//`
22
23			`// wishbone signals`
24			`input wb_clk_i; // master clock input`
25			`input wb_rst_i; // synchronous active high reset`
26			`input arst_i; // asynchronous reset`
27			`input [2:0] wb_adr_i; // lower address bits`
28			`input [7:0] wb_dat_i; // databus input`
29			`output [7:0] wb_dat_o; // databus output`
30			`reg [7:0] wb_dat_o;`
31			`input wb_we_i; // write enable input`
32			`input wb_stb_i; // stobe/core select signal`
33			`input wb_cyc_i; // valid bus cycle input`
34			`output wb_ack_o; // bus cycle acknowledge output`
35			`output wb_inta_o; // interrupt request signal output`
36			`reg wb_inta_o;`
37
38			`// I2C signals`
39			`// i2c clock line`
40			`input scl_pad_i; // SCL-line input`
41			`output scl_pad_o; // SCL-line output (always 1'b0)`
42			`output scl_padoen_o; // SCL-line output enable (active low)`
43			`// i2c data line`
44			`input sda_pad_i; // SDA-line input`
45			`output sda_pad_o; // SDA-line output (always 1'b0)`
46			`output sda_padoen_o; // SDA-line output enable (active low)`
47
48
49			`//`
50			`// variable declarations`
51			`//`
52
53			`// registers`
54			`reg [15:0] prer; // clock prescale register`
55			`reg [ 7:0] ctr; // control register`
56			`reg [ 7:0] txr; // transmit register`
57			`wire [ 7:0] rxr; // receive register`
58			`reg [ 7:0] cr; // command register`
59			`wire [ 7:0] sr; // status register`
60
61			`// done signal: command completed, clear command register`
62			`wire done;`
63
64			`// core enable signal`
65			`wire core_en;`
66
67			`// status register signals`
68			`wire irxack;`
69			`reg rxack; // received aknowledge from slave`
70			`reg tip; // transfer in progress`
71			`reg irq_flag; // interrupt pending flag`
72			`wire i2c_busy; // bus busy (start signal detected)`
73
74			`//`
75			`// module body`
76			`//`
77
78			`// generate internal reset`
79	11	rherveille	`wire rst_i = arst_i ^ ARST_LVL;`
80	10	rherveille
81			`// generate acknowledge output signal`
82			`assign wb_ack_o = wb_cyc_i && wb_stb_i; // because timing is always honored`
83
84			`// assign DAT_O`
85			`always@(wb_adr_i or prer or ctr or txr or cr or rxr or sr)`
86			`begin`
87			`case (wb_adr_i) // synopsis full_case parallel_case`
88			`3'b000: wb_dat_o = prer[ 7:0];`
89			`3'b001: wb_dat_o = prer[15:8];`
90			`3'b010: wb_dat_o = ctr;`
91			`3'b011: wb_dat_o = rxr; // write is transmit register (txr)`
92			`3'b100: wb_dat_o = sr; // write is command register (cr)`
93			`3'b101: wb_dat_o = txr;`
94			`3'b110: wb_dat_o = cr;`
95			`endcase`
96			`end`
97
98
99			`// generate registers`
100			`always@(posedge wb_clk_i or negedge rst_i)`
101			`if (!rst_i)`
102			`begin`
103			`prer <= #1 16'h0;`
104			`ctr <= #1 8'h0;`
105			`txr <= #1 8'h0;`
106			`cr <= #1 8'h0;`
107			`end`
108			`else if (wb_rst_i)`
109			`begin`
110			`prer <= #1 16'h0;`
111			`ctr <= #1 8'h0;`
112			`txr <= #1 8'h0;`
113			`cr <= #1 8'h0;`
114			`end`
115			`else`
116			`if (wb_cyc_i && wb_stb_i && wb_we_i)`
117			`begin`
118			`if (!wb_adr_i[2])`
119			`case (wb_adr_i[1:0]) // synopsis full_case parallel_case`
120			`2'b00 : prer [ 7:0] <= #1 wb_dat_i;`
121			`2'b01 : prer [15:8] <= #1 wb_dat_i;`
122			`2'b10 : ctr <= #1 wb_dat_i;`
123			`2'b11 : txr <= #1 wb_dat_i;`
124			`endcase`
125			`else`
126			`if (core_en && (wb_adr_i[1:0] == 2'b00) ) // only take new commands when i2c core enabled, pending commands are finished`
127			`cr <= #1 wb_dat_i;`
128			`end`
129			`else`
130			`begin`
131			`if (done)`
132			`cr[7:4] <= #1 4'h0; // clear command bits when done`
133
134			`cr[2:1] <= #1 2'b00; // reserved bits`
135			`cr[0] <= #1 cr[0] && irq_flag; // clear when irq_flag cleared`
136			`end`
137
138
139			`// decode command register`
140			`wire sta = cr[7];`
141			`wire sto = cr[6];`
142			`wire rd = cr[5];`
143			`wire wr = cr[4];`
144			`wire ack = cr[3];`
145			`wire iack = cr[0];`
146
147			`// decode control register`
148			`assign core_en = ctr[7];`
149
150			`// hookup byte controller block`
151			`i2c_master_byte_ctrl byte_controller (`
152			`.clk(wb_clk_i),`
153			`.rst(wb_rst_i),`
154			`.nReset(rst_i),`
155			`.ena(core_en),`
156			`.clk_cnt(prer),`
157			`.start(sta),`
158			`.stop(sto),`
159			`.read(rd),`
160			`.write(wr),`
161			`.ack_in(ack),`
162			`.din(txr),`
163			`.cmd_ack(done),`
164			`.ack_out(irxack),`
165			`.dout(rxr),`
166			`.i2c_busy(i2c_busy),`
167			`.scl_i(scl_pad_i),`
168			`.scl_o(scl_pad_o),`
169			`.scl_oen(scl_padoen_o),`
170			`.sda_i(sda_pad_i),`
171			`.sda_o(sda_pad_o),`
172			`.sda_oen(sda_padoen_o)`
173			`);`
174
175
176			`// status register block + interrupt request signal`
177			`always@(posedge wb_clk_i or negedge rst_i)`
178			`if (!rst_i)`
179			`begin`
180			`rxack <= #1 1'b0;`
181			`tip <= #1 1'b0;`
182			`irq_flag <= #1 1'b0;`
183			`end`
184			`else if (wb_rst_i)`
185			`begin`
186			`rxack <= #1 1'b0;`
187			`tip <= #1 1'b0;`
188			`irq_flag <= #1 1'b0;`
189			`end`
190			`else`
191			`begin`
192			`rxack <= #1 irxack;`
193			`tip <= #1 (rd \|\| wr);`
194			`irq_flag <= #1 (done \|\| irq_flag) && !iack; // interrupt request flag is always generated`
195			`end`
196
197			`// generate interrupt request signals`
198			`always@(posedge wb_clk_i or negedge rst_i)`
199			`if (!rst_i)`
200			`wb_inta_o <= #1 1'b0;`
201			`else if (wb_rst_i)`
202			`wb_inta_o <= #1 1'b0;`
203			`else`
204			`wb_inta_o <= #1 irq_flag && ctr[6]; // interrupt signal is only generated when IEN (interrupt enable bit is set)`
205
206			`// assign status register bits`
207			`assign sr[7] = rxack;`
208			`assign sr[6] = i2c_busy;`
209			`assign sr[5:2] = 4'h0; // reserved`
210			`assign sr[1] = tip;`
211			`assign sr[0] = irq_flag;`
212
213			`endmodule`
214
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222	11	rherveille