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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE revB.2 compliant I2C Master controller Top-level  ////
////                                                             ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: i2c_master_top.v,v 1.7 2002-12-26 15:02:32 rherveille Exp $
//
//  $Date: 2002-12-26 15:02:32 $
//  $Revision: 1.7 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.6  2002/11/30 22:24:40  rherveille
//               Cleaned up code
//
//               Revision 1.5  2001/11/10 10:52:55  rherveille
//               Changed PRER reset value from 0x0000 to 0xffff, conform specs.
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`include "i2c_master_defines.v"
 
module i2c_master_top(
        wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
        wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
        scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
 
        // parameters
        parameter ARST_LVL = 1'b0; // asynchronous reset level
 
        //
        // inputs & outputs
        //
 
        // wishbone signals
        input        wb_clk_i;     // master clock input
        input        wb_rst_i;     // synchronous active high reset
        input        arst_i;       // asynchronous reset
        input  [2:0] wb_adr_i;     // lower address bits
        input  [7:0] wb_dat_i;     // databus input
        output [7:0] wb_dat_o;     // databus output
        input        wb_we_i;      // write enable input
        input        wb_stb_i;     // stobe/core select signal
        input        wb_cyc_i;     // valid bus cycle input
        output       wb_ack_o;     // bus cycle acknowledge output
        output       wb_inta_o;    // interrupt request signal output
 
        reg [7:0] wb_dat_o;
        reg wb_ack_o;
        reg wb_inta_o;
 
        // I2C signals
        // i2c clock line
        input  scl_pad_i;       // SCL-line input
        output scl_pad_o;       // SCL-line output (always 1'b0)
        output scl_padoen_o;    // SCL-line output enable (active low)
 
        // i2c data line
        input  sda_pad_i;       // SDA-line input
        output sda_pad_o;       // SDA-line output (always 1'b0)
        output sda_padoen_o;    // SDA-line output enable (active low)
 
 
        //
        // variable declarations
        //
 
        // registers
        reg  [15:0] prer; // clock prescale register
        reg  [ 7:0] ctr;  // control register
        reg  [ 7:0] txr;  // transmit register
        wire [ 7:0] rxr;  // receive register
        reg  [ 7:0] cr;   // command register
        wire [ 7:0] sr;   // status register
 
        // done signal: command completed, clear command register
        wire done;
 
        // core enable signal
        wire core_en;
        wire ien;
 
        // status register signals
        wire irxack;
        reg  rxack;       // received aknowledge from slave
        reg  tip;         // transfer in progress
        reg  irq_flag;    // interrupt pending flag
        wire i2c_busy;    // bus busy (start signal detected)
        wire i2c_al;      // i2c bus arbitration lost
        reg  al;          // status register arbitration lost bit
 
        //
        // module body
        //
 
        // generate internal reset
        wire rst_i = arst_i ^ ARST_LVL;
 
        // generate wishbone signals
        wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
 
        // generate acknowledge output signal
        always @(posedge wb_clk_i)
          wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
 
        // assign DAT_O
        always @(posedge wb_clk_i)
        begin
          case (wb_adr_i) // synopsis full_case parallel_case
            3'b000: wb_dat_o = prer[ 7:0];
            3'b001: wb_dat_o = prer[15:8];
            3'b010: wb_dat_o = ctr;
            3'b011: wb_dat_o = rxr; // write is transmit register (txr)
            3'b100: wb_dat_o = sr;  // write is command register (cr)
            3'b101: wb_dat_o = txr;
            3'b110: wb_dat_o = cr;
            3'b111: wb_dat_o = 0;   // reserved
          endcase
        end
 
        // generate registers
        always @(posedge wb_clk_i or negedge rst_i)
          if (!rst_i)
            begin
                prer <= #1 16'hffff;
                ctr  <= #1  8'h0;
                txr  <= #1  8'h0;
                cr   <= #1  8'h0;
            end
          else if (wb_rst_i)
            begin
                prer <= #1 16'hffff;
                ctr  <= #1  8'h0;
                txr  <= #1  8'h0;
                cr   <= #1  8'h0;
            end
          else
            if (wb_wacc)
              case (wb_adr_i) // synopsis full_case parallel_case
                 3'b000 : prer [ 7:0] <= #1 wb_dat_i;
                 3'b001 : prer [15:8] <= #1 wb_dat_i;
                 3'b010 : ctr         <= #1 wb_dat_i;
                 3'b011 : txr         <= #1 wb_dat_i;
              endcase
 
        // generate command register (special case)
        always @(posedge wb_clk_i or negedge rst_i)
          if (~rst_i)
            cr <= #1 8'h0;
          else if (wb_rst_i)
            cr <= #1 8'h0;
          else if (wb_wacc)
            begin
                if (core_en & (wb_adr_i == 3'b100) )
                  cr <= #1 wb_dat_i;
            end
          else
            begin
                if (done | i2c_al)
                  cr[7:4] <= #1 4'h0;           // clear command bits when done
                                                // or when aribitration lost
                cr[2:1] <= #1 2'b0;             // reserved bits
                cr[0]   <= #1 cr[0] & irq_flag; // clear when irq_flag is cleared
            end
 
 
        // decode command register
        wire sta  = cr[7];
        wire sto  = cr[6];
        wire rd   = cr[5];
        wire wr   = cr[4];
        wire ack  = cr[3];
        wire iack = cr[0];
 
        // decode control register
        assign core_en = ctr[7];
        assign ien = ctr[6];
 
        // hookup byte controller block
        i2c_master_byte_ctrl byte_controller (
                .clk      ( wb_clk_i     ),
                .rst      ( wb_rst_i     ),
                .nReset   ( rst_i        ),
                .ena      ( core_en      ),
                .clk_cnt  ( prer         ),
                .start    ( sta          ),
                .stop     ( sto          ),
                .read     ( rd           ),
                .write    ( wr           ),
                .ack_in   ( ack          ),
                .din      ( txr          ),
                .cmd_ack  ( done         ),
                .ack_out  ( irxack       ),
                .dout     ( rxr          ),
                .i2c_busy ( i2c_busy     ),
                .i2c_al   ( i2c_al       ),
                .scl_i    ( scl_pad_i    ),
                .scl_o    ( scl_pad_o    ),
                .scl_oen  ( scl_padoen_o ),
                .sda_i    ( sda_pad_i    ),
                .sda_o    ( sda_pad_o    ),
                .sda_oen  ( sda_padoen_o )
        );
 
        // status register block + interrupt request signal
        always @(posedge wb_clk_i or negedge rst_i)
          if (!rst_i)
            begin
                al       <= #1 1'b0;
                rxack    <= #1 1'b0;
                tip      <= #1 1'b0;
                irq_flag <= #1 1'b0;
            end
          else if (wb_rst_i)
            begin
                al       <= #1 1'b0;
                rxack    <= #1 1'b0;
                tip      <= #1 1'b0;
                irq_flag <= #1 1'b0;
            end
          else
            begin
                al       <= #1 i2c_al | (al & ~sta);
                rxack    <= #1 irxack;
                tip      <= #1 (rd | wr);
                irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
            end
 
        // generate interrupt request signals
        always @(posedge wb_clk_i or negedge rst_i)
          if (!rst_i)
            wb_inta_o <= #1 1'b0;
          else if (wb_rst_i)
            wb_inta_o <= #1 1'b0;
          else
            wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
 
        // assign status register bits
        assign sr[7]   = rxack;
        assign sr[6]   = i2c_busy;
        assign sr[5]   = al;
        assign sr[4:2] = 3'h0; // reserved
        assign sr[1]   = tip;
        assign sr[0]   = irq_flag;
 
endmodule

Line No.	Rev	Author	Line
1	14	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	27	rherveille	`//// WISHBONE revB.2 compliant I2C Master controller Top-level ////`
4	14	rherveille	`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/i2c/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	10	rherveille	`//`
40	29	rherveille	`// $Id: i2c_master_top.v,v 1.7 2002-12-26 15:02:32 rherveille Exp $`
41	10	rherveille	`//`
42	29	rherveille	`// $Date: 2002-12-26 15:02:32 $`
43			`// $Revision: 1.7 $`
44	14	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47	10	rherveille	`//`
48	14	rherveille	`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	29	rherveille	`// Revision 1.6 2002/11/30 22:24:40 rherveille`
51			`// Cleaned up code`
52			`//`
53	27	rherveille	`// Revision 1.5 2001/11/10 10:52:55 rherveille`
54			`// Changed PRER reset value from 0x0000 to 0xffff, conform specs.`
55			`//`
56	10	rherveille
57	27	rherveille	`// synopsys translate_off`
58	10	rherveille	`include "timescale.v"
59	27	rherveille	`// synopsys translate_on`
60
61	10	rherveille	`include "i2c_master_defines.v"
62
63			`module i2c_master_top(`
64	29	rherveille	`wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,`
65	10	rherveille	`wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,`
66			`scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );`
67
68	11	rherveille	`// parameters`
69			`parameter ARST_LVL = 1'b0; // asynchronous reset level`
70
71	10	rherveille	`//`
72			`// inputs & outputs`
73			`//`
74
75			`// wishbone signals`
76			`input wb_clk_i; // master clock input`
77			`input wb_rst_i; // synchronous active high reset`
78			`input arst_i; // asynchronous reset`
79			`input [2:0] wb_adr_i; // lower address bits`
80			`input [7:0] wb_dat_i; // databus input`
81			`output [7:0] wb_dat_o; // databus output`
82			`input wb_we_i; // write enable input`
83			`input wb_stb_i; // stobe/core select signal`
84			`input wb_cyc_i; // valid bus cycle input`
85			`output wb_ack_o; // bus cycle acknowledge output`
86			`output wb_inta_o; // interrupt request signal output`
87	27	rherveille
88			`reg [7:0] wb_dat_o;`
89			`reg wb_ack_o;`
90	10	rherveille	`reg wb_inta_o;`
91
92			`// I2C signals`
93			`// i2c clock line`
94			`input scl_pad_i; // SCL-line input`
95			`output scl_pad_o; // SCL-line output (always 1'b0)`
96			`output scl_padoen_o; // SCL-line output enable (active low)`
97	27	rherveille
98	10	rherveille	`// i2c data line`
99			`input sda_pad_i; // SDA-line input`
100			`output sda_pad_o; // SDA-line output (always 1'b0)`
101			`output sda_padoen_o; // SDA-line output enable (active low)`
102
103
104			`//`
105			`// variable declarations`
106			`//`
107
108			`// registers`
109			`reg [15:0] prer; // clock prescale register`
110			`reg [ 7:0] ctr; // control register`
111			`reg [ 7:0] txr; // transmit register`
112			`wire [ 7:0] rxr; // receive register`
113			`reg [ 7:0] cr; // command register`
114			`wire [ 7:0] sr; // status register`
115
116			`// done signal: command completed, clear command register`
117			`wire done;`
118
119			`// core enable signal`
120			`wire core_en;`
121	13	rherveille	`wire ien;`
122	10	rherveille
123			`// status register signals`
124			`wire irxack;`
125			`reg rxack; // received aknowledge from slave`
126			`reg tip; // transfer in progress`
127			`reg irq_flag; // interrupt pending flag`
128			`wire i2c_busy; // bus busy (start signal detected)`
129	29	rherveille	`wire i2c_al; // i2c bus arbitration lost`
130			`reg al; // status register arbitration lost bit`
131	10	rherveille
132			`//`
133			`// module body`
134			`//`
135
136			`// generate internal reset`
137	11	rherveille	`wire rst_i = arst_i ^ ARST_LVL;`
138	27	rherveille
139	29	rherveille	`// generate wishbone signals`
140			`wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;`
141
142	10	rherveille	`// generate acknowledge output signal`
143	27	rherveille	`always @(posedge wb_clk_i)`
144			`wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored`
145	10	rherveille
146			`// assign DAT_O`
147	27	rherveille	`always @(posedge wb_clk_i)`
148	10	rherveille	`begin`
149	27	rherveille	`case (wb_adr_i) // synopsis full_case parallel_case`
150			`3'b000: wb_dat_o = prer[ 7:0];`
151			`3'b001: wb_dat_o = prer[15:8];`
152			`3'b010: wb_dat_o = ctr;`
153			`3'b011: wb_dat_o = rxr; // write is transmit register (txr)`
154			`3'b100: wb_dat_o = sr; // write is command register (cr)`
155			`3'b101: wb_dat_o = txr;`
156			`3'b110: wb_dat_o = cr;`
157			`3'b111: wb_dat_o = 0; // reserved`
158			`endcase`
159	10	rherveille	`end`
160
161			`// generate registers`
162	27	rherveille	`always @(posedge wb_clk_i or negedge rst_i)`
163			`if (!rst_i)`
164			`begin`
165			`prer <= #1 16'hffff;`
166			`ctr <= #1 8'h0;`
167			`txr <= #1 8'h0;`
168			`cr <= #1 8'h0;`
169			`end`
170			`else if (wb_rst_i)`
171			`begin`
172			`prer <= #1 16'hffff;`
173			`ctr <= #1 8'h0;`
174			`txr <= #1 8'h0;`
175			`cr <= #1 8'h0;`
176			`end`
177			`else`
178	29	rherveille	`if (wb_wacc)`
179			`case (wb_adr_i) // synopsis full_case parallel_case`
180			`3'b000 : prer [ 7:0] <= #1 wb_dat_i;`
181			`3'b001 : prer [15:8] <= #1 wb_dat_i;`
182			`3'b010 : ctr <= #1 wb_dat_i;`
183			`3'b011 : txr <= #1 wb_dat_i;`
184			`endcase`
185	10	rherveille
186	29	rherveille	`// generate command register (special case)`
187			`always @(posedge wb_clk_i or negedge rst_i)`
188			`if (~rst_i)`
189			`cr <= #1 8'h0;`
190			`else if (wb_rst_i)`
191			`cr <= #1 8'h0;`
192			`else if (wb_wacc)`
193			`begin`
194			`if (core_en & (wb_adr_i == 3'b100) )`
195			`cr <= #1 wb_dat_i;`
196			`end`
197			`else`
198			`begin`
199			`if (done \| i2c_al)`
200			`cr[7:4] <= #1 4'h0; // clear command bits when done`
201			`// or when aribitration lost`
202			`cr[2:1] <= #1 2'b0; // reserved bits`
203			`cr[0] <= #1 cr[0] & irq_flag; // clear when irq_flag is cleared`
204			`end`
205	10	rherveille
206
207			`// decode command register`
208			`wire sta = cr[7];`
209			`wire sto = cr[6];`
210			`wire rd = cr[5];`
211			`wire wr = cr[4];`
212			`wire ack = cr[3];`
213			`wire iack = cr[0];`
214
215			`// decode control register`
216			`assign core_en = ctr[7];`
217	13	rherveille	`assign ien = ctr[6];`
218	10	rherveille
219			`// hookup byte controller block`
220			`i2c_master_byte_ctrl byte_controller (`
221	27	rherveille	`.clk ( wb_clk_i ),`
222			`.rst ( wb_rst_i ),`
223			`.nReset ( rst_i ),`
224			`.ena ( core_en ),`
225			`.clk_cnt ( prer ),`
226			`.start ( sta ),`
227			`.stop ( sto ),`
228			`.read ( rd ),`
229			`.write ( wr ),`
230			`.ack_in ( ack ),`
231			`.din ( txr ),`
232			`.cmd_ack ( done ),`
233			`.ack_out ( irxack ),`
234			`.dout ( rxr ),`
235			`.i2c_busy ( i2c_busy ),`
236	29	rherveille	`.i2c_al ( i2c_al ),`
237	27	rherveille	`.scl_i ( scl_pad_i ),`
238			`.scl_o ( scl_pad_o ),`
239			`.scl_oen ( scl_padoen_o ),`
240			`.sda_i ( sda_pad_i ),`
241			`.sda_o ( sda_pad_o ),`
242			`.sda_oen ( sda_padoen_o )`
243	10	rherveille	`);`
244
245			`// status register block + interrupt request signal`
246	27	rherveille	`always @(posedge wb_clk_i or negedge rst_i)`
247			`if (!rst_i)`
248			`begin`
249	29	rherveille	`al <= #1 1'b0;`
250	27	rherveille	`rxack <= #1 1'b0;`
251			`tip <= #1 1'b0;`
252			`irq_flag <= #1 1'b0;`
253			`end`
254			`else if (wb_rst_i)`
255			`begin`
256	29	rherveille	`al <= #1 1'b0;`
257	27	rherveille	`rxack <= #1 1'b0;`
258			`tip <= #1 1'b0;`
259			`irq_flag <= #1 1'b0;`
260			`end`
261			`else`
262			`begin`
263	29	rherveille	`al <= #1 i2c_al \| (al & ~sta);`
264	27	rherveille	`rxack <= #1 irxack;`
265			`tip <= #1 (rd \| wr);`
266	29	rherveille	`irq_flag <= #1 (done \| i2c_al \| irq_flag) & ~iack; // interrupt request flag is always generated`
267	27	rherveille	`end`
268	10	rherveille
269	27	rherveille	`// generate interrupt request signals`
270			`always @(posedge wb_clk_i or negedge rst_i)`
271			`if (!rst_i)`
272			`wb_inta_o <= #1 1'b0;`
273			`else if (wb_rst_i)`
274			`wb_inta_o <= #1 1'b0;`
275			`else`
276			`wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)`
277	10	rherveille
278	27	rherveille	`// assign status register bits`
279			`assign sr[7] = rxack;`
280			`assign sr[6] = i2c_busy;`
281	29	rherveille	`assign sr[5] = al;`
282			`assign sr[4:2] = 3'h0; // reserved`
283	27	rherveille	`assign sr[1] = tip;`
284			`assign sr[0] = irq_flag;`
285	10	rherveille
286			`endmodule`

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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_top.v] - Blame information for rev 29