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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE revB.2 compliant I2C Master controller Top-level  ////
////                                                             ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: i2c_master_top.v,v 1.11 2005-02-27 09:26:24 rherveille Exp $
//
//  $Date: 2005-02-27 09:26:24 $
//  $Revision: 1.11 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.10  2003/09/01 10:34:38  rherveille
//               Fix a blocking vs. non-blocking error in the wb_dat output mux.
//
//               Revision 1.9  2003/01/09 16:44:45  rherveille
//               Fixed a bug in the Command Register declaration.
//
//               Revision 1.8  2002/12/26 16:05:12  rherveille
//               Small code simplifications
//
//               Revision 1.7  2002/12/26 15:02:32  rherveille
//               Core is now a Multimaster I2C controller
//
//               Revision 1.6  2002/11/30 22:24:40  rherveille
//               Cleaned up code
//
//               Revision 1.5  2001/11/10 10:52:55  rherveille
//               Changed PRER reset value from 0x0000 to 0xffff, conform specs.
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`include "i2c_master_defines.v"
 
module i2c_master_top(
        wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
        wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
        scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
 
        // parameters
        parameter ARST_LVL = 1'b0; // asynchronous reset level
 
        //
        // inputs & outputs
        //
 
        // wishbone signals
        input        wb_clk_i;     // master clock input
        input        wb_rst_i;     // synchronous active high reset
        input        arst_i;       // asynchronous reset
        input  [2:0] wb_adr_i;     // lower address bits
        input  [7:0] wb_dat_i;     // databus input
        output [7:0] wb_dat_o;     // databus output
        input        wb_we_i;      // write enable input
        input        wb_stb_i;     // stobe/core select signal
        input        wb_cyc_i;     // valid bus cycle input
        output       wb_ack_o;     // bus cycle acknowledge output
        output       wb_inta_o;    // interrupt request signal output
 
        reg [7:0] wb_dat_o;
        reg wb_ack_o;
        reg wb_inta_o;
 
        // I2C signals
        // i2c clock line
        input  scl_pad_i;       // SCL-line input
        output scl_pad_o;       // SCL-line output (always 1'b0)
        output scl_padoen_o;    // SCL-line output enable (active low)
 
        // i2c data line
        input  sda_pad_i;       // SDA-line input
        output sda_pad_o;       // SDA-line output (always 1'b0)
        output sda_padoen_o;    // SDA-line output enable (active low)
 
 
        //
        // variable declarations
        //
 
        // registers
        reg  [15:0] prer; // clock prescale register
        reg  [ 7:0] ctr;  // control register
        reg  [ 7:0] txr;  // transmit register
        wire [ 7:0] rxr;  // receive register
        reg  [ 7:0] cr;   // command register
        wire [ 7:0] sr;   // status register
 
        // done signal: command completed, clear command register
        wire done;
 
        // core enable signal
        wire core_en;
        wire ien;
 
        // status register signals
        wire irxack;
        reg  rxack;       // received aknowledge from slave
        reg  tip;         // transfer in progress
        reg  irq_flag;    // interrupt pending flag
        wire i2c_busy;    // bus busy (start signal detected)
        wire i2c_al;      // i2c bus arbitration lost
        reg  al;          // status register arbitration lost bit
 
        //
        // module body
        //
 
        // generate internal reset
        wire rst_i = arst_i ^ ARST_LVL;
 
        // generate wishbone signals
        wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
 
        // generate acknowledge output signal
        always @(posedge wb_clk_i)
          wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
 
        // assign DAT_O
        always @(posedge wb_clk_i)
        begin
          case (wb_adr_i) // synopsis parallel_case
            3'b000: wb_dat_o <= #1 prer[ 7:0];
            3'b001: wb_dat_o <= #1 prer[15:8];
            3'b010: wb_dat_o <= #1 ctr;
            3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
            3'b100: wb_dat_o <= #1 sr;  // write is command register (cr)
            3'b101: wb_dat_o <= #1 txr;
            3'b110: wb_dat_o <= #1 cr;
            3'b111: wb_dat_o <= #1 0;   // reserved
          endcase
        end
 
        // generate registers
        always @(posedge wb_clk_i or negedge rst_i)
          if (!rst_i)
            begin
                prer <= #1 16'hffff;
                ctr  <= #1  8'h0;
                txr  <= #1  8'h0;
            end
          else if (wb_rst_i)
            begin
                prer <= #1 16'hffff;
                ctr  <= #1  8'h0;
                txr  <= #1  8'h0;
            end
          else
            if (wb_wacc)
              case (wb_adr_i) // synopsis parallel_case
                 3'b000 : prer [ 7:0] <= #1 wb_dat_i;
                 3'b001 : prer [15:8] <= #1 wb_dat_i;
                 3'b010 : ctr         <= #1 wb_dat_i;
                 3'b011 : txr         <= #1 wb_dat_i;
                 default: ;
              endcase
 
        // generate command register (special case)
        always @(posedge wb_clk_i or negedge rst_i)
          if (~rst_i)
            cr <= #1 8'h0;
          else if (wb_rst_i)
            cr <= #1 8'h0;
          else if (wb_wacc)
            begin
                if (core_en & (wb_adr_i == 3'b100) )
                  cr <= #1 wb_dat_i;
            end
          else
            begin
                if (done | i2c_al)
                  cr[7:4] <= #1 4'h0;           // clear command bits when done
                                                // or when aribitration lost
                cr[2:1] <= #1 2'b0;             // reserved bits
                cr[0]   <= #1 2'b0;             // clear IRQ_ACK bit
            end
 
 
        // decode command register
        wire sta  = cr[7];
        wire sto  = cr[6];
        wire rd   = cr[5];
        wire wr   = cr[4];
        wire ack  = cr[3];
        wire iack = cr[0];
 
        // decode control register
        assign core_en = ctr[7];
        assign ien = ctr[6];
 
        // hookup byte controller block
        i2c_master_byte_ctrl byte_controller (
                .clk      ( wb_clk_i     ),
                .rst      ( wb_rst_i     ),
                .nReset   ( rst_i        ),
                .ena      ( core_en      ),
                .clk_cnt  ( prer         ),
                .start    ( sta          ),
                .stop     ( sto          ),
                .read     ( rd           ),
                .write    ( wr           ),
                .ack_in   ( ack          ),
                .din      ( txr          ),
                .cmd_ack  ( done         ),
                .ack_out  ( irxack       ),
                .dout     ( rxr          ),
                .i2c_busy ( i2c_busy     ),
                .i2c_al   ( i2c_al       ),
                .scl_i    ( scl_pad_i    ),
                .scl_o    ( scl_pad_o    ),
                .scl_oen  ( scl_padoen_o ),
                .sda_i    ( sda_pad_i    ),
                .sda_o    ( sda_pad_o    ),
                .sda_oen  ( sda_padoen_o )
        );
 
        // status register block + interrupt request signal
        always @(posedge wb_clk_i or negedge rst_i)
          if (!rst_i)
            begin
                al       <= #1 1'b0;
                rxack    <= #1 1'b0;
                tip      <= #1 1'b0;
                irq_flag <= #1 1'b0;
            end
          else if (wb_rst_i)
            begin
                al       <= #1 1'b0;
                rxack    <= #1 1'b0;
                tip      <= #1 1'b0;
                irq_flag <= #1 1'b0;
            end
          else
            begin
                al       <= #1 i2c_al | (al & ~sta);
                rxack    <= #1 irxack;
                tip      <= #1 (rd | wr);
                irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
            end
 
        // generate interrupt request signals
        always @(posedge wb_clk_i or negedge rst_i)
          if (!rst_i)
            wb_inta_o <= #1 1'b0;
          else if (wb_rst_i)
            wb_inta_o <= #1 1'b0;
          else
            wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
 
        // assign status register bits
        assign sr[7]   = rxack;
        assign sr[6]   = i2c_busy;
        assign sr[5]   = al;
        assign sr[4:2] = 3'h0; // reserved
        assign sr[1]   = tip;
        assign sr[0]   = irq_flag;
 
endmodule

Line No.	Rev	Author	Line
1	14	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	27	rherveille	`//// WISHBONE revB.2 compliant I2C Master controller Top-level ////`
4	14	rherveille	`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/i2c/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	10	rherveille	`//`
40	55	rherveille	`// $Id: i2c_master_top.v,v 1.11 2005-02-27 09:26:24 rherveille Exp $`
41	10	rherveille	`//`
42	55	rherveille	`// $Date: 2005-02-27 09:26:24 $`
43			`// $Revision: 1.11 $`
44	14	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47	10	rherveille	`//`
48	14	rherveille	`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	55	rherveille	`// Revision 1.10 2003/09/01 10:34:38 rherveille`
51			`// Fix a blocking vs. non-blocking error in the wb_dat output mux.`
52			`//`
53	40	rherveille	`// Revision 1.9 2003/01/09 16:44:45 rherveille`
54			`// Fixed a bug in the Command Register declaration.`
55			`//`
56	33	rherveille	`// Revision 1.8 2002/12/26 16:05:12 rherveille`
57			`// Small code simplifications`
58			`//`
59	30	rherveille	`// Revision 1.7 2002/12/26 15:02:32 rherveille`
60			`// Core is now a Multimaster I2C controller`
61			`//`
62	29	rherveille	`// Revision 1.6 2002/11/30 22:24:40 rherveille`
63			`// Cleaned up code`
64			`//`
65	27	rherveille	`// Revision 1.5 2001/11/10 10:52:55 rherveille`
66			`// Changed PRER reset value from 0x0000 to 0xffff, conform specs.`
67			`//`
68	10	rherveille
69	27	rherveille	`// synopsys translate_off`
70	10	rherveille	`include "timescale.v"
71	27	rherveille	`// synopsys translate_on`
72
73	10	rherveille	`include "i2c_master_defines.v"
74
75			`module i2c_master_top(`
76	29	rherveille	`wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,`
77	10	rherveille	`wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,`
78			`scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );`
79
80	11	rherveille	`// parameters`
81			`parameter ARST_LVL = 1'b0; // asynchronous reset level`
82
83	10	rherveille	`//`
84			`// inputs & outputs`
85			`//`
86
87			`// wishbone signals`
88			`input wb_clk_i; // master clock input`
89			`input wb_rst_i; // synchronous active high reset`
90			`input arst_i; // asynchronous reset`
91			`input [2:0] wb_adr_i; // lower address bits`
92			`input [7:0] wb_dat_i; // databus input`
93			`output [7:0] wb_dat_o; // databus output`
94			`input wb_we_i; // write enable input`
95			`input wb_stb_i; // stobe/core select signal`
96			`input wb_cyc_i; // valid bus cycle input`
97			`output wb_ack_o; // bus cycle acknowledge output`
98			`output wb_inta_o; // interrupt request signal output`
99	27	rherveille
100			`reg [7:0] wb_dat_o;`
101			`reg wb_ack_o;`
102	10	rherveille	`reg wb_inta_o;`
103
104			`// I2C signals`
105			`// i2c clock line`
106			`input scl_pad_i; // SCL-line input`
107			`output scl_pad_o; // SCL-line output (always 1'b0)`
108			`output scl_padoen_o; // SCL-line output enable (active low)`
109	27	rherveille
110	10	rherveille	`// i2c data line`
111			`input sda_pad_i; // SDA-line input`
112			`output sda_pad_o; // SDA-line output (always 1'b0)`
113			`output sda_padoen_o; // SDA-line output enable (active low)`
114
115
116			`//`
117			`// variable declarations`
118			`//`
119
120			`// registers`
121			`reg [15:0] prer; // clock prescale register`
122			`reg [ 7:0] ctr; // control register`
123			`reg [ 7:0] txr; // transmit register`
124			`wire [ 7:0] rxr; // receive register`
125			`reg [ 7:0] cr; // command register`
126			`wire [ 7:0] sr; // status register`
127
128			`// done signal: command completed, clear command register`
129			`wire done;`
130
131			`// core enable signal`
132			`wire core_en;`
133	13	rherveille	`wire ien;`
134	10	rherveille
135			`// status register signals`
136			`wire irxack;`
137			`reg rxack; // received aknowledge from slave`
138			`reg tip; // transfer in progress`
139			`reg irq_flag; // interrupt pending flag`
140			`wire i2c_busy; // bus busy (start signal detected)`
141	29	rherveille	`wire i2c_al; // i2c bus arbitration lost`
142			`reg al; // status register arbitration lost bit`
143	10	rherveille
144			`//`
145			`// module body`
146			`//`
147
148			`// generate internal reset`
149	11	rherveille	`wire rst_i = arst_i ^ ARST_LVL;`
150	27	rherveille
151	29	rherveille	`// generate wishbone signals`
152			`wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;`
153
154	10	rherveille	`// generate acknowledge output signal`
155	27	rherveille	`always @(posedge wb_clk_i)`
156			`wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored`
157	10	rherveille
158			`// assign DAT_O`
159	27	rherveille	`always @(posedge wb_clk_i)`
160	10	rherveille	`begin`
161	55	rherveille	`case (wb_adr_i) // synopsis parallel_case`
162	40	rherveille	`3'b000: wb_dat_o <= #1 prer[ 7:0];`
163			`3'b001: wb_dat_o <= #1 prer[15:8];`
164			`3'b010: wb_dat_o <= #1 ctr;`
165			`3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)`
166			`3'b100: wb_dat_o <= #1 sr; // write is command register (cr)`
167			`3'b101: wb_dat_o <= #1 txr;`
168			`3'b110: wb_dat_o <= #1 cr;`
169			`3'b111: wb_dat_o <= #1 0; // reserved`
170	27	rherveille	`endcase`
171	10	rherveille	`end`
172
173			`// generate registers`
174	27	rherveille	`always @(posedge wb_clk_i or negedge rst_i)`
175			`if (!rst_i)`
176			`begin`
177			`prer <= #1 16'hffff;`
178			`ctr <= #1 8'h0;`
179			`txr <= #1 8'h0;`
180			`end`
181			`else if (wb_rst_i)`
182			`begin`
183			`prer <= #1 16'hffff;`
184			`ctr <= #1 8'h0;`
185			`txr <= #1 8'h0;`
186			`end`
187			`else`
188	29	rherveille	`if (wb_wacc)`
189	55	rherveille	`case (wb_adr_i) // synopsis parallel_case`
190	29	rherveille	`3'b000 : prer [ 7:0] <= #1 wb_dat_i;`
191			`3'b001 : prer [15:8] <= #1 wb_dat_i;`
192			`3'b010 : ctr <= #1 wb_dat_i;`
193			`3'b011 : txr <= #1 wb_dat_i;`
194	55	rherveille	`default: ;`
195	29	rherveille	`endcase`
196	10	rherveille
197	29	rherveille	`// generate command register (special case)`
198			`always @(posedge wb_clk_i or negedge rst_i)`
199			`if (~rst_i)`
200			`cr <= #1 8'h0;`
201			`else if (wb_rst_i)`
202			`cr <= #1 8'h0;`
203			`else if (wb_wacc)`
204			`begin`
205			`if (core_en & (wb_adr_i == 3'b100) )`
206			`cr <= #1 wb_dat_i;`
207			`end`
208			`else`
209			`begin`
210			`if (done \| i2c_al)`
211			`cr[7:4] <= #1 4'h0; // clear command bits when done`
212			`// or when aribitration lost`
213			`cr[2:1] <= #1 2'b0; // reserved bits`
214	30	rherveille	`cr[0] <= #1 2'b0; // clear IRQ_ACK bit`
215	29	rherveille	`end`
216	10	rherveille
217
218			`// decode command register`
219			`wire sta = cr[7];`
220			`wire sto = cr[6];`
221			`wire rd = cr[5];`
222			`wire wr = cr[4];`
223			`wire ack = cr[3];`
224			`wire iack = cr[0];`
225
226			`// decode control register`
227			`assign core_en = ctr[7];`
228	13	rherveille	`assign ien = ctr[6];`
229	10	rherveille
230			`// hookup byte controller block`
231			`i2c_master_byte_ctrl byte_controller (`
232	27	rherveille	`.clk ( wb_clk_i ),`
233			`.rst ( wb_rst_i ),`
234			`.nReset ( rst_i ),`
235			`.ena ( core_en ),`
236			`.clk_cnt ( prer ),`
237			`.start ( sta ),`
238			`.stop ( sto ),`
239			`.read ( rd ),`
240			`.write ( wr ),`
241			`.ack_in ( ack ),`
242			`.din ( txr ),`
243			`.cmd_ack ( done ),`
244			`.ack_out ( irxack ),`
245			`.dout ( rxr ),`
246			`.i2c_busy ( i2c_busy ),`
247	29	rherveille	`.i2c_al ( i2c_al ),`
248	27	rherveille	`.scl_i ( scl_pad_i ),`
249			`.scl_o ( scl_pad_o ),`
250			`.scl_oen ( scl_padoen_o ),`
251			`.sda_i ( sda_pad_i ),`
252			`.sda_o ( sda_pad_o ),`
253			`.sda_oen ( sda_padoen_o )`
254	10	rherveille	`);`
255
256			`// status register block + interrupt request signal`
257	27	rherveille	`always @(posedge wb_clk_i or negedge rst_i)`
258			`if (!rst_i)`
259			`begin`
260	29	rherveille	`al <= #1 1'b0;`
261	27	rherveille	`rxack <= #1 1'b0;`
262			`tip <= #1 1'b0;`
263			`irq_flag <= #1 1'b0;`
264			`end`
265			`else if (wb_rst_i)`
266			`begin`
267	29	rherveille	`al <= #1 1'b0;`
268	27	rherveille	`rxack <= #1 1'b0;`
269			`tip <= #1 1'b0;`
270			`irq_flag <= #1 1'b0;`
271			`end`
272			`else`
273			`begin`
274	29	rherveille	`al <= #1 i2c_al \| (al & ~sta);`
275	27	rherveille	`rxack <= #1 irxack;`
276			`tip <= #1 (rd \| wr);`
277	29	rherveille	`irq_flag <= #1 (done \| i2c_al \| irq_flag) & ~iack; // interrupt request flag is always generated`
278	27	rherveille	`end`
279	10	rherveille
280	27	rherveille	`// generate interrupt request signals`
281			`always @(posedge wb_clk_i or negedge rst_i)`
282			`if (!rst_i)`
283			`wb_inta_o <= #1 1'b0;`
284			`else if (wb_rst_i)`
285			`wb_inta_o <= #1 1'b0;`
286			`else`
287			`wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)`
288	10	rherveille
289	27	rherveille	`// assign status register bits`
290			`assign sr[7] = rxack;`
291			`assign sr[6] = i2c_busy;`
292	29	rherveille	`assign sr[5] = al;`
293			`assign sr[4:2] = 3'h0; // reserved`
294	27	rherveille	`assign sr[1] = tip;`
295			`assign sr[0] = irq_flag;`
296	10	rherveille
297			`endmodule`

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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_top.v] - Blame information for rev 55