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rherveille |
---------------------------------------------------------------------
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---- ----
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---- WISHBONE revB2 compl. I2C Master Core; bit-controller ----
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---- ----
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---- ----
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---- Author: Richard Herveille ----
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---- richard@asics.ws ----
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---- www.asics.ws ----
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---- ----
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---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2000 Richard Herveille ----
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---- richard@asics.ws ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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-- CVS Log
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--
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-- $Id: i2c_master_bit_ctrl.vhd,v 1.1 2001-11-05 12:02:33 rherveille Exp $
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--
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-- $Date: 2001-11-05 12:02:33 $
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-- $Revision: 1.1 $
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-- $Author: rherveille $
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-- $Locker: $
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-- $State: Exp $
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--
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-- Change History:
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-- $Log: not supported by cvs2svn $
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--
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-------------------------------------
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-- Bit controller section
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------------------------------------
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--
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-- Translate simple commands into SCL/SDA transitions
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-- Each command has 5 states, A/B/C/D/idle
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--
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-- start: SCL ~~~~~~~~~~\____
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-- SDA ~~~~~~~~\______
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-- x | A | B | C | D | i
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--
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-- repstart SCL ____/~~~~\___
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-- SDA __/~~~\______
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-- x | A | B | C | D | i
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--
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-- stop SCL ____/~~~~~~~~
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-- SDA ==\____/~~~~~
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-- x | A | B | C | D | i
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--
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--- write SCL ____/~~~~\____
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-- SDA ==X=========X=
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-- x | A | B | C | D | i
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--
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--- read SCL ____/~~~~\____
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-- SDA XXXX=====XXXX
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-- x | A | B | C | D | i
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--
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-- Timing: Normal mode Fast mode
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-----------------------------------------------------------------
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-- Fscl 100KHz 400KHz
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-- Th_scl 4.0us 0.6us High period of SCL
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-- Tl_scl 4.7us 1.3us Low period of SCL
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-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
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-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
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-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity i2c_master_bit_ctrl is
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generic(
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Tcq : time := 1 ns
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);
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port (
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clk : in std_logic;
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rst : in std_logic;
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nReset : in std_logic;
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ena : in std_logic; -- core enable signal
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clk_cnt : in unsigned(15 downto 0); -- clock prescale value
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cmd : in std_logic_vector(3 downto 0);
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cmd_ack : out std_logic;
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busy : out std_logic;
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din : in std_logic;
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dout : out std_logic;
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-- i2c lines
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scl_i : in std_logic; -- i2c clock line input
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scl_o : out std_logic; -- i2c clock line output
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scl_oen : out std_logic; -- i2c clock line output enable, active low
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sda_i : in std_logic; -- i2c data line input
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sda_o : out std_logic; -- i2c data line output
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sda_oen : out std_logic -- i2c data line output enable, active low
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);
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end entity i2c_master_bit_ctrl;
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architecture structural of i2c_master_bit_ctrl is
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constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
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constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
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constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
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constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
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constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
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type states is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
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signal c_state : states;
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signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
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signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
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signal clk_en, slave_wait :std_logic; -- clock generation signals
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-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
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signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
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begin
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-- synchronize SCL and SDA inputs
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synch_scl_sda: process(clk)
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begin
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if (clk'event and clk = '1') then
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sSCL <= scl_i after Tcq;
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sSDA <= sda_i after Tcq;
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end if;
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end process synch_SCL_SDA;
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-- whenever the slave is not ready it can delay the cycle by pulling SCL low
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slave_wait <= iscl_oen and not sSCL;
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-- generate clk enable signal
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gen_clken: process(clk, nReset)
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begin
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if (nReset = '0') then
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cnt <= (others => '0') after Tcq;
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clk_en <= '1' after Tcq;
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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cnt <= (others => '0') after Tcq;
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clk_en <= '1' after Tcq;
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else
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if ( (cnt = 0) or (ena = '0') ) then
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clk_en <= '1' after Tcq;
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cnt <= clk_cnt after Tcq;
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else
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if (slave_wait = '0') then
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cnt <= cnt -1 after Tcq;
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end if;
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clk_en <= '0' after Tcq;
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end if;
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end if;
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end if;
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end process gen_clken;
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-- generate bus status controller
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bus_status_ctrl: block
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signal dSDA : std_logic;
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signal sta_condition : std_logic;
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signal sto_condition : std_logic;
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signal ibusy : std_logic;
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begin
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-- detect start condition => detect falling edge on SDA while SCL is high
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-- detect stop condition => detect rising edge on SDA while SCL is high
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detect_sta_sto: process(clk)
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begin
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if (clk'event and clk = '1') then
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dSDA <= sSDA; -- generate a delayed version of sSDA
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sta_condition <= (not sSDA and dSDA) and sSCL;
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sto_condition <= (sSDA and not dSDA) and sSCL;
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end if;
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end process detect_sta_sto;
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-- generate bus busy signal
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gen_busy: process(clk, nReset)
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begin
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if (nReset = '0') then
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ibusy <= '0' after Tcq;
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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ibusy <= '0' after Tcq;
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else
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ibusy <= (sta_condition or ibusy) and not sto_condition after Tcq;
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end if;
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end if;
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end process gen_busy;
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-- assign output
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busy <= ibusy;
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end block bus_status_ctrl;
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-- generate statemachine
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nxt_state_decoder : process (clk, nReset, c_state, cmd)
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variable nxt_state : states;
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variable icmd_ack, store_sda : std_logic;
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begin
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nxt_state := c_state;
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icmd_ack := '0'; -- default no acknowledge
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store_sda := '0';
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case (c_state) is
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-- idle
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when idle =>
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case cmd is
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when I2C_CMD_START =>
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nxt_state := start_a;
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when I2C_CMD_STOP =>
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nxt_state := stop_a;
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when I2C_CMD_WRITE =>
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nxt_state := wr_a;
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when I2C_CMD_READ =>
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nxt_state := rd_a;
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when others => -- NOP command
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nxt_state := idle;
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end case;
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-- start
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when start_a =>
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nxt_state := start_b;
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when start_b =>
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nxt_state := start_c;
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when start_c =>
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nxt_state := start_d;
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when start_d =>
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nxt_state := idle;
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icmd_ack := '1'; -- command completed
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-- stop
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when stop_a =>
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nxt_state := stop_b;
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when stop_b =>
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nxt_state := stop_c;
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when stop_c =>
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nxt_state := idle;
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icmd_ack := '1'; -- command completed
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-- read
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when rd_a =>
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nxt_state := rd_b;
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when rd_b =>
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nxt_state := rd_c;
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when rd_c =>
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nxt_state := rd_d;
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store_sda := '1';
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when rd_d =>
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nxt_state := idle;
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icmd_ack := '1'; -- command completed
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-- write
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when wr_a =>
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nxt_state := wr_b;
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when wr_b =>
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nxt_state := wr_c;
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when wr_c =>
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nxt_state := wr_d;
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when wr_d =>
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nxt_state := idle;
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icmd_ack := '1'; -- command completed
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end case;
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-- generate regs
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if (nReset = '0') then
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c_state <= idle after Tcq;
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cmd_ack <= '0' after Tcq;
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Dout <= '0' after Tcq;
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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c_state <= idle after Tcq;
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cmd_ack <= '0' after Tcq;
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Dout <= '0' after Tcq;
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else
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if (clk_en = '1') then
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c_state <= nxt_state after Tcq;
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if (store_sda = '1') then
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dout <= sSDA after Tcq;
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end if;
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end if;
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cmd_ack <= icmd_ack and clk_en;
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end if;
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end if;
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end process nxt_state_decoder;
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--
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-- convert states to SCL and SDA signals
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--
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output_decoder: process (clk, nReset, c_state, iscl_oen, isda_oen, din)
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variable iscl, isda : std_logic;
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begin
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case (c_state) is
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when idle =>
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iscl := iscl_oen; -- keep SCL in same state
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isda := isda_oen; -- keep SDA in same state
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-- start
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when start_a =>
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iscl := iscl_oen; -- keep SCL in same state (for repeated start)
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isda := '1'; -- set SDA high
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when start_b =>
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iscl := '1'; -- set SCL high
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isda := '1'; -- keep SDA high
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|
|
|
| 350 |
|
|
when start_c =>
|
| 351 |
|
|
iscl := '1'; -- keep SCL high
|
| 352 |
|
|
isda := '0'; -- sel SDA low
|
| 353 |
|
|
|
| 354 |
|
|
when start_d =>
|
| 355 |
|
|
iscl := '0'; -- set SCL low
|
| 356 |
|
|
isda := '0'; -- keep SDA low
|
| 357 |
|
|
|
| 358 |
|
|
-- stop
|
| 359 |
|
|
when stop_a =>
|
| 360 |
|
|
iscl := '0'; -- keep SCL disabled
|
| 361 |
|
|
isda := '0'; -- set SDA low
|
| 362 |
|
|
|
| 363 |
|
|
when stop_b =>
|
| 364 |
|
|
iscl := '1'; -- set SCL high
|
| 365 |
|
|
isda := '0'; -- keep SDA low
|
| 366 |
|
|
|
| 367 |
|
|
when stop_c =>
|
| 368 |
|
|
iscl := '1'; -- keep SCL high
|
| 369 |
|
|
isda := '1'; -- set SDA high
|
| 370 |
|
|
|
| 371 |
|
|
-- write
|
| 372 |
|
|
when wr_a =>
|
| 373 |
|
|
iscl := '0'; -- keep SCL low
|
| 374 |
|
|
isda := din; -- set SDA
|
| 375 |
|
|
|
| 376 |
|
|
when wr_b =>
|
| 377 |
|
|
iscl := '1'; -- set SCL high
|
| 378 |
|
|
isda := din; -- keep SDA
|
| 379 |
|
|
|
| 380 |
|
|
when wr_c =>
|
| 381 |
|
|
iscl := '1'; -- keep SCL high
|
| 382 |
|
|
isda := din; -- keep SDA
|
| 383 |
|
|
|
| 384 |
|
|
when wr_d =>
|
| 385 |
|
|
iscl := '0'; -- set SCL low
|
| 386 |
|
|
isda := din; -- keep SDA
|
| 387 |
|
|
|
| 388 |
|
|
-- read
|
| 389 |
|
|
when rd_a =>
|
| 390 |
|
|
iscl := '0'; -- keep SCL low
|
| 391 |
|
|
isda := '1'; -- tri-state SDA
|
| 392 |
|
|
|
| 393 |
|
|
when rd_b =>
|
| 394 |
|
|
iscl := '1'; -- set SCL high
|
| 395 |
|
|
isda := '1'; -- tri-state SDA
|
| 396 |
|
|
|
| 397 |
|
|
when rd_c =>
|
| 398 |
|
|
iscl := '1'; -- keep SCL high
|
| 399 |
|
|
isda := '1'; -- tri-state SDA
|
| 400 |
|
|
|
| 401 |
|
|
when rd_d =>
|
| 402 |
|
|
iscl := '0'; -- set SCL low
|
| 403 |
|
|
isda := '1'; -- tri-state SDA
|
| 404 |
|
|
end case;
|
| 405 |
|
|
|
| 406 |
|
|
-- generate registers
|
| 407 |
|
|
if (nReset = '0') then
|
| 408 |
|
|
iscl_oen <= '1' after Tcq;
|
| 409 |
|
|
isda_oen <= '1' after Tcq;
|
| 410 |
|
|
elsif (clk'event and clk = '1') then
|
| 411 |
|
|
if (rst = '1') then
|
| 412 |
|
|
iscl_oen <= '1' after Tcq;
|
| 413 |
|
|
isda_oen <= '1' after Tcq;
|
| 414 |
|
|
else
|
| 415 |
|
|
if (clk_en = '1') then
|
| 416 |
|
|
iscl_oen <= iscl after Tcq;
|
| 417 |
|
|
isda_oen <= isda after Tcq;
|
| 418 |
|
|
end if;
|
| 419 |
|
|
end if;
|
| 420 |
|
|
end if;
|
| 421 |
|
|
end process output_decoder;
|
| 422 |
|
|
|
| 423 |
|
|
-- assign outputs
|
| 424 |
|
|
scl_o <= '0';
|
| 425 |
|
|
scl_oen <= iscl_oen;
|
| 426 |
|
|
sda_o <= '0';
|
| 427 |
|
|
sda_oen <= isda_oen;
|
| 428 |
|
|
end architecture structural;
|
