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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_bit_ctrl.vhd] - Blame information for rev 24

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1 15 rherveille
---------------------------------------------------------------------
2
----                                                             ----
3
----  WISHBONE revB2 compl. I2C Master Core; bit-controller      ----
4
----                                                             ----
5
----                                                             ----
6
----  Author: Richard Herveille                                  ----
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----          richard@asics.ws                                   ----
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----          www.asics.ws                                       ----
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----                                                             ----
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----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
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----                                                             ----
12
---------------------------------------------------------------------
13
----                                                             ----
14
---- Copyright (C) 2000 Richard Herveille                        ----
15
----                    richard@asics.ws                         ----
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----                                                             ----
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---- This source file may be used and distributed without        ----
18
---- restriction provided that this copyright statement is not   ----
19
---- removed from the file and that any derivative work contains ----
20
---- the original copyright notice and the associated disclaimer.----
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----                                                             ----
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----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
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---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
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---- POSSIBILITY OF SUCH DAMAGE.                                 ----
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----                                                             ----
36
---------------------------------------------------------------------
37
 
38
--  CVS Log
39
--
40 24 rherveille
--  $Id: i2c_master_bit_ctrl.vhd,v 1.3 2002-10-30 18:09:53 rherveille Exp $
41 15 rherveille
--
42 24 rherveille
--  $Date: 2002-10-30 18:09:53 $
43
--  $Revision: 1.3 $
44 15 rherveille
--  $Author: rherveille $
45
--  $Locker:  $
46
--  $State: Exp $
47
--
48
-- Change History:
49
--               $Log: not supported by cvs2svn $
50 24 rherveille
--               Revision 1.2  2002/06/15 07:37:04  rherveille
51
--               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
52
--
53 22 rherveille
--               Revision 1.1  2001/11/05 12:02:33  rherveille
54
--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
55
--               Code updated, is now up-to-date to doc. rev.0.4.
56
--               Added headers.
57
--
58 15 rherveille
 
59
 
60
--
61
-------------------------------------
62
-- Bit controller section
63
------------------------------------
64
--
65
-- Translate simple commands into SCL/SDA transitions
66
-- Each command has 5 states, A/B/C/D/idle
67
--
68
-- start:       SCL     ~~~~~~~~~~\____
69
--      SDA     ~~~~~~~~\______
70
--               x | A | B | C | D | i
71
--
72
-- repstart     SCL     ____/~~~~\___
73
--      SDA     __/~~~\______
74
--               x | A | B | C | D | i
75
--
76
-- stop SCL     ____/~~~~~~~~
77
--      SDA     ==\____/~~~~~
78
--               x | A | B | C | D | i
79
--
80
--- write       SCL     ____/~~~~\____
81
--      SDA     ==X=========X=
82
--               x | A | B | C | D | i
83
--
84
--- read        SCL     ____/~~~~\____
85
--      SDA     XXXX=====XXXX
86
--               x | A | B | C | D | i
87
--
88
 
89 24 rherveille
-- Timing:      Normal mode     Fast mode
90 15 rherveille
-----------------------------------------------------------------
91 24 rherveille
-- Fscl         100KHz          400KHz
92
-- Th_scl       4.0us           0.6us   High period of SCL
93
-- Tl_scl       4.7us           1.3us   Low period of SCL
94
-- Tsu:sta      4.7us           0.6us   setup time for a repeated start condition
95
-- Tsu:sto      4.0us           0.6us   setup time for a stop conditon
96
-- Tbuf         4.7us           1.3us   Bus free time between a stop and start condition
97 15 rherveille
--
98
 
99
library ieee;
100
use ieee.std_logic_1164.all;
101
use ieee.std_logic_arith.all;
102
 
103
entity i2c_master_bit_ctrl is
104
        generic(
105
                Tcq : time := 1 ns
106
        );
107
        port (
108
                clk    : in std_logic;
109
                rst    : in std_logic;
110
                nReset : in std_logic;
111
                ena    : in std_logic;                          -- core enable signal
112
 
113
                clk_cnt : in unsigned(15 downto 0);              -- clock prescale value
114
 
115
                cmd     : in std_logic_vector(3 downto 0);
116
                cmd_ack : out std_logic;
117
                busy    : out std_logic;
118
 
119
                din  : in std_logic;
120
                dout : out std_logic;
121
 
122
                -- i2c lines
123
                scl_i   : in std_logic;  -- i2c clock line input
124
                scl_o   : out std_logic; -- i2c clock line output
125
                scl_oen : out std_logic; -- i2c clock line output enable, active low
126
                sda_i   : in std_logic;  -- i2c data line input
127
                sda_o   : out std_logic; -- i2c data line output
128
                sda_oen : out std_logic  -- i2c data line output enable, active low
129
        );
130
end entity i2c_master_bit_ctrl;
131
 
132
architecture structural of i2c_master_bit_ctrl is
133 22 rherveille
        constant I2C_CMD_NOP    : std_logic_vector(3 downto 0) := "0000";
134
        constant I2C_CMD_START  : std_logic_vector(3 downto 0) := "0001";
135
        constant I2C_CMD_STOP   : std_logic_vector(3 downto 0) := "0010";
136
        constant I2C_CMD_READ   : std_logic_vector(3 downto 0) := "0100";
137
        constant I2C_CMD_WRITE  : std_logic_vector(3 downto 0) := "1000";
138 15 rherveille
 
139 24 rherveille
        type states is (idle, start_a, start_b, start_c, start_d, start_e,
140
                        stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
141 15 rherveille
        signal c_state : states;
142
 
143 22 rherveille
        signal iscl_oen, isda_oen : std_logic;          -- internal I2C lines
144
        signal sSCL, sSDA         : std_logic;          -- synchronized SCL and SDA inputs
145
        signal dscl_oen           : std_logic;          -- delayed scl_oen signals
146 15 rherveille
 
147 22 rherveille
        signal clk_en, slave_wait :std_logic;           -- clock generation signals
148
--      signal cnt : unsigned(15 downto 0) := clk_cnt;  -- clock divider counter (simulation)
149 15 rherveille
        signal cnt : unsigned(15 downto 0);             -- clock divider counter (synthesis)
150
 
151
begin
152
        -- synchronize SCL and SDA inputs
153
        synch_scl_sda: process(clk)
154
        begin
155 24 rherveille
            if (clk'event and clk = '1') then
156
              sSCL <= scl_i after Tcq;
157
              sSDA <= sda_i after Tcq;
158
            end if;
159 15 rherveille
        end process synch_SCL_SDA;
160 24 rherveille
 
161 22 rherveille
        -- delay scl_oen
162
        process (clk)
163
        begin
164 24 rherveille
            if (clk'event and clk = '1') then
165
              dscl_oen <= iscl_oen after Tcq;
166
            end if;
167 22 rherveille
        end process;
168
 
169 15 rherveille
        -- whenever the slave is not ready it can delay the cycle by pulling SCL low
170 22 rherveille
        slave_wait <= dscl_oen and not sSCL;
171 15 rherveille
 
172
        -- generate clk enable signal
173
        gen_clken: process(clk, nReset)
174
        begin
175 24 rherveille
            if (nReset = '0') then
176
              cnt    <= (others => '0') after Tcq;
177
              clk_en <= '1' after Tcq;
178
            elsif (clk'event and clk = '1') then
179
              if (rst = '1') then
180
                cnt    <= (others => '0') after Tcq;
181
                clk_en <= '1' after Tcq;
182
              else
183
                if ( (cnt = 0) or (ena = '0') ) then
184
                  clk_en <= '1' after Tcq;
185
                  cnt    <= clk_cnt after Tcq;
186
                else
187
                  if (slave_wait = '0') then
188
                    cnt <= cnt -1 after Tcq;
189
                  end if;
190
                  clk_en <= '0' after Tcq;
191
                end if;
192
              end if;
193
            end if;
194 15 rherveille
        end process gen_clken;
195
 
196
 
197
        -- generate bus status controller
198
        bus_status_ctrl: block
199 24 rherveille
          signal dSDA : std_logic;
200
          signal sta_condition : std_logic;
201
          signal sto_condition : std_logic;
202 15 rherveille
 
203 24 rherveille
          signal ibusy : std_logic;
204 15 rherveille
        begin
205 24 rherveille
            -- detect start condition => detect falling edge on SDA while SCL is high
206
            -- detect stop condition  => detect rising edge on SDA while SCL is high
207
            detect_sta_sto: process(clk)
208
            begin
209
                if (clk'event and clk = '1') then
210
                  dSDA <= sSDA; -- generate a delayed version of sSDA
211 15 rherveille
 
212 24 rherveille
                  sta_condition <= (not sSDA and dSDA) and sSCL;
213
                  sto_condition <= (sSDA and not dSDA) and sSCL;
214
                end if;
215
            end process detect_sta_sto;
216 15 rherveille
 
217 24 rherveille
            -- generate bus busy signal
218
            gen_busy: process(clk, nReset)
219
            begin
220
                if (nReset = '0') then
221
                  ibusy <= '0' after Tcq;
222
                elsif (clk'event and clk = '1') then
223
                  if (rst = '1') then
224
                    ibusy <= '0' after Tcq;
225
                  else
226
                    ibusy <= (sta_condition or ibusy) and not sto_condition after Tcq;
227
                  end if;
228
                end if;
229
            end process gen_busy;
230 15 rherveille
 
231 24 rherveille
            -- assign output
232
            busy <= ibusy;
233 15 rherveille
        end block bus_status_ctrl;
234
 
235
 
236
        -- generate statemachine
237
        nxt_state_decoder : process (clk, nReset, c_state, cmd)
238 24 rherveille
          variable nxt_state : states;
239
          variable icmd_ack, store_sda : std_logic;
240 15 rherveille
        begin
241 24 rherveille
            nxt_state := c_state;
242 15 rherveille
 
243 24 rherveille
            icmd_ack := '0'; -- default no acknowledge
244 15 rherveille
 
245 24 rherveille
            store_sda := '0';
246 15 rherveille
 
247 24 rherveille
            case (c_state) is
248
              -- idle
249
              when idle =>
250
                case cmd is
251
                  when I2C_CMD_START =>
252
                    nxt_state := start_a;
253 15 rherveille
 
254 24 rherveille
                  when I2C_CMD_STOP =>
255
                    nxt_state := stop_a;
256 15 rherveille
 
257 24 rherveille
                  when I2C_CMD_WRITE =>
258
                    nxt_state := wr_a;
259 15 rherveille
 
260 24 rherveille
                  when I2C_CMD_READ =>
261
                    nxt_state := rd_a;
262 15 rherveille
 
263 24 rherveille
                  when others =>  -- NOP command
264
                    nxt_state := idle;
265
                end case;
266 15 rherveille
 
267 24 rherveille
              -- start
268
              when start_a =>
269
                nxt_state := start_b;
270 15 rherveille
 
271 24 rherveille
              when start_b =>
272
                nxt_state := start_c;
273 15 rherveille
 
274 24 rherveille
              when start_c =>
275
                nxt_state := start_d;
276 15 rherveille
 
277 24 rherveille
              when start_d =>
278
                nxt_state := start_e;
279 15 rherveille
 
280 24 rherveille
              when start_e =>
281
                nxt_state := idle;
282
                icmd_ack := '1'; -- command completed
283 15 rherveille
 
284 24 rherveille
              -- stop
285
              when stop_a =>
286
                nxt_state := stop_b;
287 15 rherveille
 
288 24 rherveille
              when stop_b =>
289
                nxt_state := stop_c;
290 15 rherveille
 
291 24 rherveille
              when stop_c =>
292
                nxt_state := stop_d;
293 15 rherveille
 
294 24 rherveille
              when stop_d =>
295
                nxt_state := idle;
296
                icmd_ack := '1'; -- command completed
297 15 rherveille
 
298 24 rherveille
              -- read
299
              when rd_a =>
300
                nxt_state := rd_b;
301 15 rherveille
 
302 24 rherveille
              when rd_b =>
303
                nxt_state := rd_c;
304 15 rherveille
 
305 24 rherveille
              when rd_c =>
306
                nxt_state := rd_d;
307
                store_sda := '1';
308 15 rherveille
 
309 24 rherveille
              when rd_d =>
310
                nxt_state := idle;
311
                icmd_ack := '1'; -- command completed
312 15 rherveille
 
313 24 rherveille
              -- write
314
              when wr_a =>
315
                nxt_state := wr_b;
316 15 rherveille
 
317 24 rherveille
              when wr_b =>
318
                nxt_state := wr_c;
319 15 rherveille
 
320 24 rherveille
              when wr_c =>
321
                nxt_state := wr_d;
322 15 rherveille
 
323 24 rherveille
              when wr_d =>
324
                nxt_state := idle;
325
                icmd_ack := '1'; -- command completed
326 15 rherveille
 
327 24 rherveille
            end case;
328 15 rherveille
 
329 24 rherveille
            -- generate regs
330
            if (nReset = '0') then
331
              c_state <= idle after Tcq;
332
              cmd_ack <= '0' after Tcq;
333
              Dout    <= '0' after Tcq;
334
            elsif (clk'event and clk = '1') then
335
              if (rst = '1') then
336
                c_state <= idle after Tcq;
337
                cmd_ack <= '0' after Tcq;
338
                Dout    <= '0' after Tcq;
339
              elsif (clk_en = '1') then
340
                c_state <= nxt_state after Tcq;
341 15 rherveille
 
342 24 rherveille
                if (store_sda = '1') then
343
                  dout <= sSDA after Tcq;
344
                end if;
345
              end if;
346
 
347
              cmd_ack <= icmd_ack and clk_en;
348
            end if;
349 15 rherveille
        end process nxt_state_decoder;
350
 
351
        --
352
        -- convert states to SCL and SDA signals
353
        --
354
        output_decoder: process (clk, nReset, c_state, iscl_oen, isda_oen, din)
355 24 rherveille
          variable iscl, isda : std_logic;
356 15 rherveille
        begin
357 24 rherveille
            case (c_state) is
358
              -- idle
359
              when idle =>
360
                iscl := iscl_oen; -- keep SCL in same state
361
                isda := isda_oen; -- keep SDA in same state
362 15 rherveille
 
363 24 rherveille
              -- start
364
              when start_a =>
365
                iscl := iscl_oen; -- keep SCL in same state (for repeated start)
366
                isda := '1';      -- set SDA high
367 15 rherveille
 
368 24 rherveille
              when start_b =>
369
                iscl := '1'; -- set SCL high
370
                isda := '1'; -- keep SDA high
371 15 rherveille
 
372 24 rherveille
              when start_c =>
373
                iscl := '1'; -- keep SCL high
374
                isda := '0'; -- set SDA low
375 15 rherveille
 
376 24 rherveille
              when start_d =>
377
                iscl := '1'; -- keep SCL high
378
                isda := '0'; -- keep SDA low
379 15 rherveille
 
380 24 rherveille
              when start_e =>
381
                iscl := '0'; -- set SCL low
382
                isda := '0'; -- keep SDA low
383 15 rherveille
 
384 24 rherveille
              -- stop
385
              when stop_a =>
386
                iscl := '0'; -- keep SCL disabled
387
                isda := '0'; -- set SDA low
388 15 rherveille
 
389 24 rherveille
              when stop_b =>
390
                 iscl := '1'; -- set SCL high
391
                 isda := '0'; -- keep SDA low
392 15 rherveille
 
393 24 rherveille
              when stop_c =>
394
                 iscl := '1'; -- keep SCL high
395
                 isda := '0'; -- keep SDA low
396 15 rherveille
 
397 24 rherveille
              when stop_d =>
398
                iscl := '1'; -- keep SCL high
399
                isda := '1'; -- set SDA high
400 15 rherveille
 
401 24 rherveille
              -- write
402
              when wr_a =>
403
                iscl := '0'; -- keep SCL low
404
                isda := din; -- set SDA
405 15 rherveille
 
406 24 rherveille
              when wr_b =>
407
                iscl := '1'; -- set SCL high
408
                isda := din; -- keep SDA
409 15 rherveille
 
410 24 rherveille
              when wr_c =>
411
                iscl := '1'; -- keep SCL high
412
                isda := din; -- keep SDA
413 15 rherveille
 
414 24 rherveille
              when wr_d =>
415
                iscl := '0'; -- set SCL low
416
                isda := din; -- keep SDA
417 15 rherveille
 
418 24 rherveille
              -- read
419
              when rd_a =>
420
                iscl := '0'; -- keep SCL low
421
                isda := '1'; -- tri-state SDA
422 15 rherveille
 
423 24 rherveille
              when rd_b =>
424
                iscl := '1'; -- set SCL high
425
                isda := '1'; -- tri-state SDA
426 15 rherveille
 
427 24 rherveille
              when rd_c =>
428
                iscl := '1'; -- keep SCL high
429
                isda := '1'; -- tri-state SDA
430
 
431
              when rd_d =>
432
                iscl := '0'; -- set SCL low
433
                isda := '1'; -- tri-state SDA
434
            end case;
435
 
436
            -- generate registers
437
            if (nReset = '0') then
438
              iscl_oen <= '1' after Tcq;
439
              isda_oen <= '1' after Tcq;
440
            elsif (clk'event and clk = '1') then
441
              if (rst = '1') then
442
                iscl_oen <= '1' after Tcq;
443
                isda_oen <= '1' after Tcq;
444
              elsif (clk_en = '1') then
445
                iscl_oen <= iscl after Tcq;
446
                isda_oen <= isda after Tcq;
447
              end if;
448
            end if;
449 15 rherveille
        end process output_decoder;
450
 
451
        -- assign outputs
452
        scl_o   <= '0';
453
        scl_oen <= iscl_oen;
454
        sda_o   <= '0';
455
        sda_oen <= isda_oen;
456
end architecture structural;

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