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---------------------------------------------------------------------
----                                                             ----
----  WISHBONE revB2 I2C Master Core; bit-controller             ----
----                                                             ----
----                                                             ----
----  Author: Richard Herveille                                  ----
----          richard@asics.ws                                   ----
----          www.asics.ws                                       ----
----                                                             ----
----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2000 Richard Herveille                        ----
----                    richard@asics.ws                         ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
---- POSSIBILITY OF SUCH DAMAGE.                                 ----
----                                                             ----
---------------------------------------------------------------------
 
--  CVS Log
--
--  $Id: i2c_master_bit_ctrl.vhd,v 1.8 2003-08-09 07:01:13 rherveille Exp $
--
--  $Date: 2003-08-09 07:01:13 $
--  $Revision: 1.8 $
--  $Author: rherveille $
--  $Locker:  $
--  $State: Exp $
--
-- Change History:
--               $Log: not supported by cvs2svn $
--               Revision 1.7  2003/02/05 00:06:02  rherveille
--               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
--               Revision 1.6  2003/02/01 02:03:06  rherveille
--               Fixed a few 'arbitration lost' bugs. VHDL version only.
--
--               Revision 1.5  2002/12/26 16:05:47  rherveille
--               Core is now a Multimaster I2C controller.
--
--               Revision 1.4  2002/11/30 22:24:37  rherveille
--               Cleaned up code
--
--               Revision 1.3  2002/10/30 18:09:53  rherveille
--               Fixed some reported minor start/stop generation timing issuess.
--
--               Revision 1.2  2002/06/15 07:37:04  rherveille
--               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
--               Revision 1.1  2001/11/05 12:02:33  rherveille
--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
--               Code updated, is now up-to-date to doc. rev.0.4.
--               Added headers.
--
 
 
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start:    SCL  ~~~~~~~~~~~~~~\____
--           SDA  XX/~~~~~~~\______
--                x | A | B | C | D | i
--
-- repstart  SCL  ______/~~~~~~~\___
--           SDA  __/~~~~~~~\______
--                x | A | B | C | D | i
--
-- stop      SCL  _______/~~~~~~~~~~~
--           SDA  ==\___________/~~~~~
--                x | A | B | C | D | i
--
--- write    SCL  ______/~~~~~~~\____
--           SDA  XXX===============XX
--                x | A | B | C | D | i
--
--- read     SCL  ______/~~~~~~~\____
--           SDA  XXXXXXX=XXXXXXXXXXX
--                x | A | B | C | D | i
--
 
-- Timing:      Normal mode     Fast mode
-----------------------------------------------------------------
-- Fscl         100KHz          400KHz
-- Th_scl       4.0us           0.6us   High period of SCL
-- Tl_scl       4.7us           1.3us   Low period of SCL
-- Tsu:sta      4.7us           0.6us   setup time for a repeated start condition
-- Tsu:sto      4.0us           0.6us   setup time for a stop conditon
-- Tbuf         4.7us           1.3us   Bus free time between a stop and start condition
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity i2c_master_bit_ctrl is
        port (
                clk    : in std_logic;
                rst    : in std_logic;
                nReset : in std_logic;
                ena    : in std_logic;                          -- core enable signal
 
                clk_cnt : in unsigned(15 downto 0);              -- clock prescale value
 
                cmd     : in std_logic_vector(3 downto 0);
                cmd_ack : out std_logic; -- command completed
                busy    : out std_logic; -- i2c bus busy
                al      : out std_logic; -- arbitration lost
 
                din  : in std_logic;
                dout : out std_logic;
 
                -- i2c lines
                scl_i   : in std_logic;  -- i2c clock line input
                scl_o   : out std_logic; -- i2c clock line output
                scl_oen : out std_logic; -- i2c clock line output enable, active low
                sda_i   : in std_logic;  -- i2c data line input
                sda_o   : out std_logic; -- i2c data line output
                sda_oen : out std_logic  -- i2c data line output enable, active low
        );
end entity i2c_master_bit_ctrl;
 
architecture structural of i2c_master_bit_ctrl is
        constant I2C_CMD_NOP    : std_logic_vector(3 downto 0) := "0000";
        constant I2C_CMD_START  : std_logic_vector(3 downto 0) := "0001";
        constant I2C_CMD_STOP   : std_logic_vector(3 downto 0) := "0010";
        constant I2C_CMD_READ   : std_logic_vector(3 downto 0) := "0100";
        constant I2C_CMD_WRITE  : std_logic_vector(3 downto 0) := "1000";
 
        type states is (idle, start_a, start_b, start_c, start_d, start_e,
                        stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
        signal c_state : states;
 
        signal iscl_oen, isda_oen : std_logic;          -- internal I2C lines
        signal sda_chk            : std_logic;          -- check SDA status (multi-master arbitration)
        signal dscl_oen           : std_logic;          -- delayed scl_oen signals
        signal sSCL, sSDA         : std_logic;          -- synchronized SCL and SDA inputs
        signal clk_en, slave_wait : std_logic;          -- clock generation signals
        signal ial                : std_logic;          -- internal arbitration lost signal
--      signal cnt : unsigned(15 downto 0) := clk_cnt;  -- clock divider counter (simulation)
        signal cnt : unsigned(15 downto 0);             -- clock divider counter (synthesis)
 
begin
        -- whenever the slave is not ready it can delay the cycle by pulling SCL low
        -- delay scl_oen
        process (clk)
        begin
            if (clk'event and clk = '1') then
              dscl_oen <= iscl_oen;
            end if;
        end process;
        slave_wait <= dscl_oen and not sSCL;
 
        -- generate clk enable signal
        gen_clken: process(clk, nReset)
        begin
            if (nReset = '0') then
              cnt    <= (others => '0');
              clk_en <= '1';
            elsif (clk'event and clk = '1') then
              if (rst = '1') then
                cnt    <= (others => '0');
                clk_en <= '1';
              else
                if ( (cnt = 0) or (ena = '0') ) then
                  if (slave_wait = '0') then
                    cnt    <= clk_cnt;
                    clk_en <= '1';
                  else
                    cnt    <= cnt;
                    clk_en <= '0';
                  end if;
                else
                  if (slave_wait = '0') then
                    cnt <= cnt -1;
                  end if;
                  clk_en <= '0';
                end if;
              end if;
            end if;
        end process gen_clken;
 
 
        -- generate bus status controller
        bus_status_ctrl: block
          signal dSCL, dSDA          : std_logic;  -- delayes sSCL and sSDA
          signal sta_condition       : std_logic;  -- start detected
          signal sto_condition       : std_logic;  -- stop detected
          signal cmd_stop            : std_logic;  -- STOP command
          signal ibusy               : std_logic;  -- internal busy signal
        begin
            -- synchronize SCL and SDA inputs
            synch_scl_sda: process(clk, nReset)
            begin
                if (nReset = '0') then
                  sSCL <= '1';
                  sSDA <= '1';
 
                  dSCL <= '1';
                  dSDA <= '1';
                elsif (clk'event and clk = '1') then
                  if (rst = '1') then
                    sSCL <= '1';
                    sSDA <= '1';
 
                    dSCL <= '1';
                    dSDA <= '1';
                  else
                    sSCL <= scl_i;
                    sSDA <= sda_i;
 
                    dSCL <= sSCL;
                    dSDA <= sSDA;
                  end if;
                end if;
            end process synch_SCL_SDA;
 
            -- detect start condition => detect falling edge on SDA while SCL is high
            -- detect stop condition  => detect rising edge on SDA while SCL is high
            detect_sta_sto: process(clk, nReset)
            begin
                if (nReset = '0') then
                  sta_condition <= '0';
                  sto_condition <= '0';
                elsif (clk'event and clk = '1') then
                  if (rst = '1') then
                    sta_condition <= '0';
                    sto_condition <= '0';
                  else
                    sta_condition <= (not sSDA and dSDA) and sSCL;
                    sto_condition <= (sSDA and not dSDA) and sSCL;
                  end if;
                end if;
            end process detect_sta_sto;
 
            -- generate i2c-bus busy signal
            gen_busy: process(clk, nReset)
            begin
                if (nReset = '0') then
                  ibusy <= '0';
                elsif (clk'event and clk = '1') then
                  if (rst = '1') then
                    ibusy <= '0';
                  else
                    ibusy <= (sta_condition or ibusy) and not sto_condition;
                  end if;
                end if;
            end process gen_busy;
            busy <= ibusy;
 
 
            -- generate arbitration lost signal
            gen_al: process(clk, nReset)
            begin
              if (nReset = '0') then
                cmd_stop  <= '0';
                ial       <= '0';
              elsif (clk'event and clk = '1') then
                if (rst = '1') then
                  cmd_stop  <= '0';
                  ial       <= '0';
                else
                  if (clk_en = '1') then
                    if (cmd = I2C_CMD_STOP) then
                      cmd_stop <= '1';
                    else
                      cmd_stop <= '0';
                    end if;
 
                  ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
                end if;
              end if;
            end process gen_al;
            al <= ial;
 
            -- generate dout signal, store dout on rising edge of SCL
            gen_dout: process(clk)
            begin
              if (clk'event and clk = '1') then
                if (sSCL = '1' and dSCL = '0') then
                  dout <= sSDA;
                end if;
              end if;
            end process gen_dout;
        end block bus_status_ctrl;
 
 
        -- generate statemachine
        nxt_state_decoder : process (clk, nReset, c_state, cmd)
        begin
            if (nReset = '0') then
              c_state  <= idle;
              cmd_ack  <= '0';
              iscl_oen <= '1';
              isda_oen <= '1';
              sda_chk  <= '0';
            elsif (clk'event and clk = '1') then
              if (rst = '1' or ial = '1') then
                c_state  <= idle;
                cmd_ack  <= '0';
                iscl_oen <= '1';
                isda_oen <= '1';
                sda_chk  <= '0';
              else
                cmd_ack <= '0'; -- default no acknowledge
 
                if (clk_en = '1') then
                  case (c_state) is
                     -- idle
                     when idle =>
                        case cmd is
                          when I2C_CMD_START => c_state <= start_a;
                          when I2C_CMD_STOP  => c_state <= stop_a;
                          when I2C_CMD_WRITE => c_state <= wr_a;
                          when I2C_CMD_READ  => c_state <= rd_a;
                          when others        => c_state <= idle; -- NOP command
                        end case;
 
                        iscl_oen <= iscl_oen; -- keep SCL in same state
                        isda_oen <= isda_oen; -- keep SDA in same state
                        sda_chk  <= '0';      -- don't check SDA
 
                     -- start
                     when start_a =>
                        c_state  <= start_b;
                        iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
                        isda_oen <= '1';      -- set SDA high
                        sda_chk  <= '0';      -- don't check SDA
 
                     when start_b =>
                        c_state  <= start_c;
                        iscl_oen <= '1'; -- set SCL high
                        isda_oen <= '1'; -- keep SDA high
                        sda_chk  <= '0'; -- don't check SDA
 
                     when start_c =>
                        c_state  <= start_d;
                        iscl_oen <= '1'; -- keep SCL high
                        isda_oen <= '0'; -- set SDA low
                        sda_chk  <= '0'; -- don't check SDA
 
                     when start_d =>
                        c_state  <= start_e;
                        iscl_oen <= '1'; -- keep SCL high
                        isda_oen <= '0'; -- keep SDA low
                        sda_chk  <= '0'; -- don't check SDA
 
                     when start_e =>
                        c_state  <= idle;
                        cmd_ack  <= '1'; -- command completed
                        iscl_oen <= '0'; -- set SCL low
                        isda_oen <= '0'; -- keep SDA low
                        sda_chk  <= '0'; -- don't check SDA
 
                     -- stop
                     when stop_a =>
                        c_state  <= stop_b;
                        iscl_oen <= '0'; -- keep SCL low
                        isda_oen <= '0'; -- set SDA low
                        sda_chk  <= '0'; -- don't check SDA
 
                     when stop_b =>
                        c_state  <= stop_c;
                        iscl_oen <= '1'; -- set SCL high
                        isda_oen <= '0'; -- keep SDA low
                        sda_chk  <= '0'; -- don't check SDA
 
                     when stop_c =>
                        c_state  <= stop_d;
                        iscl_oen <= '1'; -- keep SCL high
                        isda_oen <= '0'; -- keep SDA low
                        sda_chk  <= '0'; -- don't check SDA
 
                     when stop_d =>
                        c_state  <= idle;
                        cmd_ack  <= '1'; -- command completed
                        iscl_oen <= '1'; -- keep SCL high
                        isda_oen <= '1'; -- set SDA high
                        sda_chk  <= '0'; -- don't check SDA
 
                     -- read
                     when rd_a =>
                        c_state  <= rd_b;
                        iscl_oen <= '0'; -- keep SCL low
                        isda_oen <= '1'; -- tri-state SDA
                        sda_chk  <= '0'; -- don't check SDA
 
                     when rd_b =>
                        c_state  <= rd_c;
                        iscl_oen <= '1'; -- set SCL high
                        isda_oen <= '1'; -- tri-state SDA
                        sda_chk  <= '0'; -- don't check SDA
 
                     when rd_c =>
                        c_state  <= rd_d;
                        iscl_oen <= '1'; -- keep SCL high
                        isda_oen <= '1'; -- tri-state SDA
                        sda_chk  <= '0'; -- don't check SDA
 
                     when rd_d =>
                        c_state  <= idle;
                        cmd_ack  <= '1'; -- command completed
                        iscl_oen <= '0'; -- set SCL low
                        isda_oen <= '1'; -- tri-state SDA
                        sda_chk  <= '0'; -- don't check SDA
 
                     -- write
                     when wr_a =>
                        c_state  <= wr_b;
                        iscl_oen <= '0'; -- keep SCL low
                        isda_oen <= din; -- set SDA
                        sda_chk  <= '0'; -- don't check SDA (SCL low)
 
                     when wr_b =>
                        c_state  <= wr_c;
                        iscl_oen <= '1'; -- set SCL high
                        isda_oen <= din; -- keep SDA
                        sda_chk  <= '1'; -- check SDA
 
                     when wr_c =>
                        c_state  <= wr_d;
                        iscl_oen <= '1'; -- keep SCL high
                        isda_oen <= din; -- keep SDA
                        sda_chk  <= '1'; -- check SDA
 
                     when wr_d =>
                        c_state  <= idle;
                        cmd_ack  <= '1'; -- command completed
                        iscl_oen <= '0'; -- set SCL low
                        isda_oen <= din; -- keep SDA
                        sda_chk  <= '0'; -- don't check SDA (SCL low)
 
                     when others =>
 
                  end case;
                end if;
              end if;
            end if;
        end process nxt_state_decoder;
 
 
        -- assign outputs
        scl_o   <= '0';
        scl_oen <= iscl_oen;
        sda_o   <= '0';
        sda_oen <= isda_oen;
end architecture structural;
 

Line No.	Rev	Author	Line
1	15	rherveille	`---------------------------------------------------------------------`
2			`---- ----`
3	27	rherveille	`---- WISHBONE revB2 I2C Master Core; bit-controller ----`
4	15	rherveille	`---- ----`
5			`---- ----`
6			`---- Author: Richard Herveille ----`
7			`---- richard@asics.ws ----`
8			`---- www.asics.ws ----`
9			`---- ----`
10			`---- Downloaded from: http://www.opencores.org/projects/i2c/ ----`
11			`---- ----`
12			`---------------------------------------------------------------------`
13			`---- ----`
14			`---- Copyright (C) 2000 Richard Herveille ----`
15			`---- richard@asics.ws ----`
16			`---- ----`
17			`---- This source file may be used and distributed without ----`
18			`---- restriction provided that this copyright statement is not ----`
19			`---- removed from the file and that any derivative work contains ----`
20			`---- the original copyright notice and the associated disclaimer.----`
21			`---- ----`
22			---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
23			`---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----`
24			`---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----`
25			`---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----`
26			`---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
27			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----`
28			`---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----`
29			`---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----`
30			`---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----`
31			`---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
32			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----`
33			`---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----`
34			`---- POSSIBILITY OF SUCH DAMAGE. ----`
35			`---- ----`
36			`---------------------------------------------------------------------`
37
38			`-- CVS Log`
39			`--`
40	38	rherveille	`-- $Id: i2c_master_bit_ctrl.vhd,v 1.8 2003-08-09 07:01:13 rherveille Exp $`
41	15	rherveille	`--`
42	38	rherveille	`-- $Date: 2003-08-09 07:01:13 $`
43			`-- $Revision: 1.8 $`
44	15	rherveille	`-- $Author: rherveille $`
45			`-- $Locker: $`
46			`-- $State: Exp $`
47			`--`
48			`-- Change History:`
49			`-- $Log: not supported by cvs2svn $`
50	38	rherveille	`-- Revision 1.7 2003/02/05 00:06:02 rherveille`
51			`-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.`
52			`--`
53	35	rherveille	`-- Revision 1.6 2003/02/01 02:03:06 rherveille`
54			`-- Fixed a few 'arbitration lost' bugs. VHDL version only.`
55			`--`
56	34	rherveille	`-- Revision 1.5 2002/12/26 16:05:47 rherveille`
57			`-- Core is now a Multimaster I2C controller.`
58			`--`
59	31	rherveille	`-- Revision 1.4 2002/11/30 22:24:37 rherveille`
60			`-- Cleaned up code`
61			`--`
62	27	rherveille	`-- Revision 1.3 2002/10/30 18:09:53 rherveille`
63			`-- Fixed some reported minor start/stop generation timing issuess.`
64			`--`
65	24	rherveille	`-- Revision 1.2 2002/06/15 07:37:04 rherveille`
66			`-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.`
67			`--`
68	22	rherveille	`-- Revision 1.1 2001/11/05 12:02:33 rherveille`
69			`-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.`
70			`-- Code updated, is now up-to-date to doc. rev.0.4.`
71			`-- Added headers.`
72			`--`
73	15	rherveille
74
75			`--`
76			`-------------------------------------`
77			`-- Bit controller section`
78			`------------------------------------`
79			`--`
80			`-- Translate simple commands into SCL/SDA transitions`
81			`-- Each command has 5 states, A/B/C/D/idle`
82			`--`
83	31	rherveille	`-- start: SCL ~~~~~~~~~~~~~~\____`
84			`-- SDA XX/~~~~~~~\______`
85			`-- x \| A \| B \| C \| D \| i`
86	15	rherveille	`--`
87	31	rherveille	`-- repstart SCL ______/~~~~~~~\___`
88			`-- SDA __/~~~~~~~\______`
89			`-- x \| A \| B \| C \| D \| i`
90	15	rherveille	`--`
91	31	rherveille	`-- stop SCL _______/~~~~~~~~~~~`
92			`-- SDA ==\___________/~~~~~`
93			`-- x \| A \| B \| C \| D \| i`
94	15	rherveille	`--`
95	31	rherveille	`--- write SCL ______/~~~~~~~\____`
96			`-- SDA XXX===============XX`
97			`-- x \| A \| B \| C \| D \| i`
98	15	rherveille	`--`
99	31	rherveille	`--- read SCL ______/~~~~~~~\____`
100			`-- SDA XXXXXXX=XXXXXXXXXXX`
101			`-- x \| A \| B \| C \| D \| i`
102	15	rherveille	`--`
103
104	24	rherveille	`-- Timing: Normal mode Fast mode`
105	15	rherveille	`-----------------------------------------------------------------`
106	24	rherveille	`-- Fscl 100KHz 400KHz`
107			`-- Th_scl 4.0us 0.6us High period of SCL`
108			`-- Tl_scl 4.7us 1.3us Low period of SCL`
109			`-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition`
110			`-- Tsu:sto 4.0us 0.6us setup time for a stop conditon`
111			`-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition`
112	15	rherveille	`--`
113
114			`library ieee;`
115			`use ieee.std_logic_1164.all;`
116			`use ieee.std_logic_arith.all;`
117
118			`entity i2c_master_bit_ctrl is`
119			`port (`
120			`clk : in std_logic;`
121			`rst : in std_logic;`
122			`nReset : in std_logic;`
123			`ena : in std_logic; -- core enable signal`
124
125			`clk_cnt : in unsigned(15 downto 0); -- clock prescale value`
126
127			`cmd : in std_logic_vector(3 downto 0);`
128	31	rherveille	`cmd_ack : out std_logic; -- command completed`
129			`busy : out std_logic; -- i2c bus busy`
130			`al : out std_logic; -- arbitration lost`
131	15	rherveille
132			`din : in std_logic;`
133			`dout : out std_logic;`
134
135			`-- i2c lines`
136			`scl_i : in std_logic; -- i2c clock line input`
137			`scl_o : out std_logic; -- i2c clock line output`
138			`scl_oen : out std_logic; -- i2c clock line output enable, active low`
139			`sda_i : in std_logic; -- i2c data line input`
140			`sda_o : out std_logic; -- i2c data line output`
141			`sda_oen : out std_logic -- i2c data line output enable, active low`
142			`);`
143			`end entity i2c_master_bit_ctrl;`
144
145			`architecture structural of i2c_master_bit_ctrl is`
146	22	rherveille	`constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";`
147			`constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";`
148			`constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";`
149			`constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";`
150			`constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";`
151	15	rherveille
152	27	rherveille	`type states is (idle, start_a, start_b, start_c, start_d, start_e,`
153	24	rherveille	`stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);`
154	15	rherveille	`signal c_state : states;`
155
156	22	rherveille	`signal iscl_oen, isda_oen : std_logic; -- internal I2C lines`
157	31	rherveille	`signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)`
158			`signal dscl_oen : std_logic; -- delayed scl_oen signals`
159	22	rherveille	`signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs`
160	34	rherveille	`signal clk_en, slave_wait : std_logic; -- clock generation signals`
161			`signal ial : std_logic; -- internal arbitration lost signal`
162	22	rherveille	`-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)`
163	15	rherveille	`signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)`
164
165			`begin`
166	31	rherveille	`-- whenever the slave is not ready it can delay the cycle by pulling SCL low`
167	22	rherveille	`-- delay scl_oen`
168			`process (clk)`
169			`begin`
170	24	rherveille	`if (clk'event and clk = '1') then`
171	27	rherveille	`dscl_oen <= iscl_oen;`
172	24	rherveille	`end if;`
173	22	rherveille	`end process;`
174			`slave_wait <= dscl_oen and not sSCL;`
175	15	rherveille
176			`-- generate clk enable signal`
177			`gen_clken: process(clk, nReset)`
178			`begin`
179	24	rherveille	`if (nReset = '0') then`
180	27	rherveille	`cnt <= (others => '0');`
181			`clk_en <= '1';`
182	24	rherveille	`elsif (clk'event and clk = '1') then`
183			`if (rst = '1') then`
184	27	rherveille	`cnt <= (others => '0');`
185			`clk_en <= '1';`
186	24	rherveille	`else`
187			`if ( (cnt = 0) or (ena = '0') ) then`
188	31	rherveille	`if (slave_wait = '0') then`
189			`cnt <= clk_cnt;`
190			`clk_en <= '1';`
191			`else`
192			`cnt <= cnt;`
193			`clk_en <= '0';`
194			`end if;`
195	24	rherveille	`else`
196			`if (slave_wait = '0') then`
197	27	rherveille	`cnt <= cnt -1;`
198	24	rherveille	`end if;`
199	27	rherveille	`clk_en <= '0';`
200	24	rherveille	`end if;`
201			`end if;`
202			`end if;`
203	15	rherveille	`end process gen_clken;`
204
205
206			`-- generate bus status controller`
207			`bus_status_ctrl: block`
208	31	rherveille	`signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA`
209			`signal sta_condition : std_logic; -- start detected`
210			`signal sto_condition : std_logic; -- stop detected`
211	38	rherveille	`signal cmd_stop : std_logic; -- STOP command`
212	31	rherveille	`signal ibusy : std_logic; -- internal busy signal`
213			`begin`
214			`-- synchronize SCL and SDA inputs`
215	35	rherveille	`synch_scl_sda: process(clk, nReset)`
216	31	rherveille	`begin`
217	35	rherveille	`if (nReset = '0') then`
218			`sSCL <= '1';`
219			`sSDA <= '1';`
220	15	rherveille
221	35	rherveille	`dSCL <= '1';`
222			`dSDA <= '1';`
223			`elsif (clk'event and clk = '1') then`
224			`if (rst = '1') then`
225			`sSCL <= '1';`
226			`sSDA <= '1';`
227
228			`dSCL <= '1';`
229			`dSDA <= '1';`
230			`else`
231			`sSCL <= scl_i;`
232			`sSDA <= sda_i;`
233
234			`dSCL <= sSCL;`
235			`dSDA <= sSDA;`
236			`end if;`
237	31	rherveille	`end if;`
238			`end process synch_SCL_SDA;`
239
240	24	rherveille	`-- detect start condition => detect falling edge on SDA while SCL is high`
241			`-- detect stop condition => detect rising edge on SDA while SCL is high`
242	35	rherveille	`detect_sta_sto: process(clk, nReset)`
243	24	rherveille	`begin`
244	35	rherveille	`if (nReset = '0') then`
245			`sta_condition <= '0';`
246			`sto_condition <= '0';`
247			`elsif (clk'event and clk = '1') then`
248			`if (rst = '1') then`
249			`sta_condition <= '0';`
250			`sto_condition <= '0';`
251			`else`
252			`sta_condition <= (not sSDA and dSDA) and sSCL;`
253			`sto_condition <= (sSDA and not dSDA) and sSCL;`
254			`end if;`
255	24	rherveille	`end if;`
256			`end process detect_sta_sto;`
257	15	rherveille
258	31	rherveille	`-- generate i2c-bus busy signal`
259	24	rherveille	`gen_busy: process(clk, nReset)`
260			`begin`
261			`if (nReset = '0') then`
262	27	rherveille	`ibusy <= '0';`
263	24	rherveille	`elsif (clk'event and clk = '1') then`
264			`if (rst = '1') then`
265	27	rherveille	`ibusy <= '0';`
266	24	rherveille	`else`
267	27	rherveille	`ibusy <= (sta_condition or ibusy) and not sto_condition;`
268	24	rherveille	`end if;`
269			`end if;`
270			`end process gen_busy;`
271	31	rherveille	`busy <= ibusy;`
272	15	rherveille
273	31	rherveille
274			`-- generate arbitration lost signal`
275	35	rherveille	`gen_al: process(clk, nReset)`
276	31	rherveille	`begin`
277	35	rherveille	`if (nReset = '0') then`
278			`cmd_stop <= '0';`
279			`ial <= '0';`
280			`elsif (clk'event and clk = '1') then`
281			`if (rst = '1') then`
282			`cmd_stop <= '0';`
283			`ial <= '0';`
284			`else`
285	38	rherveille	`if (clk_en = '1') then`
286			`if (cmd = I2C_CMD_STOP) then`
287			`cmd_stop <= '1';`
288			`else`
289			`cmd_stop <= '0';`
290			`end if;`
291	31	rherveille
292	38	rherveille	`ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);`
293	35	rherveille	`end if;`
294	31	rherveille	`end if;`
295			`end process gen_al;`
296	35	rherveille	`al <= ial;`
297	34	rherveille
298	31	rherveille	`-- generate dout signal, store dout on rising edge of SCL`
299			`gen_dout: process(clk)`
300			`begin`
301			`if (clk'event and clk = '1') then`
302			`if (sSCL = '1' and dSCL = '0') then`
303			`dout <= sSDA;`
304			`end if;`
305			`end if;`
306			`end process gen_dout;`
307	15	rherveille	`end block bus_status_ctrl;`
308
309
310			`-- generate statemachine`
311			`nxt_state_decoder : process (clk, nReset, c_state, cmd)`
312			`begin`
313	27	rherveille	`if (nReset = '0') then`
314			`c_state <= idle;`
315			`cmd_ack <= '0';`
316			`iscl_oen <= '1';`
317			`isda_oen <= '1';`
318	31	rherveille	`sda_chk <= '0';`
319	27	rherveille	`elsif (clk'event and clk = '1') then`
320	34	rherveille	`if (rst = '1' or ial = '1') then`
321	27	rherveille	`c_state <= idle;`
322			`cmd_ack <= '0';`
323			`iscl_oen <= '1';`
324			`isda_oen <= '1';`
325	31	rherveille	`sda_chk <= '0';`
326	27	rherveille	`else`
327			`cmd_ack <= '0'; -- default no acknowledge`
328	15	rherveille
329	27	rherveille	`if (clk_en = '1') then`
330			`case (c_state) is`
331			`-- idle`
332			`when idle =>`
333			`case cmd is`
334			`when I2C_CMD_START => c_state <= start_a;`
335			`when I2C_CMD_STOP => c_state <= stop_a;`
336			`when I2C_CMD_WRITE => c_state <= wr_a;`
337			`when I2C_CMD_READ => c_state <= rd_a;`
338			`when others => c_state <= idle; -- NOP command`
339			`end case;`
340	15	rherveille
341	27	rherveille	`iscl_oen <= iscl_oen; -- keep SCL in same state`
342			`isda_oen <= isda_oen; -- keep SDA in same state`
343	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
344	15	rherveille
345	27	rherveille	`-- start`
346			`when start_a =>`
347			`c_state <= start_b;`
348			`iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)`
349			`isda_oen <= '1'; -- set SDA high`
350	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
351	15	rherveille
352	27	rherveille	`when start_b =>`
353			`c_state <= start_c;`
354			`iscl_oen <= '1'; -- set SCL high`
355			`isda_oen <= '1'; -- keep SDA high`
356	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
357	15	rherveille
358	27	rherveille	`when start_c =>`
359			`c_state <= start_d;`
360			`iscl_oen <= '1'; -- keep SCL high`
361			`isda_oen <= '0'; -- set SDA low`
362	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
363	15	rherveille
364	27	rherveille	`when start_d =>`
365			`c_state <= start_e;`
366			`iscl_oen <= '1'; -- keep SCL high`
367			`isda_oen <= '0'; -- keep SDA low`
368	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
369	15	rherveille
370	27	rherveille	`when start_e =>`
371			`c_state <= idle;`
372			`cmd_ack <= '1'; -- command completed`
373			`iscl_oen <= '0'; -- set SCL low`
374			`isda_oen <= '0'; -- keep SDA low`
375	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
376	15	rherveille
377	27	rherveille	`-- stop`
378			`when stop_a =>`
379			`c_state <= stop_b;`
380	31	rherveille	`iscl_oen <= '0'; -- keep SCL low`
381	27	rherveille	`isda_oen <= '0'; -- set SDA low`
382	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
383	15	rherveille
384	27	rherveille	`when stop_b =>`
385			`c_state <= stop_c;`
386			`iscl_oen <= '1'; -- set SCL high`
387			`isda_oen <= '0'; -- keep SDA low`
388	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
389	15	rherveille
390	27	rherveille	`when stop_c =>`
391			`c_state <= stop_d;`
392			`iscl_oen <= '1'; -- keep SCL high`
393			`isda_oen <= '0'; -- keep SDA low`
394	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
395	15	rherveille
396	27	rherveille	`when stop_d =>`
397			`c_state <= idle;`
398			`cmd_ack <= '1'; -- command completed`
399			`iscl_oen <= '1'; -- keep SCL high`
400			`isda_oen <= '1'; -- set SDA high`
401	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
402	15	rherveille
403	27	rherveille	`-- read`
404			`when rd_a =>`
405			`c_state <= rd_b;`
406			`iscl_oen <= '0'; -- keep SCL low`
407			`isda_oen <= '1'; -- tri-state SDA`
408	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
409	15	rherveille
410	27	rherveille	`when rd_b =>`
411			`c_state <= rd_c;`
412			`iscl_oen <= '1'; -- set SCL high`
413			`isda_oen <= '1'; -- tri-state SDA`
414	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
415	15	rherveille
416	27	rherveille	`when rd_c =>`
417			`c_state <= rd_d;`
418			`iscl_oen <= '1'; -- keep SCL high`
419			`isda_oen <= '1'; -- tri-state SDA`
420	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
421	15	rherveille
422	27	rherveille	`when rd_d =>`
423			`c_state <= idle;`
424			`cmd_ack <= '1'; -- command completed`
425			`iscl_oen <= '0'; -- set SCL low`
426			`isda_oen <= '1'; -- tri-state SDA`
427	31	rherveille	`sda_chk <= '0'; -- don't check SDA`
428	15	rherveille
429	27	rherveille	`-- write`
430			`when wr_a =>`
431			`c_state <= wr_b;`
432			`iscl_oen <= '0'; -- keep SCL low`
433			`isda_oen <= din; -- set SDA`
434	31	rherveille	`sda_chk <= '0'; -- don't check SDA (SCL low)`
435	15	rherveille
436	27	rherveille	`when wr_b =>`
437			`c_state <= wr_c;`
438			`iscl_oen <= '1'; -- set SCL high`
439			`isda_oen <= din; -- keep SDA`
440	31	rherveille	`sda_chk <= '1'; -- check SDA`
441	15	rherveille
442	27	rherveille	`when wr_c =>`
443			`c_state <= wr_d;`
444			`iscl_oen <= '1'; -- keep SCL high`
445			`isda_oen <= din; -- keep SDA`
446	31	rherveille	`sda_chk <= '1'; -- check SDA`
447	15	rherveille
448	27	rherveille	`when wr_d =>`
449			`c_state <= idle;`
450			`cmd_ack <= '1'; -- command completed`
451			`iscl_oen <= '0'; -- set SCL low`
452			`isda_oen <= din; -- keep SDA`
453	31	rherveille	`sda_chk <= '0'; -- don't check SDA (SCL low)`
454	15	rherveille
455	27	rherveille	`when others =>`
456	15	rherveille
457	27	rherveille	`end case;`
458	24	rherveille	`end if;`
459			`end if;`
460			`end if;`
461	15	rherveille	`end process nxt_state_decoder;`
462
463
464			`-- assign outputs`
465			`scl_o <= '0';`
466			`scl_oen <= iscl_oen;`
467			`sda_o <= '0';`
468			`sda_oen <= isda_oen;`
469			`end architecture structural;`
470	34	rherveille

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