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1 15 rherveille
---------------------------------------------------------------------
2
----                                                             ----
3 27 rherveille
----  WISHBONE revB2 I2C Master Core; bit-controller             ----
4 15 rherveille
----                                                             ----
5
----                                                             ----
6
----  Author: Richard Herveille                                  ----
7
----          richard@asics.ws                                   ----
8
----          www.asics.ws                                       ----
9
----                                                             ----
10
----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
11
----                                                             ----
12
---------------------------------------------------------------------
13
----                                                             ----
14
---- Copyright (C) 2000 Richard Herveille                        ----
15
----                    richard@asics.ws                         ----
16
----                                                             ----
17
---- This source file may be used and distributed without        ----
18
---- restriction provided that this copyright statement is not   ----
19
---- removed from the file and that any derivative work contains ----
20
---- the original copyright notice and the associated disclaimer.----
21
----                                                             ----
22
----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
23
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
24
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
25
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
26
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
27
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
28
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
29
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
30
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
31
---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
32
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
34
---- POSSIBILITY OF SUCH DAMAGE.                                 ----
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----                                                             ----
36
---------------------------------------------------------------------
37
 
38
--  CVS Log
39
--
40 52 rherveille
--  $Id: i2c_master_bit_ctrl.vhd,v 1.11 2004-05-07 11:04:00 rherveille Exp $
41 15 rherveille
--
42 52 rherveille
--  $Date: 2004-05-07 11:04:00 $
43
--  $Revision: 1.11 $
44 15 rherveille
--  $Author: rherveille $
45
--  $Locker:  $
46
--  $State: Exp $
47
--
48
-- Change History:
49
--               $Log: not supported by cvs2svn $
50 52 rherveille
--               Revision 1.10  2004/02/27 07:49:43  rherveille
51
--               Fixed a bug in the arbitration-lost signal generation. VHDL version only.
52
--
53 48 rherveille
--               Revision 1.9  2003/08/12 14:48:37  rherveille
54
--               Forgot an 'end if' :-/
55
--
56 39 rherveille
--               Revision 1.8  2003/08/09 07:01:13  rherveille
57
--               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
58
--               Fixed a potential bug in the byte controller's host-acknowledge generation.
59
--
60 38 rherveille
--               Revision 1.7  2003/02/05 00:06:02  rherveille
61
--               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
62
--
63 35 rherveille
--               Revision 1.6  2003/02/01 02:03:06  rherveille
64
--               Fixed a few 'arbitration lost' bugs. VHDL version only.
65
--
66 34 rherveille
--               Revision 1.5  2002/12/26 16:05:47  rherveille
67
--               Core is now a Multimaster I2C controller.
68
--
69 31 rherveille
--               Revision 1.4  2002/11/30 22:24:37  rherveille
70
--               Cleaned up code
71
--
72 27 rherveille
--               Revision 1.3  2002/10/30 18:09:53  rherveille
73
--               Fixed some reported minor start/stop generation timing issuess.
74
--
75 24 rherveille
--               Revision 1.2  2002/06/15 07:37:04  rherveille
76
--               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
77
--
78 22 rherveille
--               Revision 1.1  2001/11/05 12:02:33  rherveille
79
--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
80
--               Code updated, is now up-to-date to doc. rev.0.4.
81
--               Added headers.
82
--
83 15 rherveille
 
84
 
85
--
86
-------------------------------------
87
-- Bit controller section
88
------------------------------------
89
--
90
-- Translate simple commands into SCL/SDA transitions
91
-- Each command has 5 states, A/B/C/D/idle
92
--
93 31 rherveille
-- start:    SCL  ~~~~~~~~~~~~~~\____
94
--           SDA  XX/~~~~~~~\______
95
--                x | A | B | C | D | i
96 15 rherveille
--
97 31 rherveille
-- repstart  SCL  ______/~~~~~~~\___
98
--           SDA  __/~~~~~~~\______
99
--                x | A | B | C | D | i
100 15 rherveille
--
101 31 rherveille
-- stop      SCL  _______/~~~~~~~~~~~
102
--           SDA  ==\___________/~~~~~
103
--                x | A | B | C | D | i
104 15 rherveille
--
105 31 rherveille
--- write    SCL  ______/~~~~~~~\____
106
--           SDA  XXX===============XX
107
--                x | A | B | C | D | i
108 15 rherveille
--
109 31 rherveille
--- read     SCL  ______/~~~~~~~\____
110
--           SDA  XXXXXXX=XXXXXXXXXXX
111
--                x | A | B | C | D | i
112 15 rherveille
--
113
 
114 24 rherveille
-- Timing:      Normal mode     Fast mode
115 15 rherveille
-----------------------------------------------------------------
116 24 rherveille
-- Fscl         100KHz          400KHz
117
-- Th_scl       4.0us           0.6us   High period of SCL
118
-- Tl_scl       4.7us           1.3us   Low period of SCL
119
-- Tsu:sta      4.7us           0.6us   setup time for a repeated start condition
120
-- Tsu:sto      4.0us           0.6us   setup time for a stop conditon
121
-- Tbuf         4.7us           1.3us   Bus free time between a stop and start condition
122 15 rherveille
--
123
 
124
library ieee;
125
use ieee.std_logic_1164.all;
126
use ieee.std_logic_arith.all;
127
 
128
entity i2c_master_bit_ctrl is
129
        port (
130
                clk    : in std_logic;
131
                rst    : in std_logic;
132
                nReset : in std_logic;
133
                ena    : in std_logic;                          -- core enable signal
134
 
135
                clk_cnt : in unsigned(15 downto 0);              -- clock prescale value
136
 
137
                cmd     : in std_logic_vector(3 downto 0);
138 31 rherveille
                cmd_ack : out std_logic; -- command completed
139
                busy    : out std_logic; -- i2c bus busy
140
                al      : out std_logic; -- arbitration lost
141 15 rherveille
 
142
                din  : in std_logic;
143
                dout : out std_logic;
144
 
145
                -- i2c lines
146
                scl_i   : in std_logic;  -- i2c clock line input
147
                scl_o   : out std_logic; -- i2c clock line output
148
                scl_oen : out std_logic; -- i2c clock line output enable, active low
149
                sda_i   : in std_logic;  -- i2c data line input
150
                sda_o   : out std_logic; -- i2c data line output
151
                sda_oen : out std_logic  -- i2c data line output enable, active low
152
        );
153
end entity i2c_master_bit_ctrl;
154
 
155
architecture structural of i2c_master_bit_ctrl is
156 22 rherveille
        constant I2C_CMD_NOP    : std_logic_vector(3 downto 0) := "0000";
157
        constant I2C_CMD_START  : std_logic_vector(3 downto 0) := "0001";
158
        constant I2C_CMD_STOP   : std_logic_vector(3 downto 0) := "0010";
159
        constant I2C_CMD_READ   : std_logic_vector(3 downto 0) := "0100";
160
        constant I2C_CMD_WRITE  : std_logic_vector(3 downto 0) := "1000";
161 15 rherveille
 
162 27 rherveille
        type states is (idle, start_a, start_b, start_c, start_d, start_e,
163 24 rherveille
                        stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
164 15 rherveille
        signal c_state : states;
165
 
166 22 rherveille
        signal iscl_oen, isda_oen : std_logic;          -- internal I2C lines
167 31 rherveille
        signal sda_chk            : std_logic;          -- check SDA status (multi-master arbitration)
168
        signal dscl_oen           : std_logic;          -- delayed scl_oen signals
169 22 rherveille
        signal sSCL, sSDA         : std_logic;          -- synchronized SCL and SDA inputs
170 34 rherveille
        signal clk_en, slave_wait : std_logic;          -- clock generation signals
171
        signal ial                : std_logic;          -- internal arbitration lost signal
172 22 rherveille
--      signal cnt : unsigned(15 downto 0) := clk_cnt;  -- clock divider counter (simulation)
173 15 rherveille
        signal cnt : unsigned(15 downto 0);             -- clock divider counter (synthesis)
174
 
175
begin
176 31 rherveille
        -- whenever the slave is not ready it can delay the cycle by pulling SCL low
177 22 rherveille
        -- delay scl_oen
178
        process (clk)
179
        begin
180 24 rherveille
            if (clk'event and clk = '1') then
181 27 rherveille
              dscl_oen <= iscl_oen;
182 24 rherveille
            end if;
183 22 rherveille
        end process;
184
        slave_wait <= dscl_oen and not sSCL;
185 15 rherveille
 
186
        -- generate clk enable signal
187
        gen_clken: process(clk, nReset)
188
        begin
189 24 rherveille
            if (nReset = '0') then
190 27 rherveille
              cnt    <= (others => '0');
191
              clk_en <= '1';
192 24 rherveille
            elsif (clk'event and clk = '1') then
193
              if (rst = '1') then
194 27 rherveille
                cnt    <= (others => '0');
195
                clk_en <= '1';
196 24 rherveille
              else
197
                if ( (cnt = 0) or (ena = '0') ) then
198 31 rherveille
                  if (slave_wait = '0') then
199
                    cnt    <= clk_cnt;
200
                    clk_en <= '1';
201
                  else
202
                    cnt    <= cnt;
203
                    clk_en <= '0';
204
                  end if;
205 24 rherveille
                else
206
                  if (slave_wait = '0') then
207 27 rherveille
                    cnt <= cnt -1;
208 24 rherveille
                  end if;
209 27 rherveille
                  clk_en <= '0';
210 24 rherveille
                end if;
211
              end if;
212
            end if;
213 15 rherveille
        end process gen_clken;
214
 
215
 
216
        -- generate bus status controller
217
        bus_status_ctrl: block
218 31 rherveille
          signal dSCL, dSDA          : std_logic;  -- delayes sSCL and sSDA
219
          signal sta_condition       : std_logic;  -- start detected
220
          signal sto_condition       : std_logic;  -- stop detected
221 38 rherveille
          signal cmd_stop            : std_logic;  -- STOP command
222 31 rherveille
          signal ibusy               : std_logic;  -- internal busy signal
223
        begin
224
            -- synchronize SCL and SDA inputs
225 35 rherveille
            synch_scl_sda: process(clk, nReset)
226 31 rherveille
            begin
227 35 rherveille
                if (nReset = '0') then
228
                  sSCL <= '1';
229
                  sSDA <= '1';
230 15 rherveille
 
231 35 rherveille
                  dSCL <= '1';
232
                  dSDA <= '1';
233
                elsif (clk'event and clk = '1') then
234
                  if (rst = '1') then
235
                    sSCL <= '1';
236
                    sSDA <= '1';
237
 
238
                    dSCL <= '1';
239
                    dSDA <= '1';
240
                  else
241
                    sSCL <= scl_i;
242
                    sSDA <= sda_i;
243
 
244
                    dSCL <= sSCL;
245
                    dSDA <= sSDA;
246
                  end if;
247 31 rherveille
                end if;
248
            end process synch_SCL_SDA;
249
 
250 24 rherveille
            -- detect start condition => detect falling edge on SDA while SCL is high
251
            -- detect stop condition  => detect rising edge on SDA while SCL is high
252 35 rherveille
            detect_sta_sto: process(clk, nReset)
253 24 rherveille
            begin
254 35 rherveille
                if (nReset = '0') then
255
                  sta_condition <= '0';
256
                  sto_condition <= '0';
257
                elsif (clk'event and clk = '1') then
258
                  if (rst = '1') then
259
                    sta_condition <= '0';
260
                    sto_condition <= '0';
261
                  else
262
                    sta_condition <= (not sSDA and dSDA) and sSCL;
263
                    sto_condition <= (sSDA and not dSDA) and sSCL;
264
                  end if;
265 24 rherveille
                end if;
266
            end process detect_sta_sto;
267 15 rherveille
 
268 31 rherveille
            -- generate i2c-bus busy signal
269 24 rherveille
            gen_busy: process(clk, nReset)
270
            begin
271
                if (nReset = '0') then
272 27 rherveille
                  ibusy <= '0';
273 24 rherveille
                elsif (clk'event and clk = '1') then
274
                  if (rst = '1') then
275 27 rherveille
                    ibusy <= '0';
276 24 rherveille
                  else
277 27 rherveille
                    ibusy <= (sta_condition or ibusy) and not sto_condition;
278 24 rherveille
                  end if;
279
                end if;
280
            end process gen_busy;
281 31 rherveille
            busy <= ibusy;
282 15 rherveille
 
283 31 rherveille
 
284
            -- generate arbitration lost signal
285 52 rherveille
            -- aribitration lost when:
286
            -- 1) master drives SDA high, but the i2c bus is low
287
            -- 2) stop detected while not requested (detect during 'idle' state)
288 35 rherveille
            gen_al: process(clk, nReset)
289 31 rherveille
            begin
290 35 rherveille
              if (nReset = '0') then
291
                cmd_stop  <= '0';
292
                ial       <= '0';
293
              elsif (clk'event and clk = '1') then
294
                if (rst = '1') then
295
                  cmd_stop  <= '0';
296
                  ial       <= '0';
297
                else
298 48 rherveille
                  if (clk_en = '1') then
299 52 rherveille
                    if (cmd = I2C_CMD_STOP) then
300 48 rherveille
                      cmd_stop <= '1';
301
                    else
302
                      cmd_stop <= '0';
303 52 rherveille
                    end if;
304 39 rherveille
                  end if;
305 31 rherveille
 
306 52 rherveille
                  if (c_state = idle) then
307
                    ial <= '0';
308
                  else
309
                    ial <= (sto_condition and not cmd_stop);
310
                  end if;
311
                  ial <= ial or (sda_chk and not sSDA and isda_oen);
312
 
313 35 rherveille
                end if;
314 31 rherveille
              end if;
315
            end process gen_al;
316 35 rherveille
            al <= ial;
317 34 rherveille
 
318 31 rherveille
            -- generate dout signal, store dout on rising edge of SCL
319
            gen_dout: process(clk)
320
            begin
321
              if (clk'event and clk = '1') then
322
                if (sSCL = '1' and dSCL = '0') then
323
                  dout <= sSDA;
324
                end if;
325
              end if;
326
            end process gen_dout;
327 15 rherveille
        end block bus_status_ctrl;
328
 
329
 
330
        -- generate statemachine
331
        nxt_state_decoder : process (clk, nReset, c_state, cmd)
332
        begin
333 27 rherveille
            if (nReset = '0') then
334
              c_state  <= idle;
335
              cmd_ack  <= '0';
336
              iscl_oen <= '1';
337
              isda_oen <= '1';
338 31 rherveille
              sda_chk  <= '0';
339 27 rherveille
            elsif (clk'event and clk = '1') then
340 34 rherveille
              if (rst = '1' or ial = '1') then
341 27 rherveille
                c_state  <= idle;
342
                cmd_ack  <= '0';
343
                iscl_oen <= '1';
344
                isda_oen <= '1';
345 31 rherveille
                sda_chk  <= '0';
346 27 rherveille
              else
347
                cmd_ack <= '0'; -- default no acknowledge
348 15 rherveille
 
349 27 rherveille
                if (clk_en = '1') then
350
                  case (c_state) is
351
                     -- idle
352
                     when idle =>
353
                        case cmd is
354
                          when I2C_CMD_START => c_state <= start_a;
355
                          when I2C_CMD_STOP  => c_state <= stop_a;
356
                          when I2C_CMD_WRITE => c_state <= wr_a;
357
                          when I2C_CMD_READ  => c_state <= rd_a;
358
                          when others        => c_state <= idle; -- NOP command
359
                        end case;
360 15 rherveille
 
361 27 rherveille
                        iscl_oen <= iscl_oen; -- keep SCL in same state
362
                        isda_oen <= isda_oen; -- keep SDA in same state
363 31 rherveille
                        sda_chk  <= '0';      -- don't check SDA
364 15 rherveille
 
365 27 rherveille
                     -- start
366
                     when start_a =>
367
                        c_state  <= start_b;
368
                        iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
369
                        isda_oen <= '1';      -- set SDA high
370 31 rherveille
                        sda_chk  <= '0';      -- don't check SDA
371 15 rherveille
 
372 27 rherveille
                     when start_b =>
373
                        c_state  <= start_c;
374
                        iscl_oen <= '1'; -- set SCL high
375
                        isda_oen <= '1'; -- keep SDA high
376 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
377 15 rherveille
 
378 27 rherveille
                     when start_c =>
379
                        c_state  <= start_d;
380
                        iscl_oen <= '1'; -- keep SCL high
381
                        isda_oen <= '0'; -- set SDA low
382 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
383 15 rherveille
 
384 27 rherveille
                     when start_d =>
385
                        c_state  <= start_e;
386
                        iscl_oen <= '1'; -- keep SCL high
387
                        isda_oen <= '0'; -- keep SDA low
388 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
389 15 rherveille
 
390 27 rherveille
                     when start_e =>
391
                        c_state  <= idle;
392
                        cmd_ack  <= '1'; -- command completed
393
                        iscl_oen <= '0'; -- set SCL low
394
                        isda_oen <= '0'; -- keep SDA low
395 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
396 15 rherveille
 
397 27 rherveille
                     -- stop
398
                     when stop_a =>
399
                        c_state  <= stop_b;
400 31 rherveille
                        iscl_oen <= '0'; -- keep SCL low
401 27 rherveille
                        isda_oen <= '0'; -- set SDA low
402 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
403 15 rherveille
 
404 27 rherveille
                     when stop_b =>
405
                        c_state  <= stop_c;
406
                        iscl_oen <= '1'; -- set SCL high
407
                        isda_oen <= '0'; -- keep SDA low
408 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
409 15 rherveille
 
410 27 rherveille
                     when stop_c =>
411
                        c_state  <= stop_d;
412
                        iscl_oen <= '1'; -- keep SCL high
413
                        isda_oen <= '0'; -- keep SDA low
414 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
415 15 rherveille
 
416 27 rherveille
                     when stop_d =>
417
                        c_state  <= idle;
418
                        cmd_ack  <= '1'; -- command completed
419
                        iscl_oen <= '1'; -- keep SCL high
420
                        isda_oen <= '1'; -- set SDA high
421 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
422 15 rherveille
 
423 27 rherveille
                     -- read
424
                     when rd_a =>
425
                        c_state  <= rd_b;
426
                        iscl_oen <= '0'; -- keep SCL low
427
                        isda_oen <= '1'; -- tri-state SDA
428 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
429 15 rherveille
 
430 27 rherveille
                     when rd_b =>
431
                        c_state  <= rd_c;
432
                        iscl_oen <= '1'; -- set SCL high
433
                        isda_oen <= '1'; -- tri-state SDA
434 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
435 15 rherveille
 
436 27 rherveille
                     when rd_c =>
437
                        c_state  <= rd_d;
438
                        iscl_oen <= '1'; -- keep SCL high
439
                        isda_oen <= '1'; -- tri-state SDA
440 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
441 15 rherveille
 
442 27 rherveille
                     when rd_d =>
443
                        c_state  <= idle;
444
                        cmd_ack  <= '1'; -- command completed
445
                        iscl_oen <= '0'; -- set SCL low
446
                        isda_oen <= '1'; -- tri-state SDA
447 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA
448 15 rherveille
 
449 27 rherveille
                     -- write
450
                     when wr_a =>
451
                        c_state  <= wr_b;
452
                        iscl_oen <= '0'; -- keep SCL low
453
                        isda_oen <= din; -- set SDA
454 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA (SCL low)
455 15 rherveille
 
456 27 rherveille
                     when wr_b =>
457
                        c_state  <= wr_c;
458
                        iscl_oen <= '1'; -- set SCL high
459
                        isda_oen <= din; -- keep SDA
460 31 rherveille
                        sda_chk  <= '1'; -- check SDA
461 15 rherveille
 
462 27 rherveille
                     when wr_c =>
463
                        c_state  <= wr_d;
464
                        iscl_oen <= '1'; -- keep SCL high
465
                        isda_oen <= din; -- keep SDA
466 31 rherveille
                        sda_chk  <= '1'; -- check SDA
467 15 rherveille
 
468 27 rherveille
                     when wr_d =>
469
                        c_state  <= idle;
470
                        cmd_ack  <= '1'; -- command completed
471
                        iscl_oen <= '0'; -- set SCL low
472
                        isda_oen <= din; -- keep SDA
473 31 rherveille
                        sda_chk  <= '0'; -- don't check SDA (SCL low)
474 15 rherveille
 
475 27 rherveille
                     when others =>
476 15 rherveille
 
477 27 rherveille
                  end case;
478 24 rherveille
                end if;
479
              end if;
480
            end if;
481 15 rherveille
        end process nxt_state_decoder;
482
 
483
 
484
        -- assign outputs
485
        scl_o   <= '0';
486
        scl_oen <= iscl_oen;
487
        sda_o   <= '0';
488
        sda_oen <= isda_oen;
489
end architecture structural;
490 34 rherveille
 

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