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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_bit_ctrl.vhd] - Blame information for rev 72

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1 15 rherveille
---------------------------------------------------------------------
2
----                                                             ----
3 27 rherveille
----  WISHBONE revB2 I2C Master Core; bit-controller             ----
4 15 rherveille
----                                                             ----
5
----                                                             ----
6
----  Author: Richard Herveille                                  ----
7
----          richard@asics.ws                                   ----
8
----          www.asics.ws                                       ----
9
----                                                             ----
10
----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
11
----                                                             ----
12
---------------------------------------------------------------------
13
----                                                             ----
14
---- Copyright (C) 2000 Richard Herveille                        ----
15
----                    richard@asics.ws                         ----
16
----                                                             ----
17
---- This source file may be used and distributed without        ----
18
---- restriction provided that this copyright statement is not   ----
19
---- removed from the file and that any derivative work contains ----
20
---- the original copyright notice and the associated disclaimer.----
21
----                                                             ----
22
----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
23
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
24
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
25
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
26
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
27
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
28
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
29
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
30
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
31
---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
32
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
34
---- POSSIBILITY OF SUCH DAMAGE.                                 ----
35
----                                                             ----
36
---------------------------------------------------------------------
37
 
38
--  CVS Log
39
--
40 67 rherveille
--  $Id: i2c_master_bit_ctrl.vhd,v 1.17 2009-02-04 20:17:34 rherveille Exp $
41 15 rherveille
--
42 67 rherveille
--  $Date: 2009-02-04 20:17:34 $
43
--  $Revision: 1.17 $
44 15 rherveille
--  $Author: rherveille $
45
--  $Locker:  $
46
--  $State: Exp $
47
--
48
-- Change History:
49
--               $Log: not supported by cvs2svn $
50 67 rherveille
--               Revision 1.16  2009/01/20 20:40:36  rherveille
51
--               Fixed type iscl_oen instead of scl_oen
52
--
53 66 rherveille
--               Revision 1.15  2009/01/20 10:34:51  rherveille
54
--               Added SCL clock synchronization logic
55
--               Fixed slave_wait signal generation
56
--
57 64 rherveille
--               Revision 1.14  2006/10/11 12:10:13  rherveille
58
--               Added missing semicolons ';' on endif
59
--
60 60 rherveille
--               Revision 1.13  2006/10/06 10:48:24  rherveille
61
--               fixed short scl high pulse after clock stretch
62
--
63 59 rherveille
--               Revision 1.12  2004/05/07 11:53:31  rherveille
64
--               Fixed previous fix :) Made a variable vs signal mistake.
65
--
66 53 rherveille
--               Revision 1.11  2004/05/07 11:04:00  rherveille
67
--               Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
68
--
69 52 rherveille
--               Revision 1.10  2004/02/27 07:49:43  rherveille
70
--               Fixed a bug in the arbitration-lost signal generation. VHDL version only.
71
--
72 48 rherveille
--               Revision 1.9  2003/08/12 14:48:37  rherveille
73
--               Forgot an 'end if' :-/
74
--
75 39 rherveille
--               Revision 1.8  2003/08/09 07:01:13  rherveille
76
--               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
77
--               Fixed a potential bug in the byte controller's host-acknowledge generation.
78
--
79 38 rherveille
--               Revision 1.7  2003/02/05 00:06:02  rherveille
80
--               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
81
--
82 35 rherveille
--               Revision 1.6  2003/02/01 02:03:06  rherveille
83
--               Fixed a few 'arbitration lost' bugs. VHDL version only.
84
--
85 34 rherveille
--               Revision 1.5  2002/12/26 16:05:47  rherveille
86
--               Core is now a Multimaster I2C controller.
87
--
88 31 rherveille
--               Revision 1.4  2002/11/30 22:24:37  rherveille
89
--               Cleaned up code
90
--
91 27 rherveille
--               Revision 1.3  2002/10/30 18:09:53  rherveille
92
--               Fixed some reported minor start/stop generation timing issuess.
93
--
94 24 rherveille
--               Revision 1.2  2002/06/15 07:37:04  rherveille
95
--               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
96
--
97 22 rherveille
--               Revision 1.1  2001/11/05 12:02:33  rherveille
98
--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
99
--               Code updated, is now up-to-date to doc. rev.0.4.
100
--               Added headers.
101
--
102 15 rherveille
 
103
 
104
--
105
-------------------------------------
106
-- Bit controller section
107
------------------------------------
108
--
109
-- Translate simple commands into SCL/SDA transitions
110
-- Each command has 5 states, A/B/C/D/idle
111
--
112 31 rherveille
-- start:    SCL  ~~~~~~~~~~~~~~\____
113 72 rherveille
--           SDA  XX/~~~~~~~\______
114
--                x | A | B | C | D | i
115 15 rherveille
--
116 31 rherveille
-- repstart  SCL  ______/~~~~~~~\___
117 72 rherveille
--           SDA  __/~~~~~~~\______
118
--                x | A | B | C | D | i
119 15 rherveille
--
120 31 rherveille
-- stop      SCL  _______/~~~~~~~~~~~
121 72 rherveille
--           SDA  ==\___________/~~~~~
122
--                x | A | B | C | D | i
123 15 rherveille
--
124 31 rherveille
--- write    SCL  ______/~~~~~~~\____
125 72 rherveille
--           SDA  XXX===============XX
126
--                x | A | B | C | D | i
127 15 rherveille
--
128 31 rherveille
--- read     SCL  ______/~~~~~~~\____
129 72 rherveille
--           SDA  XXXXXXX=XXXXXXXXXXX
130
--                x | A | B | C | D | i
131 15 rherveille
--
132
 
133 24 rherveille
-- Timing:      Normal mode     Fast mode
134 15 rherveille
-----------------------------------------------------------------
135 24 rherveille
-- Fscl         100KHz          400KHz
136
-- Th_scl       4.0us           0.6us   High period of SCL
137
-- Tl_scl       4.7us           1.3us   Low period of SCL
138
-- Tsu:sta      4.7us           0.6us   setup time for a repeated start condition
139
-- Tsu:sto      4.0us           0.6us   setup time for a stop conditon
140
-- Tbuf         4.7us           1.3us   Bus free time between a stop and start condition
141 15 rherveille
--
142
 
143
library ieee;
144
use ieee.std_logic_1164.all;
145 72 rherveille
use ieee.numeric_std.all;
146 15 rherveille
 
147
entity i2c_master_bit_ctrl is
148 72 rherveille
    port (
149
          clk    : in std_logic;
150
          rst    : in std_logic;
151
          nReset : in std_logic;
152
          ena    : in std_logic;                     -- core enable signal
153 15 rherveille
 
154 72 rherveille
          clk_cnt : in unsigned(15 downto 0);        -- clock prescale value
155 15 rherveille
 
156 72 rherveille
          cmd     : in std_logic_vector(3 downto 0);
157
          cmd_ack : out std_logic;                   -- command completed
158
          busy    : out std_logic;                   -- i2c bus busy
159
          al      : out std_logic;                   -- arbitration lost
160 15 rherveille
 
161 72 rherveille
          din  : in std_logic;
162
          dout : out std_logic;
163 15 rherveille
 
164 72 rherveille
          -- i2c lines
165
          scl_i   : in std_logic;                    -- i2c clock line input
166
          scl_o   : out std_logic;                   -- i2c clock line output
167
          scl_oen : out std_logic;                   -- i2c clock line output enable, active low
168
          sda_i   : in std_logic;                    -- i2c data line input
169
          sda_o   : out std_logic;                   -- i2c data line output
170
          sda_oen : out std_logic                    -- i2c data line output enable, active low
171
    );
172 15 rherveille
end entity i2c_master_bit_ctrl;
173
 
174
architecture structural of i2c_master_bit_ctrl is
175 72 rherveille
    constant I2C_CMD_NOP    : std_logic_vector(3 downto 0) := "0000";
176
    constant I2C_CMD_START  : std_logic_vector(3 downto 0) := "0001";
177
    constant I2C_CMD_STOP   : std_logic_vector(3 downto 0) := "0010";
178
    constant I2C_CMD_READ   : std_logic_vector(3 downto 0) := "0100";
179
    constant I2C_CMD_WRITE  : std_logic_vector(3 downto 0) := "1000";
180 15 rherveille
 
181 72 rherveille
    type states is (idle, start_a, start_b, start_c, start_d, start_e,
182
                    stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
183
    signal c_state : states;
184 15 rherveille
 
185 72 rherveille
    signal iscl_oen, isda_oen   : std_logic;             -- internal I2C lines
186
    signal sda_chk              : std_logic;             -- check SDA status (multi-master arbitration)
187
    signal dscl_oen             : std_logic;             -- delayed scl_oen signals
188
    signal sSCL, sSDA           : std_logic;             -- synchronized SCL and SDA inputs
189
    signal dSCL, dSDA           : std_logic;             -- delayed versions ofsSCL and sSDA
190
    signal clk_en               : std_logic;             -- statemachine clock enable
191
    signal scl_sync, slave_wait : std_logic;             -- clock generation signals
192
    signal ial                  : std_logic;             -- internal arbitration lost signal
193
    signal cnt                  : unsigned(15 downto 0); -- clock divider counter (synthesis)
194 15 rherveille
 
195
begin
196 72 rherveille
    -- whenever the slave is not ready it can delay the cycle by pulling SCL low
197
    -- delay scl_oen
198
    process (clk, nReset)
199
    begin
200
        if (nReset = '0') then
201
            dscl_oen <= '0';
202
        elsif (clk'event and clk = '1') then
203
            dscl_oen <= iscl_oen;
204
        end if;
205
    end process;
206 15 rherveille
 
207 72 rherveille
    -- slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
208
    -- slave_wait remains asserted until the slave releases SCL
209
    process (clk, nReset)
210
    begin
211
        if (nReset = '0') then
212
            slave_wait <= '0';
213
        elsif (clk'event and clk = '1') then
214
               slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL);
215
        end if;
216
    end process;
217 64 rherveille
 
218 72 rherveille
    -- master drives SCL high, but another master pulls it low
219
    -- master start counting down its low cycle now (clock synchronization)
220
    scl_sync <= dSCL and not sSCL and iscl_oen;
221 64 rherveille
 
222 72 rherveille
    -- generate clk enable signal
223
    gen_clken: process(clk, nReset)
224
    begin
225
        if (nReset = '0') then
226
            cnt    <= (others => '0');
227
            clk_en <= '1';
228
        elsif (clk'event and clk = '1') then
229
               if ((rst = '1') or (cnt = 0) or (ena = '0') or (scl_sync = '1')) then
230
                   cnt    <= clk_cnt;
231
                   clk_en <= '1';
232
               elsif (slave_wait = '1') then
233
                   cnt    <= cnt;
234
                   clk_en <= '0';
235
               else
236
                   cnt    <= cnt -1;
237
                   clk_en <= '0';
238
               end if;
239
        end if;
240
    end process gen_clken;
241 15 rherveille
 
242
 
243 72 rherveille
    -- generate bus status controller
244
    bus_status_ctrl: block
245
      signal cSCL, cSDA    : std_logic_vector( 1 downto 0); -- capture SDA and SCL
246
      signal fSCL, fSDA    : std_logic_vector( 2 downto 0); -- filter inputs for SCL and SDA
247
      signal filter_cnt    : unsigned(13 downto 0);         -- clock divider for filter
248
      signal sta_condition : std_logic;                     -- start detected
249
      signal sto_condition : std_logic;                     -- stop detected
250
      signal cmd_stop      : std_logic;                     -- STOP command
251
      signal ibusy         : std_logic;                     -- internal busy signal
252
    begin
253
        -- capture SCL and SDA
254
        capture_scl_sda: process(clk, nReset)
255
        begin
256
            if (nReset = '0') then
257
                cSCL <= "00";
258
                cSDA <= "00";
259
            elsif (clk'event and clk = '1') then
260
                if (rst = '1') then
261
                    cSCL <= "00";
262
                    cSDA <= "00";
263
                else
264
                    cSCL <= (cSCL(0) & scl_i);
265
                    cSDA <= (cSDA(0) & sda_i);
266
                end if;
267
            end if;
268
        end process capture_scl_sda;
269 15 rherveille
 
270 72 rherveille
        -- filter SCL and SDA; (attempt to) remove glitches
271
        filter_divider: process(clk, nReset)
272
        begin
273
            if (nReset = '0') then
274
                filter_cnt <= (others => '0');
275
            elsif (clk'event and clk = '1') then
276
                if ((rst = '1') or (filter_cnt = 0)) then
277
                    filter_cnt <= clk_cnt(15 downto 2);
278
                else
279
                    filter_cnt <= filter_cnt -1;
280
                end if;
281
            end if;
282
        end process filter_divider;
283 35 rherveille
 
284 72 rherveille
        filter_scl_sda: process(clk, nReset)
285
        begin
286
            if (nReset = '0') then
287
                fSCL <= (others => '1');
288
                fSDA <= (others => '1');
289
            elsif (clk'event and clk = '1') then
290
                if (rst = '1') then
291
                    fSCL <= (others => '1');
292
                    fSDA <= (others => '1');
293
                elsif (filter_cnt = 0) then
294
                    fSCL <= (fSCL(1 downto 0) & cSCL(1));
295
                    fSDA <= (fSDA(1 downto 0) & cSDA(1));
296
                end if;
297
            end if;
298
        end process filter_scl_sda;
299 35 rherveille
 
300 72 rherveille
       -- generate filtered SCL and SDA signals
301
       scl_sda: process(clk, nReset)
302
       begin
303
           if (nReset = '0') then
304
               sSCL <= '1';
305
               sSDA <= '1';
306 31 rherveille
 
307 72 rherveille
               dSCL <= '1';
308
               dSDA <= '1';
309
           elsif (clk'event and clk = '1') then
310
               if (rst = '1') then
311
                   sSCL <= '1';
312
                   sSDA <= '1';
313 15 rherveille
 
314 72 rherveille
                   dSCL <= '1';
315
                   dSDA <= '1';
316
               else
317
                  sSCL <= (fSCL(2) and fSCL(1)) or
318
                          (fSCL(2) and fSCL(0)) or
319
                          (fSCL(1) and fSCL(0));
320
                  sSDA <= (fSDA(2) and fSDA(1)) or
321
                          (fSDA(2) and fSDA(0)) or
322
                          (fSCL(1) and fSCL(0));
323 15 rherveille
 
324 72 rherveille
                  dSCL <= sSCL;
325
                  dSDA <= sSDA;
326
               end if;
327
           end if;
328
       end process scl_sda;
329 31 rherveille
 
330
 
331 72 rherveille
       -- detect start condition => detect falling edge on SDA while SCL is high
332
       -- detect stop condition  => detect rising edge on SDA while SCL is high
333
       detect_sta_sto: process(clk, nReset)
334
       begin
335
           if (nReset = '0') then
336
               sta_condition <= '0';
337
               sto_condition <= '0';
338
           elsif (clk'event and clk = '1') then
339
               if (rst = '1') then
340
                   sta_condition <= '0';
341
                   sto_condition <= '0';
342
               else
343
                   sta_condition <= (not sSDA and dSDA) and sSCL;
344
                   sto_condition <= (sSDA and not dSDA) and sSCL;
345
               end if;
346
           end if;
347
       end process detect_sta_sto;
348 52 rherveille
 
349 34 rherveille
 
350 72 rherveille
       -- generate i2c-bus busy signal
351
       gen_busy: process(clk, nReset)
352
       begin
353
           if (nReset = '0') then
354
               ibusy <= '0';
355
           elsif (clk'event and clk = '1') then
356
               if (rst = '1') then
357
                   ibusy <= '0';
358
               else
359
                   ibusy <= (sta_condition or ibusy) and not sto_condition;
360
               end if;
361
           end if;
362
       end process gen_busy;
363
       busy <= ibusy;
364 15 rherveille
 
365
 
366 72 rherveille
       -- generate arbitration lost signal
367
       -- aribitration lost when:
368
       -- 1) master drives SDA high, but the i2c bus is low
369
       -- 2) stop detected while not requested (detect during 'idle' state)
370
       gen_al: process(clk, nReset)
371
       begin
372
           if (nReset = '0') then
373
               cmd_stop  <= '0';
374
               ial       <= '0';
375
           elsif (clk'event and clk = '1') then
376
               if (rst = '1') then
377
                   cmd_stop  <= '0';
378
                   ial       <= '0';
379
               else
380
                   if (clk_en = '1') then
381
                       if (cmd = I2C_CMD_STOP) then
382
                           cmd_stop <= '1';
383
                       else
384
                           cmd_stop <= '0';
385
                       end if;
386
                   end if;
387 15 rherveille
 
388 72 rherveille
                   if (c_state = idle) then
389
                       ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
390
                   else
391
                       ial <= (sda_chk and not sSDA and isda_oen);
392
                   end if;
393
               end if;
394
          end if;
395
       end process gen_al;
396
       al <= ial;
397 15 rherveille
 
398
 
399 72 rherveille
       -- generate dout signal, store dout on rising edge of SCL
400
       gen_dout: process(clk, nReset)
401
       begin
402
           if (nReset = '0') then
403
               dout <= '0';
404
           elsif (clk'event and clk = '1') then
405
               if (sSCL = '1' and dSCL = '0') then
406
                   dout <= sSDA;
407
               end if;
408
           end if;
409
       end process gen_dout;
410
    end block bus_status_ctrl;
411 15 rherveille
 
412
 
413 72 rherveille
    -- generate statemachine
414
    nxt_state_decoder : process (clk, nReset)
415
    begin
416
        if (nReset = '0') then
417
            c_state  <= idle;
418
            cmd_ack  <= '0';
419
            iscl_oen <= '1';
420
            isda_oen <= '1';
421
            sda_chk  <= '0';
422
        elsif (clk'event and clk = '1') then
423
               if (rst = '1' or ial = '1') then
424
                   c_state  <= idle;
425
                   cmd_ack  <= '0';
426
                   iscl_oen <= '1';
427
                   isda_oen <= '1';
428
                   sda_chk  <= '0';
429
               else
430
                   cmd_ack <= '0'; -- default no acknowledge
431 15 rherveille
 
432 72 rherveille
                   if (clk_en = '1') then
433
                       case (c_state) is
434
                             -- idle
435
                             when idle =>
436
                                 case cmd is
437
                                     when I2C_CMD_START => c_state <= start_a;
438
                                     when I2C_CMD_STOP  => c_state <= stop_a;
439
                                     when I2C_CMD_WRITE => c_state <= wr_a;
440
                                     when I2C_CMD_READ  => c_state <= rd_a;
441
                                     when others        => c_state <= idle; -- NOP command
442
                                 end case;
443 15 rherveille
 
444 72 rherveille
                                 iscl_oen <= iscl_oen; -- keep SCL in same state
445
                                 isda_oen <= isda_oen; -- keep SDA in same state
446
                                 sda_chk  <= '0';      -- don't check SDA
447 15 rherveille
 
448 72 rherveille
                             -- start
449
                             when start_a =>
450
                                 c_state  <= start_b;
451
                                 iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
452
                                 isda_oen <= '1';      -- set SDA high
453
                                 sda_chk  <= '0';      -- don't check SDA
454 15 rherveille
 
455 72 rherveille
                             when start_b =>
456
                                 c_state  <= start_c;
457
                                 iscl_oen <= '1'; -- set SCL high
458
                                 isda_oen <= '1'; -- keep SDA high
459
                                 sda_chk  <= '0'; -- don't check SDA
460 15 rherveille
 
461 72 rherveille
                             when start_c =>
462
                                 c_state  <= start_d;
463
                                 iscl_oen <= '1'; -- keep SCL high
464
                                 isda_oen <= '0'; -- set SDA low
465
                                 sda_chk  <= '0'; -- don't check SDA
466 15 rherveille
 
467 72 rherveille
                             when start_d =>
468
                                 c_state  <= start_e;
469
                                 iscl_oen <= '1'; -- keep SCL high
470
                                 isda_oen <= '0'; -- keep SDA low
471
                                 sda_chk  <= '0'; -- don't check SDA
472 15 rherveille
 
473 72 rherveille
                             when start_e =>
474
                                 c_state  <= idle;
475
                                 cmd_ack  <= '1'; -- command completed
476
                                 iscl_oen <= '0'; -- set SCL low
477
                                 isda_oen <= '0'; -- keep SDA low
478
                                 sda_chk  <= '0'; -- don't check SDA
479 15 rherveille
 
480 72 rherveille
                             -- stop
481
                            when stop_a =>
482
                                c_state  <= stop_b;
483
                                iscl_oen <= '0'; -- keep SCL low
484
                                isda_oen <= '0'; -- set SDA low
485
                                sda_chk  <= '0'; -- don't check SDA
486 15 rherveille
 
487 72 rherveille
                            when stop_b =>
488
                                c_state  <= stop_c;
489
                                iscl_oen <= '1'; -- set SCL high
490
                                isda_oen <= '0'; -- keep SDA low
491
                                sda_chk  <= '0'; -- don't check SDA
492 15 rherveille
 
493 72 rherveille
                            when stop_c =>
494
                                c_state  <= stop_d;
495
                                iscl_oen <= '1'; -- keep SCL high
496
                                isda_oen <= '0'; -- keep SDA low
497
                                sda_chk  <= '0'; -- don't check SDA
498 15 rherveille
 
499 72 rherveille
                            when stop_d =>
500
                                c_state  <= idle;
501
                                cmd_ack  <= '1'; -- command completed
502
                                iscl_oen <= '1'; -- keep SCL high
503
                                isda_oen <= '1'; -- set SDA high
504
                                sda_chk  <= '0'; -- don't check SDA
505 15 rherveille
 
506 72 rherveille
                            -- read
507
                            when rd_a =>
508
                                c_state  <= rd_b;
509
                                iscl_oen <= '0'; -- keep SCL low
510
                                isda_oen <= '1'; -- tri-state SDA
511
                                sda_chk  <= '0'; -- don't check SDA
512 15 rherveille
 
513 72 rherveille
                            when rd_b =>
514
                                c_state  <= rd_c;
515
                                iscl_oen <= '1'; -- set SCL high
516
                                isda_oen <= '1'; -- tri-state SDA
517
                                sda_chk  <= '0'; -- don't check SDA
518 15 rherveille
 
519 72 rherveille
                            when rd_c =>
520
                                c_state  <= rd_d;
521
                                iscl_oen <= '1'; -- keep SCL high
522
                                isda_oen <= '1'; -- tri-state SDA
523
                                sda_chk  <= '0'; -- don't check SDA
524 15 rherveille
 
525 72 rherveille
                            when rd_d =>
526
                                c_state  <= idle;
527
                                cmd_ack  <= '1'; -- command completed
528
                                iscl_oen <= '0'; -- set SCL low
529
                                isda_oen <= '1'; -- tri-state SDA
530
                                sda_chk  <= '0'; -- don't check SDA
531 15 rherveille
 
532 72 rherveille
                            -- write
533
                            when wr_a =>
534
                                c_state  <= wr_b;
535
                                iscl_oen <= '0'; -- keep SCL low
536
                                isda_oen <= din; -- set SDA
537
                                sda_chk  <= '0'; -- don't check SDA (SCL low)
538 15 rherveille
 
539 72 rherveille
                            when wr_b =>
540
                                c_state  <= wr_c;
541
                                iscl_oen <= '1'; -- set SCL high
542
                                isda_oen <= din; -- keep SDA
543
                                sda_chk  <= '0'; -- don't check SDA yet
544
                                                 -- Allow some more time for SDA and SCL to settle
545 15 rherveille
 
546 72 rherveille
                            when wr_c =>
547
                                c_state  <= wr_d;
548
                                iscl_oen <= '1'; -- keep SCL high
549
                                isda_oen <= din; -- keep SDA
550
                                sda_chk  <= '1'; -- check SDA
551
 
552
                            when wr_d =>
553
                                c_state  <= idle;
554
                                cmd_ack  <= '1'; -- command completed
555
                                iscl_oen <= '0'; -- set SCL low
556
                                isda_oen <= din; -- keep SDA
557
                                sda_chk  <= '0'; -- don't check SDA (SCL low)
558
 
559
                            when others =>
560
 
561
                       end case;
562
                   end if;
563
               end if;
564
        end if;
565
    end process nxt_state_decoder;
566
 
567
 
568
    -- assign outputs
569
    scl_o   <= '0';
570
    scl_oen <= iscl_oen;
571
    sda_o   <= '0';
572
    sda_oen <= isda_oen;
573 15 rherveille
end architecture structural;
574 34 rherveille
 

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