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<b><font size=+2 face="Helvetica, Arial"
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color=#bf0000>Project Name: I2C controller core</font></b>
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<p>
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<font size=+1><b>Description</b></font>
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<P>
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I2C is a two-wire, bidirectional serials bus that provide a simple, efficient method of data exchange between devices.
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<BR>
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You can find I2C specification on <A HREF=http://www-us.semiconductors.philips.com/acrobat/various/I2C_BUS_SPECIFICATION_3.pdf> Phillips web Site</A>.
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<BR>
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<p>
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<font size=+1><b>What you get</b></font><p>
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The simplest master I2C ever built! Requirement is low gate count so features are restricted:<BR>
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<UL>
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<LI>No Multimaster operation
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<LI>No FIFO
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<LI>No slave mode
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</UL>
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<BR>
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The processor interface is composed of four registers:
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<UL>
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<LI>Timing Register (TR)
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<LI>Control Register (CR)
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<LI>Status Register (SR)
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<LI>Data Register (DR)
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</UL>
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This is a copy of <I>ColdFire</I> MBUS Interface Programmer's Model from Motorola.
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<P>
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There is the preliminary block diagram :
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<img src="Block.gif" border="0" ><br>
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The design is fully synchronous, only one clock. The Timing register fix the output rate of the I2C bus.
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<br>
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The bus interface is not specified at this time and it would be either OR1K specific bus or APB (from AMBA specification).
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<P>
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Current Status:
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<ul>
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working on functional and design specifications
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</ul>
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<p>Maintainer(s):
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<ul><a href=mailto:f.renet@mipsys.com_NOSPAM>Frédéric Renet</A></ul>
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<p>Mailing-list:
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<ul><a href=mailto:cores@opencores.org_NOSPAM>cores@opencores.org_NOSPAM</A></ul>
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