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--
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-- VHDL Architecture i2c.i2c_core_v02.arc
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--
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-- Created:
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-- by - Eli&Natalie.UNKNOWN (ELI)
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-- at - 20:01:49 06/11/2008
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--
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-- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY i2c_core_v02 IS
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generic
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(
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CLK_FREQ : natural := 25000000
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);
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PORT
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(
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--INPUTS
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sys_clk : IN std_logic;
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sys_rst : IN std_logic;
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start : IN std_logic;
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stop : IN std_logic;
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read : IN std_logic;
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write : IN std_logic;
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send_ack : IN std_logic;
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mstr_din : IN std_logic_vector ( 7 DOWNTO 0 );
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slv_din : IN std_logic_vector ( 7 DOWNTO 0 );
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slv_a0 : IN std_logic;
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slv_a1 : IN std_logic;
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slv_a2 : IN std_logic;
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slv_a3 : IN std_logic;
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slv_a4 : IN std_logic;
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slv_a5 : IN std_logic;
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slv_a6 : IN std_logic;
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reg_exist: IN std_logic;
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--OUTPUTS
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sda : INOUT std_logic;
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scl : INOUT std_logic;
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slv_read : OUT std_logic;
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slv_write: OUT std_logic;
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slv_busy : OUT std_logic; --slave is busy
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slv_int : OUT std_logic; --interrupt from the slave to its interface
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free : OUT std_logic;
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rec_ack : OUT std_logic;
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ready : OUT std_logic;
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mstr_slv : OUT std_logic;
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mstr_dout: OUT std_logic_vector( 7 downto 0 );
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slv_dout : OUT std_logic_vector( 7 DOWNTO 0 )
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);
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END ENTITY i2c_core_v02;
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--
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ARCHITECTURE arc OF i2c_core_v02 IS
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constant FRAME : natural := 11; -- number of bits in frame: start, stop, 8 bits data, 1 bit acknoledge
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constant BAUD : natural := 200000;
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-- constant CLK_FREQ : natural := 25000000;
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constant FULL_BIT : natural := CLK_FREQ / BAUD;
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constant HALF_BIT : natural := FULL_BIT / 2;
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constant GAP_WIDTH : natural := FULL_BIT * 2;
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signal i_mstr_slv : std_logic; --for master-slave arbitration 1 - master, 0 - slave
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signal i_free : std_logic;
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signal i_ready : std_logic;
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signal i_sda_mstr : std_logic;
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signal i_scl_mstr : std_logic;
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signal i_scl_cntr : natural range 0 to 511;
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signal i_bit_cntr_mstr : natural range 0 to 7;
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signal i_ack_mstr : std_logic;
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signal i_mstr_rd_data : std_logic_vector( 7 downto 0 );
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signal i_mstr_ad : std_logic_vector( 7 downto 0 ); --latched address and data
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alias fld_rd_wr : std_logic is i_mstr_ad( 0 ); --1 - read, 0 - write
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-- slave signals
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signal i_slv_sda_fall : std_logic;
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signal i_slv_sda_rise : std_logic;
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signal i_slv_scl_fall : std_logic;
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signal i_slv_scl_rise : std_logic;
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signal i_sda_sam : std_logic_vector( 1 downto 0 );
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signal i_scl_sam : std_logic_vector( 1 downto 0 );
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signal i_sda_slv : std_logic;
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signal i_slv_data : std_logic_vector( 7 downto 0 );
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signal i_slv_addr : std_logic_vector( 7 downto 0 );
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signal i_slv_reg_addr : std_logic_vector( 7 downto 0 );
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signal i_slv_bit_cnt : natural range 0 to 10;
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signal i_slv_stop_bit : std_logic;
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signal i_slv_strt_bit : std_logic;
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signal i_slv_dout : std_logic_vector( 7 downto 0 );
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--address "1111111" not legal
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signal SLAVE_ADDR : std_logic_vector( 6 downto 0 );
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type i2c_master_state is ( mstr_idle, mstr_start_cnt , mstr_active , mstr_wait_first_half , mstr_wait_second_half ,
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mstr_wait_full , mstr_wait_ack , mstr_wait_ack_second_half , mstr_wait_ack_third_half ,
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mstr_wait_ack_fourth_half , mstr_rd_wait_low , mstr_rd_wait_half , mstr_rd_read , mstr_stop ,
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mstr_rd_wait_last_half , mstr_rd_wait_ack , mstr_rd_get_ack , mstr_restart , mstr_gap );
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signal stm_mstr : i2c_master_state;
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type i2c_slave_state is ( slv_idle , slv_get_addr , slv_rd_wr , slv_read_reg_addr , slv_write_data , slv_send_addr_ack, slv_wait_ack , slv_send_data_ack ,
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slv_wait_data_ack , slv_read_data , slv_get_data_ack , slv_get_wait_data_ack );
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signal stm_slv : i2c_slave_state;
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BEGIN
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sda <= i_sda_mstr when ( i_mstr_slv = '1' ) else i_sda_slv;
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scl <= i_scl_mstr;
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free <= i_free;
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ready <= i_ready;
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mstr_slv <= i_mstr_slv;
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arbitration:
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process( sys_clk , sys_rst )
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begin
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if ( sys_rst = '1' ) then
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i_mstr_slv <= '1';
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-- i_slv_stop_bit <= '0';
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elsif rising_edge( sys_clk ) then
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SLAVE_ADDR <= slv_a6 & slv_a5 & slv_a4 & slv_a3 & slv_a2 & slv_a1 & slv_a0;
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i_scl_sam( 0 ) <= scl;
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i_scl_sam( 1 ) <= i_scl_sam( 0 );
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i_sda_sam( 0 ) <= sda;
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i_sda_sam( 1 ) <= i_sda_sam( 0 );
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if ( sda = '0' ) and ( scl = '1' ) and ( stm_mstr = mstr_idle ) then
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i_mstr_slv <= '0'; --slave
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elsif ( i_slv_sda_rise = '1' ) and ( to_X01( scl ) = '1' ) then
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i_mstr_slv <= '1'; --master
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end if;
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end if;
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end process arbitration;
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i_slv_sda_fall <= not i_sda_sam( 0 ) and i_sda_sam( 1 );
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i_slv_sda_rise <= i_sda_sam( 0 ) and not i_sda_sam( 1 );
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i_slv_scl_fall <= not i_scl_sam( 0 ) and i_scl_sam( 1 );
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i_slv_scl_rise <= i_scl_sam( 0 ) and not i_scl_sam( 1 );
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i_slv_stop_bit <= '1' when ( i_slv_sda_rise = '1' ) and ( to_X01( scl ) = '1' ) else '0';
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i_slv_strt_bit <= '1' when ( i_slv_sda_fall = '1' ) and ( to_X01( scl ) = '1' ) else '0';
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rec_ack <= not i_ack_mstr;
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i2c_master:
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process( sys_clk , sys_rst )
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begin
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if ( sys_rst = '1' ) then
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stm_mstr <= mstr_idle;
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i_free <= '0';
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i_ready <= '0';
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i_sda_mstr <= 'Z';
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i_scl_mstr <= 'Z';
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i_scl_cntr <= 0;
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i_bit_cntr_mstr <= 7;
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i_ack_mstr <= '1';
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i_mstr_rd_data <= ( others => '0' );
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mstr_dout <= ( others => '0' );
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i_mstr_ad <= ( others => '0' );
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elsif rising_edge( sys_clk ) then
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if ( i_mstr_slv = '1' ) then
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case stm_mstr is
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-------------------
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when mstr_idle =>
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i_free <= '1';
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i_ready <= '0';
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i_sda_mstr <= 'Z';
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i_scl_mstr <= 'Z';
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if ( start = '1' ) then
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stm_mstr <= mstr_start_cnt;
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i_free <= '0';
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else
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stm_mstr <= mstr_idle;
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end if;
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-------------------
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when mstr_start_cnt =>
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i_sda_mstr <= '0';
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i_scl_mstr <= '1';
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if ( i_scl_cntr < HALF_BIT ) then
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i_scl_cntr <= i_scl_cntr + 1;
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stm_mstr <= mstr_start_cnt;
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else
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i_scl_cntr <= 0;
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stm_mstr <= mstr_active;
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i_scl_mstr <= '0';
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end if;
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-------------------
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when mstr_active =>
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i_ready <= '1';
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i_scl_mstr <= '0';
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i_sda_mstr <= '0';
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i_bit_cntr_mstr <= 7;
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if ( read = '1' ) then
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stm_mstr <= mstr_rd_wait_low;
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i_ready <= '0';
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elsif ( write = '1' ) then
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i_mstr_ad <= mstr_din;
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i_ready <= '0';
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stm_mstr <= mstr_wait_first_half;
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elsif ( stop = '1' ) then
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stm_mstr <= mstr_stop;
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elsif ( start = '1' ) then
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stm_mstr <= mstr_restart;
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end if;
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--------------------
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--####################
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--##### WRITE ########
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--####################
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when mstr_wait_first_half =>
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if ( i_scl_cntr < HALF_BIT ) then
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i_scl_mstr <= '0';
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i_scl_cntr <= i_scl_cntr + 1;
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else
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i_scl_cntr <= 0;
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stm_mstr <= mstr_wait_second_half;
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i_sda_mstr <= i_mstr_ad( i_bit_cntr_mstr );
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end if;
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--------------------
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when mstr_wait_second_half =>
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if ( i_scl_cntr < HALF_BIT ) then
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i_scl_cntr <= i_scl_cntr + 1;
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stm_mstr <= mstr_wait_second_half;
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else
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i_scl_cntr <= 0;
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stm_mstr <= mstr_wait_full;
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end if;
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---------------------
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when mstr_wait_full =>
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if ( i_scl_cntr < FULL_BIT ) then
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i_scl_mstr <= '1';
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i_scl_cntr <= i_scl_cntr + 1;
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stm_mstr <= mstr_wait_full;
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else
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i_scl_cntr <= 0;
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if ( i_bit_cntr_mstr >= 1 ) then
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i_bit_cntr_mstr <= i_bit_cntr_mstr - 1;
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stm_mstr <= mstr_wait_first_half;
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elsif ( i_bit_cntr_mstr = 0 ) then
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--i_sda_mstr <= 'Z';
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stm_mstr <= mstr_wait_ack;
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end if;
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end if;
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--------------------
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--####################
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--#### ACKNOWLEDGE ###
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--####################
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when mstr_wait_ack =>
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i_scl_mstr <= '0';
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if ( i_scl_cntr < HALF_BIT ) then
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i_scl_cntr <= i_scl_cntr + 1;
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else
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i_scl_cntr <= 0;
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i_sda_mstr <= 'Z';
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stm_mstr <= mstr_wait_ack_second_half;
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end if;
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--------------------
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when mstr_wait_ack_second_half =>
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if ( i_scl_cntr < HALF_BIT ) then
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i_scl_cntr <= i_scl_cntr + 1;
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else
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i_scl_cntr <= 0;
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i_sda_mstr <= 'Z';
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stm_mstr <= mstr_wait_ack_third_half;
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end if;
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--------------------
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when mstr_wait_ack_third_half =>
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i_scl_mstr <= '1';
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if ( i_scl_cntr < HALF_BIT ) then
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i_scl_cntr <= i_scl_cntr + 1;
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else
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i_scl_cntr <= 0;
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i_sda_mstr <= 'Z';
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i_ack_mstr <= sda;
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stm_mstr <= mstr_wait_ack_fourth_half;
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end if;
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--------------------
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when mstr_wait_ack_fourth_half =>
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if ( i_scl_cntr < HALF_BIT ) then
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i_scl_cntr <= i_scl_cntr + 1;
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else
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i_scl_cntr <= 0;
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i_sda_mstr <= 'Z';
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stm_mstr <= mstr_active;
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end if;
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--------------------
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--####################
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--###### READ ########
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--####################
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when mstr_rd_wait_low =>
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i_scl_mstr <= '0';
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i_sda_mstr <= 'Z';
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if ( i_scl_cntr < FULL_BIT ) then
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i_scl_cntr <= i_scl_cntr + 1;
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stm_mstr <= mstr_rd_wait_low;
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else
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i_scl_cntr <= 0;
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|
|
stm_mstr <= mstr_rd_wait_half;
|
| 307 |
|
|
end if;
|
| 308 |
|
|
--------------------
|
| 309 |
|
|
when mstr_rd_wait_half =>
|
| 310 |
|
|
i_scl_mstr <= '1';
|
| 311 |
|
|
if ( i_scl_cntr < HALF_BIT ) then
|
| 312 |
|
|
i_scl_cntr <= i_scl_cntr + 1;
|
| 313 |
|
|
stm_mstr <= mstr_rd_wait_half;
|
| 314 |
|
|
else
|
| 315 |
|
|
i_scl_cntr <= 0;
|
| 316 |
|
|
i_mstr_rd_data <= i_mstr_rd_data( 6 downto 0 ) & sda;
|
| 317 |
|
|
stm_mstr <= mstr_rd_read;
|
| 318 |
|
|
end if;
|
| 319 |
|
|
---------------------
|
| 320 |
|
|
when mstr_rd_read =>
|
| 321 |
|
|
i_scl_mstr <= '1';
|
| 322 |
|
|
if ( i_scl_cntr < HALF_BIT ) then
|
| 323 |
|
|
i_scl_cntr <= i_scl_cntr + 1;
|
| 324 |
|
|
stm_mstr <= mstr_rd_read;
|
| 325 |
|
|
else
|
| 326 |
|
|
i_scl_cntr <= 0;
|
| 327 |
|
|
if ( i_bit_cntr_mstr > 0 ) then
|
| 328 |
|
|
i_bit_cntr_mstr <= i_bit_cntr_mstr - 1;
|
| 329 |
|
|
i_scl_mstr <= '0';
|
| 330 |
|
|
stm_mstr <= mstr_rd_wait_low;
|
| 331 |
|
|
else
|
| 332 |
|
|
i_mstr_ad <= ( others => '0' );
|
| 333 |
|
|
mstr_dout <= i_mstr_rd_data;
|
| 334 |
|
|
stm_mstr <= mstr_rd_wait_ack;
|
| 335 |
|
|
end if;
|
| 336 |
|
|
end if;
|
| 337 |
|
|
---------------------
|
| 338 |
|
|
--#######################
|
| 339 |
|
|
--### SEND ACKNOWELEDGE #
|
| 340 |
|
|
--#######################
|
| 341 |
|
|
when mstr_rd_wait_ack =>
|
| 342 |
|
|
i_scl_mstr <= '0';
|
| 343 |
|
|
if ( i_scl_cntr < HALF_BIT ) then
|
| 344 |
|
|
i_scl_cntr <= i_scl_cntr + 1;
|
| 345 |
|
|
stm_mstr <= mstr_rd_wait_ack;
|
| 346 |
|
|
else
|
| 347 |
|
|
i_scl_cntr <= 0;
|
| 348 |
|
|
i_sda_mstr <= not send_ack;
|
| 349 |
|
|
stm_mstr <= mstr_rd_get_ack;
|
| 350 |
|
|
end if;
|
| 351 |
|
|
----------------------
|
| 352 |
|
|
when mstr_rd_get_ack =>
|
| 353 |
|
|
i_scl_mstr <= '0';
|
| 354 |
|
|
if ( i_scl_cntr < HALF_BIT ) then
|
| 355 |
|
|
i_scl_cntr <= i_scl_cntr + 1;
|
| 356 |
|
|
stm_mstr <= mstr_rd_get_ack;
|
| 357 |
|
|
else
|
| 358 |
|
|
i_scl_cntr <= 0;
|
| 359 |
|
|
--i_ack_mstr <= sda;
|
| 360 |
|
|
stm_mstr <= mstr_rd_wait_last_half;
|
| 361 |
|
|
end if;
|
| 362 |
|
|
----------------------
|
| 363 |
|
|
when mstr_rd_wait_last_half =>
|
| 364 |
|
|
i_scl_mstr <= '1';
|
| 365 |
|
|
if ( i_scl_cntr < FULL_BIT ) then
|
| 366 |
|
|
i_scl_cntr <= i_scl_cntr + 1;
|
| 367 |
|
|
stm_mstr <= mstr_rd_wait_last_half;
|
| 368 |
|
|
else
|
| 369 |
|
|
i_scl_cntr <= 0;
|
| 370 |
|
|
stm_mstr <= mstr_active;
|
| 371 |
|
|
end if;
|
| 372 |
|
|
----------------------
|
| 373 |
|
|
--######################
|
| 374 |
|
|
--######## STOP ########
|
| 375 |
|
|
--######################
|
| 376 |
|
|
when mstr_stop =>
|
| 377 |
|
|
i_scl_mstr <= '1';
|
| 378 |
|
|
i_sda_mstr <= '0';
|
| 379 |
|
|
if ( i_scl_cntr < HALF_BIT ) then
|
| 380 |
|
|
i_scl_cntr <= i_scl_cntr + 1;
|
| 381 |
|
|
stm_mstr <= mstr_stop;
|
| 382 |
|
|
else
|
| 383 |
|
|
i_scl_cntr <= 0;
|
| 384 |
|
|
i_sda_mstr <= '1';
|
| 385 |
|
|
stm_mstr <= mstr_gap;
|
| 386 |
|
|
end if;
|
| 387 |
|
|
---------------------
|
| 388 |
|
|
when mstr_gap =>
|
| 389 |
|
|
if ( i_scl_cntr < GAP_WIDTH ) then
|
| 390 |
|
|
i_scl_cntr <= i_scl_cntr + 1;
|
| 391 |
|
|
stm_mstr <= mstr_gap;
|
| 392 |
|
|
else
|
| 393 |
|
|
i_scl_cntr <= 0;
|
| 394 |
|
|
stm_mstr <= mstr_idle;
|
| 395 |
|
|
end if;
|
| 396 |
|
|
--#####################
|
| 397 |
|
|
--###### RESTART ######
|
| 398 |
|
|
--#####################
|
| 399 |
|
|
when mstr_restart =>
|
| 400 |
|
|
i_scl_mstr <= '1';
|
| 401 |
|
|
i_sda_mstr <= '0';
|
| 402 |
|
|
if ( i_scl_cntr < HALF_BIT ) then
|
| 403 |
|
|
i_scl_cntr <= i_scl_cntr + 1;
|
| 404 |
|
|
stm_mstr <= mstr_restart;
|
| 405 |
|
|
else
|
| 406 |
|
|
i_scl_cntr <= 0;
|
| 407 |
|
|
i_sda_mstr <= '1';
|
| 408 |
|
|
stm_mstr <= mstr_start_cnt;
|
| 409 |
|
|
end if;
|
| 410 |
|
|
when others => stm_mstr <= mstr_idle;
|
| 411 |
|
|
end case;
|
| 412 |
|
|
end if;
|
| 413 |
|
|
end if;
|
| 414 |
|
|
end process i2c_master;
|
| 415 |
|
|
--##############################################
|
| 416 |
|
|
--##############################################
|
| 417 |
|
|
--##############################################
|
| 418 |
|
|
--##############################################
|
| 419 |
|
|
--##############################################
|
| 420 |
|
|
--##############################################
|
| 421 |
|
|
slv_dout <= i_slv_dout;
|
| 422 |
|
|
i2c_slave:
|
| 423 |
|
|
process( sys_clk , sys_rst )
|
| 424 |
|
|
begin
|
| 425 |
|
|
if ( sys_rst = '1' ) then
|
| 426 |
|
|
stm_slv <= slv_idle;
|
| 427 |
|
|
slv_busy <= '0';
|
| 428 |
|
|
i_slv_bit_cnt <= 0;
|
| 429 |
|
|
i_slv_addr <= ( others => '0' );
|
| 430 |
|
|
i_sda_slv <= 'Z';
|
| 431 |
|
|
i_slv_reg_addr <= ( others => '0' );
|
| 432 |
|
|
i_slv_data <= ( others => '0' );
|
| 433 |
|
|
slv_read <= '0';
|
| 434 |
|
|
slv_write <= '0';
|
| 435 |
|
|
i_slv_dout <= ( others => '0' );
|
| 436 |
|
|
elsif rising_edge( sys_clk ) then
|
| 437 |
|
|
case stm_slv is
|
| 438 |
|
|
----------------------
|
| 439 |
|
|
when slv_idle =>
|
| 440 |
|
|
slv_busy <= '0';
|
| 441 |
|
|
i_sda_slv <= 'Z';
|
| 442 |
|
|
i_slv_bit_cnt <= 0;
|
| 443 |
|
|
if ( i_mstr_slv = '0' ) and ( i_slv_strt_bit = '1' ) then
|
| 444 |
|
|
stm_slv <= slv_get_addr;
|
| 445 |
|
|
slv_busy <= '1';
|
| 446 |
|
|
else
|
| 447 |
|
|
stm_slv <= slv_idle;
|
| 448 |
|
|
end if;
|
| 449 |
|
|
----------------------
|
| 450 |
|
|
when slv_get_addr =>
|
| 451 |
|
|
i_sda_slv <= 'Z';
|
| 452 |
|
|
if ( i_slv_stop_bit = '0' ) then
|
| 453 |
|
|
if ( i_slv_scl_rise = '1' ) then
|
| 454 |
|
|
if ( i_slv_bit_cnt < 8 ) then
|
| 455 |
|
|
i_slv_addr <= i_slv_addr( 6 downto 0 ) & sda;
|
| 456 |
|
|
i_slv_bit_cnt <= i_slv_bit_cnt + 1;
|
| 457 |
|
|
stm_slv <= slv_get_addr;
|
| 458 |
|
|
elsif( i_slv_bit_cnt = 8 ) then
|
| 459 |
|
|
i_slv_addr <= i_slv_addr( 6 downto 0 ) & sda;
|
| 460 |
|
|
i_slv_bit_cnt <= 0;
|
| 461 |
|
|
stm_slv <= slv_send_addr_ack;
|
| 462 |
|
|
end if;
|
| 463 |
|
|
elsif ( i_slv_scl_fall = '1' ) and ( i_slv_bit_cnt = 8 ) then
|
| 464 |
|
|
stm_slv <= slv_send_addr_ack;
|
| 465 |
|
|
i_slv_bit_cnt <= 0;
|
| 466 |
|
|
else
|
| 467 |
|
|
stm_slv <= slv_get_addr;
|
| 468 |
|
|
end if;
|
| 469 |
|
|
else
|
| 470 |
|
|
stm_slv <= slv_idle;
|
| 471 |
|
|
end if;
|
| 472 |
|
|
-----------------------
|
| 473 |
|
|
when slv_send_addr_ack =>
|
| 474 |
|
|
if ( i_slv_addr( 7 downto 1 ) = SLAVE_ADDR ) then
|
| 475 |
|
|
if ( i_slv_scl_rise = '1' ) then
|
| 476 |
|
|
i_sda_slv <= '0';
|
| 477 |
|
|
stm_slv <= slv_wait_ack;
|
| 478 |
|
|
end if;
|
| 479 |
|
|
else
|
| 480 |
|
|
stm_slv <= slv_idle;
|
| 481 |
|
|
end if;
|
| 482 |
|
|
-----------------------
|
| 483 |
|
|
when slv_wait_ack =>
|
| 484 |
|
|
if ( i_slv_scl_fall = '1' ) then
|
| 485 |
|
|
if ( reg_exist = '1' ) then
|
| 486 |
|
|
stm_slv <= slv_read_reg_addr;
|
| 487 |
|
|
elsif ( i_slv_addr( 0 ) = '0' ) then
|
| 488 |
|
|
stm_slv <= slv_write_data;
|
| 489 |
|
|
slv_read <= '1';
|
| 490 |
|
|
elsif ( i_slv_addr( 0 ) = '1' ) then
|
| 491 |
|
|
stm_slv <= slv_read_reg_addr;
|
| 492 |
|
|
end if;
|
| 493 |
|
|
else
|
| 494 |
|
|
stm_slv <= slv_wait_ack;
|
| 495 |
|
|
end if;
|
| 496 |
|
|
-----------------------
|
| 497 |
|
|
when slv_rd_wr =>
|
| 498 |
|
|
i_sda_slv <= 'Z';
|
| 499 |
|
|
i_slv_data <= slv_din;
|
| 500 |
|
|
i_slv_dout <= i_slv_reg_addr;
|
| 501 |
|
|
if ( i_slv_addr( 0 ) = '1' ) then
|
| 502 |
|
|
slv_write <= '1';
|
| 503 |
|
|
stm_slv <= slv_read_data;
|
| 504 |
|
|
else
|
| 505 |
|
|
stm_slv <= slv_write_data;
|
| 506 |
|
|
slv_read <= '1';
|
| 507 |
|
|
end if;
|
| 508 |
|
|
-----------------------
|
| 509 |
|
|
when slv_read_reg_addr =>
|
| 510 |
|
|
slv_write <= '0';
|
| 511 |
|
|
i_sda_slv <= 'Z';
|
| 512 |
|
|
if ( i_slv_stop_bit = '0' ) then
|
| 513 |
|
|
if ( i_slv_scl_rise = '1' ) then
|
| 514 |
|
|
if ( i_slv_bit_cnt < 7 ) then
|
| 515 |
|
|
i_slv_reg_addr <= i_slv_reg_addr( 6 downto 0 ) & sda;
|
| 516 |
|
|
i_slv_bit_cnt <= i_slv_bit_cnt + 1;
|
| 517 |
|
|
stm_slv <= slv_read_reg_addr;
|
| 518 |
|
|
elsif ( i_slv_bit_cnt = 7 ) then
|
| 519 |
|
|
i_slv_reg_addr <= i_slv_reg_addr( 6 downto 0 ) & sda;
|
| 520 |
|
|
i_slv_bit_cnt <= 0;
|
| 521 |
|
|
stm_slv <= slv_send_data_ack;
|
| 522 |
|
|
end if;
|
| 523 |
|
|
else
|
| 524 |
|
|
stm_slv <= slv_read_reg_addr;
|
| 525 |
|
|
end if;
|
| 526 |
|
|
else
|
| 527 |
|
|
stm_slv <= slv_idle;
|
| 528 |
|
|
end if;
|
| 529 |
|
|
-----------------------
|
| 530 |
|
|
when slv_send_data_ack =>
|
| 531 |
|
|
if ( i_slv_scl_rise = '1' ) then
|
| 532 |
|
|
i_sda_slv <= '0';
|
| 533 |
|
|
stm_slv <= slv_wait_data_ack;
|
| 534 |
|
|
end if;
|
| 535 |
|
|
-----------------------
|
| 536 |
|
|
when slv_wait_data_ack =>
|
| 537 |
|
|
if ( i_slv_scl_fall = '1' ) then
|
| 538 |
|
|
stm_slv <= slv_rd_wr;
|
| 539 |
|
|
else
|
| 540 |
|
|
stm_slv <= slv_wait_data_ack;
|
| 541 |
|
|
end if;
|
| 542 |
|
|
-----------------------
|
| 543 |
|
|
when slv_write_data =>
|
| 544 |
|
|
slv_read <= '0';
|
| 545 |
|
|
if ( i_slv_stop_bit = '0' ) then
|
| 546 |
|
|
i_sda_slv <= i_slv_data( 7 );
|
| 547 |
|
|
if ( i_slv_scl_fall = '1' ) then
|
| 548 |
|
|
if ( i_slv_bit_cnt < 7 ) then
|
| 549 |
|
|
-- i_sda_slv <= i_slv_data( 7 );
|
| 550 |
|
|
i_slv_data <= i_slv_data( 6 downto 0 ) & '0';
|
| 551 |
|
|
i_slv_bit_cnt <= i_slv_bit_cnt + 1;
|
| 552 |
|
|
stm_slv <= slv_write_data;
|
| 553 |
|
|
elsif ( i_slv_bit_cnt = 7 ) then
|
| 554 |
|
|
i_sda_slv <= i_slv_data( 7 );
|
| 555 |
|
|
i_slv_bit_cnt <= 0;
|
| 556 |
|
|
stm_slv <= slv_get_wait_data_ack;
|
| 557 |
|
|
end if;
|
| 558 |
|
|
end if;
|
| 559 |
|
|
else
|
| 560 |
|
|
stm_slv <= slv_idle;
|
| 561 |
|
|
end if;
|
| 562 |
|
|
-----------------------
|
| 563 |
|
|
when slv_get_wait_data_ack =>
|
| 564 |
|
|
i_sda_slv <= 'Z';
|
| 565 |
|
|
if ( i_slv_scl_rise = '1' ) then
|
| 566 |
|
|
stm_slv <= slv_get_data_ack;
|
| 567 |
|
|
else
|
| 568 |
|
|
stm_slv <= slv_get_wait_data_ack;
|
| 569 |
|
|
end if;
|
| 570 |
|
|
-----------------------
|
| 571 |
|
|
when slv_get_data_ack =>
|
| 572 |
|
|
i_sda_slv <= 'Z';
|
| 573 |
|
|
if ( i_slv_scl_fall = '1' ) then
|
| 574 |
|
|
if ( sda = '0' ) and ( i_slv_sda_fall = '0' ) then
|
| 575 |
|
|
stm_slv <= slv_rd_wr;
|
| 576 |
|
|
else
|
| 577 |
|
|
stm_slv <= slv_idle;
|
| 578 |
|
|
end if;
|
| 579 |
|
|
else
|
| 580 |
|
|
stm_slv <= slv_get_data_ack;
|
| 581 |
|
|
end if;
|
| 582 |
|
|
------------------------
|
| 583 |
|
|
when slv_read_data =>
|
| 584 |
|
|
slv_write <= '0';
|
| 585 |
|
|
if ( i_slv_stop_bit = '1' ) then
|
| 586 |
|
|
stm_slv <= slv_idle;
|
| 587 |
|
|
else
|
| 588 |
|
|
if ( i_slv_scl_rise = '1' ) then
|
| 589 |
|
|
if ( i_slv_bit_cnt < 7 ) then
|
| 590 |
|
|
i_slv_reg_addr <= i_slv_reg_addr( 6 downto 0 ) & sda;
|
| 591 |
|
|
i_slv_bit_cnt <= i_slv_bit_cnt + 1;
|
| 592 |
|
|
stm_slv <= slv_read_data;
|
| 593 |
|
|
elsif ( i_slv_bit_cnt = 7 ) then
|
| 594 |
|
|
i_slv_reg_addr <= i_slv_reg_addr( 6 downto 0 ) & sda;
|
| 595 |
|
|
i_slv_bit_cnt <= 0;
|
| 596 |
|
|
stm_slv <= slv_send_data_ack;
|
| 597 |
|
|
end if;
|
| 598 |
|
|
else
|
| 599 |
|
|
stm_slv <= slv_read_data;
|
| 600 |
|
|
end if;
|
| 601 |
|
|
end if;
|
| 602 |
|
|
-------------------------
|
| 603 |
|
|
when others => stm_slv <= slv_idle;
|
| 604 |
|
|
end case;
|
| 605 |
|
|
end if;
|
| 606 |
|
|
end process i2c_slave;
|
| 607 |
|
|
END ARCHITECTURE arc;
|
| 608 |
|
|
|
