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[/] [i2clog/] [web_uploads/] [I2C_TrafficLogger.v] - Blame information for rev 6

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//This Verilog code datalog I2C bus traffic and writes into an external
//RAM in 8 bit byte format. It supports the 5 Atmel I2C read/write
//protocals:  (1) One byte read-  S:DEV:ADD:R:A:DATA:A:P
//            (2) One byte write- S:DEV:ADD:W:A:DATA:A:P
//            (3) Page write -    S:DEV:ADD:W:A:DATA1:A:DATA2:A ...P
//            (4) Page read-      S:DEV:ADD:R:A:DATA1:A:DATA2:A ...P
//            (5) Random read-    S:DEV:W:A:ADD:A:S:DEV:R:A:DATA:A:...P
//
//Algorithm-
//The design consist of a start and stop bit detector, a serial to
//parallel shift register, a read write control. Serial to parallel
//conversion begin when the start bit is detected, upon which all
//necessary data are initialized. 
//into an external RAM in a 9 bit wide format. The 9th bit is output as
//This I2C traffic logger works best with Clk 5 to 10MHz. The I2C
//clock speed from 30KHz to 180KHz
`timescale 10ns/100ps
module          I2CLog(Clk,SDA,SCL,Rst,Ce,Oe,We,ACK,Dout,Current_addr);
input           Clk,Rst,SDA,SCL;
output          Ce,Oe,We,ACK;
output[7:0]     Dout;
output[14:0]    Current_addr;
wire            Start,Stop,SDA,SCL,RW,ACK,Clk,Rst,ByteRdy;
wire[8:0]        Byte;
I2C             ModStSp(Clk,SCL,SDA,Start,Stop,Rst);
Serial2Byte     ModSerial2Byte(SCL,SDA,RW,Start,Rst,Byte,ACK,ByteRdy);
ByteWr2Ram      ModByteWr(Clk,SCL,Rst,ByteRdy,Oe,We,Ce,Byte,Dout,ACK,Current_addr);
RWCtrl          ModRW(Clk,Start,Stop,Rst,RW);
endmodule
 
//StartStop verilog code generates a start pulse on posedge of
//I2C start bit, and a stop pulse on the posedge of I2C stop bit. 
//The pulse width is about 2 clock cycles and varies slightly
//due to asynchronous timing of start and stop bits
//This design is verified on I2C bus such as Atmel eproms
//to detect start and stop bit up to 200KHz bus rate
//The propagation delays from the edge of the I2C start and
//stop bits to the leading edge of the Start/Stop pulse is ~10nS
//Note implementation on C4000 Xilinx have to choose the global
//clocks for the SDA and SCL pins. Only P13,P35,P10,P72,P78 work
//in the XS40 board. Typical implementation: SCL=P10,SDA=P35,Start=P27
//Stop=P28,ResetPON=P44(from Xport control)
module StartTrigger(SCL,SDA,Start,Reset);
        input SCL,SDA,Reset;
        output Start;
        wire   Din;
        wire   SCL;
        DlatchNeg   StLatch(Reset,SDA,SCL,Start);
endmodule
module StopTrigger(SCL,SDA,Start,Reset);
        input SCL,SDA,Reset;
        output Start;
        wire   Din;
        wire   SCL;
        DlatchPos   SpLatch(Reset,SDA,SCL,Start);
endmodule
module DlatchNeg(Reset,Clk,Din,Q);
        input Reset,Clk,Din;
        output   Q;
        reg Q;
        always @(negedge Clk or posedge Reset)
                if (Reset)
                        Q=1'b0;
                else
                        Q=Din;
endmodule
module DlatchPos(Reset,Clk,Din,Q);
        input Reset,Clk,Din;
        output   Q;
        reg Q;
        always @(posedge Clk or posedge Reset)
                if (Reset)
                        Q=1'b0;
                else
                        Q=Din;
endmodule
module I2CStart(Clk,SCL,SDA,Start,ResetPON);
        input   Clk,SCL,SDA,ResetPON;
        output  Start;
        reg     [1:0]    StState_reg,StNext_state;
        wire    Clk,Start,Reset,SCL,SDA;
        reg     RstStart,ResetPON;
 
parameter       StReset_state   = 2'b00;
parameter       PulseStart_state  = 2'b01;
parameter       PulseOff_state  = 2'b10;
assign          Reset= (RstStart || ResetPON);
StartTrigger   ModStart(SCL,SDA,Start,Reset);
always @(posedge ResetPON or posedge Clk)
        if (ResetPON == 1)
        begin
                StState_reg <= StReset_state;
                end
           else
           begin
                StState_reg <= StNext_state;
          end
always @(StState_reg or Clk)
                case (StState_reg)
                        StReset_state:
                        if (Start == 1)
                                begin
                                        StNext_state <=PulseStart_state;
                                        RstStart=0;
                                end
                        else
                                begin
                                        RstStart=0;
                                        StNext_state <= StReset_state;
                                 end
                        PulseStart_state:
                        begin
                                RstStart=0;
                                StNext_state <= PulseOff_state;
                        end
                        PulseOff_state:
                         begin
                                RstStart=1;
                                StNext_state <= StReset_state;
                                end
                        default: StNext_state <= StReset_state;
                        endcase
 
endmodule
module I2CStop(Clk,SCL,SDA,Stop,ResetPON);
        input   Clk,SCL,SDA,ResetPON;
        output  Stop;
        reg     [1:0]    SpState_reg,SpNext_state;
        wire    Clk,Stop,Reset,SCL,SDA;
        reg     RstStop,ResetPON;
 
parameter       SpReset_state   = 2'b00;
parameter       PulseStop_state  = 2'b01;
parameter       PulseOffStop_state  = 2'b10;
assign          Reset= (RstStop || ResetPON);
StopTrigger   ModStop(SCL,SDA,Stop,Reset);
always @(posedge ResetPON or posedge Clk)
        if (ResetPON == 1)
        begin
                SpState_reg <= SpReset_state;
                end
           else
           begin
                SpState_reg <= SpNext_state;
          end
always @(SpState_reg or Clk)
                case (SpState_reg)
                        SpReset_state:
                        if (Stop == 1)
                                begin
                                        SpNext_state <=PulseStop_state;
                                        RstStop=0;
                                end
                        else
                                begin
                                        RstStop=0;
                                        SpNext_state <= SpReset_state;
                                 end
                        PulseStop_state:
                        begin
                                RstStop=0;
                                SpNext_state <= PulseOffStop_state;
                        end
                        PulseOffStop_state:
                         begin
                                RstStop=1;
                                SpNext_state <= SpReset_state;
                                end
                        default: SpNext_state <= SpReset_state;
                        endcase
 
endmodule
module I2C(Clk,SCL,SDA,Start,Stop,ResetPON);
        input   Clk,SCL,SDA,ResetPON;
        output  Start,Stop;
        reg     SCL,SDA,ResetPON;
        wire    Clk;
I2CStop   mod1(Clk,SCL,SDA,Stop,ResetPON);
I2CStart  mod2(Clk,SCL,SDA,Start,ResetPON);
endmodule
 
//Serial to parallel conversion module. 
//This module converts the serial SDA bits into a 9 bit
//byte format with the 9th bit as ACK. Conversion commences
//and ends with asserting and de-asserting the input Start
//signal. The Start behaves like a reset where the output byte is
//initialized to 0, and bit count is set to 0, and handshake ByteRdy
//is reseted to 0. ByteRdy is asserted every 9th cycle
 
module         Serial2Byte (SCL,SDA,RW,Start,Reset,Byte,ACK,ByteRdy);
input          SCL,SDA,RW,Start,Reset;
output[8:0]    Byte;
output         ACK,ByteRdy;
reg[8:0]       Byte;
reg            ByteRdy;
wire           RWInv,RstSerial;
reg[3:0]       COUNT;
reg[1:0]       state_reg,next_state;
parameter      reset_state='b00;
parameter      start_state='b01;
parameter      stop_state ='b10;
assign         RWInv=~RW;
assign         RstSerial=Reset||Start;
always @(posedge SCL or posedge RstSerial or posedge RWInv)
        begin
                if (RstSerial)
                        begin
                                COUNT = 4'b0;
                                ByteRdy =0;
                                Byte = 9'b0;
                        end
                else if (RWInv)
                         begin
                                COUNT=4'b0;
                                ByteRdy =0;
                                Byte=9'b0;
                         end
                         else
                        begin
                                Byte = {Byte[7:0],SDA};
                                COUNT = COUNT + 1;
                                if (COUNT==9)
                                        begin
                                                ByteRdy =1;
                                                COUNT =0;
                                        end
                                        else
                                                ByteRdy=0;
                        end
        end
endmodule
 
//Write to Ram
//A repeated read2 and write2 is added to give longer valid write time                          
module          ByteWr2Ram(Clk,SCL,Rst,ByteRdy,Oe,We,Ce,Din,Dout,ACK,Current_addr);
input           Clk,SCL,Rst,ByteRdy;
input[8:0]      Din;
output[7:0]     Dout;
output[14:0]    Current_addr;
output          Oe,Ce,We,ACK;
reg             Oe,Ce,We;
reg             RstByteRdy,ByteRdyOut,ACK;
wire            Din1,Rst;
reg[7:0]        Dout;
reg[14:0]        Current_addr,Next_addr;
reg[7:0]         Current_data,Next_data;
reg[2:0] state_reg,next_state;
assign          Din1='b1;
parameter       reset_state   = 3'b000;
parameter       load_state    = 3'b001;
parameter       write1_state   = 3'b010;
parameter       write2_state   = 3'b011;
parameter       read1_state    = 3'b100;
parameter       read2_state    = 3'b101;
DFF             Mod1(ByteRdy,RstByteRdy,Din1,ByteRdyOut);
        always @(posedge Clk or posedge Rst)
           if (Rst)
                        state_reg = reset_state;
                 else
                        state_reg = next_state;
        always @(posedge Clk)
                case (state_reg)
                        reset_state:
                        begin
                           if (Rst)
                           begin
                                next_state =reset_state;
                                Next_addr  ='h0000;
                                Current_addr ='h0000;
                                Dout       ='b00000000;
                                Oe         =1;
                                We         =1;
                                Ce         =1;
                                RstByteRdy =1;
                                end
                            else
                                begin
                                next_state =load_state;
                                RstByteRdy =0;
                                end
                        end
 
                        load_state:
 
                        if (ByteRdyOut)
                              begin
                                Oe =1;
                                We =1;
                                Ce =0;
                                Current_addr =Next_addr;
                                next_state  = write1_state;
                                Dout[7:0] =Din[8:1];
                                ACK = Din[0];
                                RstByteRdy =0;
                                end
                                else
                                begin
                                next_state =load_state;
                                Current_addr =Next_addr;
                                end
                        write1_state:
                        begin
                                We =0;
                                Oe =1;
                                Ce =0;
                                next_state = write2_state;
                                RstByteRdy =1;
                                end
                        write2_state:
                        begin
                                We=0;
                                Oe=1;
                                Ce=0;
                                RstByteRdy =0;
                                next_state = read1_state;
                        end
 
                        read1_state:
                                begin
                                        We =1;
                                        Oe =1;
                                        Ce =0;
                                        RstByteRdy=0;
                                        next_state = read2_state;
                                end
                        read2_state:
                                begin
                                        We=1;
                                        Oe=1;
                                        Ce=0;
                                        next_state = load_state;
                                        Next_addr =Current_addr+1;
 
                                end
                        default         next_state = load_state;
 
                endcase
        endmodule
 
module DFF(CLK,RESET,DIN,DOUT);
          input CLK,RESET,DIN;
          output DOUT;
          reg DOUT;
        always @(posedge CLK or posedge RESET)
                begin
                        if (RESET)
                                DOUT = 1'b0;
                        else
                                DOUT = DIN;
                end
endmodule
//This code generates an one short trigger pulse
//when arm=1 at trigger in
//A 3 state machine clocked bythe fast Clk to ensure
//RW signal responds to Start and Stop signal with little delay
//The state machine toggles between start and stop signal to 
//generate the RW output for RAM write.
module    RWCtrl (Clk,Start,Stop,Reset,RW);
input       Clk,Start,Stop,Reset;
output      RW;
wire        Clk;
reg         RW;
reg     [2:0]    state_reg,next_state;
parameter       start_state   = 2'b00;
parameter       arming_state  = 2'b01;
parameter       stop_state    = 2'b10;
always @(posedge Clk or posedge Reset)
        if (Reset) state_reg <= start_state;
           else state_reg <= next_state;
always @(state_reg or Start or Stop)
                case (state_reg)
                        start_state:
                        if (Start == 1)
                                begin
                                        next_state <= arming_state;
                                        RW =1;
                                end
                        else
                                begin
                                        RW =0;
                                        next_state <= start_state;
                                end
                        arming_state:
                      if (Stop==1)
                      begin
                                RW=0;
                                next_state <= start_state;
                                end
                         else
                                  begin
                                        RW=1;
                                        next_state <= arming_state;
                                  end
 
                        default: next_state <= start_state;
                endcase
endmodule

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Subversion Repositories i2clog

[/] [i2clog/] [web_uploads/] [I2C_TrafficLogger.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	6	root	`//This Verilog code datalog I2C bus traffic and writes into an external`
2			`//RAM in 8 bit byte format. It supports the 5 Atmel I2C read/write`
3			`//protocals: (1) One byte read- S:DEV:ADD:R:A:DATA:A:P`
4			`// (2) One byte write- S:DEV:ADD:W:A:DATA:A:P`
5			`// (3) Page write - S:DEV:ADD:W:A:DATA1:A:DATA2:A ...P`
6			`// (4) Page read- S:DEV:ADD:R:A:DATA1:A:DATA2:A ...P`
7			`// (5) Random read- S:DEV:W:A:ADD:A:S:DEV:R:A:DATA:A:...P`
8			`//`
9			`//Algorithm-`
10			`//The design consist of a start and stop bit detector, a serial to`
11			`//parallel shift register, a read write control. Serial to parallel`
12			`//conversion begin when the start bit is detected, upon which all`
13			`//necessary data are initialized.`
14			`//into an external RAM in a 9 bit wide format. The 9th bit is output as`
15			`//This I2C traffic logger works best with Clk 5 to 10MHz. The I2C`
16			`//clock speed from 30KHz to 180KHz`
17			`timescale 10ns/100ps
18			`module I2CLog(Clk,SDA,SCL,Rst,Ce,Oe,We,ACK,Dout,Current_addr);`
19			`input Clk,Rst,SDA,SCL;`
20			`output Ce,Oe,We,ACK;`
21			`output[7:0] Dout;`
22			`output[14:0] Current_addr;`
23			`wire Start,Stop,SDA,SCL,RW,ACK,Clk,Rst,ByteRdy;`
24			`wire[8:0] Byte;`
25			`I2C ModStSp(Clk,SCL,SDA,Start,Stop,Rst);`
26			`Serial2Byte ModSerial2Byte(SCL,SDA,RW,Start,Rst,Byte,ACK,ByteRdy);`
27			`ByteWr2Ram ModByteWr(Clk,SCL,Rst,ByteRdy,Oe,We,Ce,Byte,Dout,ACK,Current_addr);`
28			`RWCtrl ModRW(Clk,Start,Stop,Rst,RW);`
29			`endmodule`
30
31			`//StartStop verilog code generates a start pulse on posedge of`
32			`//I2C start bit, and a stop pulse on the posedge of I2C stop bit.`
33			`//The pulse width is about 2 clock cycles and varies slightly`
34			`//due to asynchronous timing of start and stop bits`
35			`//This design is verified on I2C bus such as Atmel eproms`
36			`//to detect start and stop bit up to 200KHz bus rate`
37			`//The propagation delays from the edge of the I2C start and`
38			`//stop bits to the leading edge of the Start/Stop pulse is ~10nS`
39			`//Note implementation on C4000 Xilinx have to choose the global`
40			`//clocks for the SDA and SCL pins. Only P13,P35,P10,P72,P78 work`
41			`//in the XS40 board. Typical implementation: SCL=P10,SDA=P35,Start=P27`
42			`//Stop=P28,ResetPON=P44(from Xport control)`
43			`module StartTrigger(SCL,SDA,Start,Reset);`
44			`input SCL,SDA,Reset;`
45			`output Start;`
46			`wire Din;`
47			`wire SCL;`
48			`DlatchNeg StLatch(Reset,SDA,SCL,Start);`
49			`endmodule`
50			`module StopTrigger(SCL,SDA,Start,Reset);`
51			`input SCL,SDA,Reset;`
52			`output Start;`
53			`wire Din;`
54			`wire SCL;`
55			`DlatchPos SpLatch(Reset,SDA,SCL,Start);`
56			`endmodule`
57			`module DlatchNeg(Reset,Clk,Din,Q);`
58			`input Reset,Clk,Din;`
59			`output Q;`
60			`reg Q;`
61			`always @(negedge Clk or posedge Reset)`
62			`if (Reset)`
63			`Q=1'b0;`
64			`else`
65			`Q=Din;`
66			`endmodule`
67			`module DlatchPos(Reset,Clk,Din,Q);`
68			`input Reset,Clk,Din;`
69			`output Q;`
70			`reg Q;`
71			`always @(posedge Clk or posedge Reset)`
72			`if (Reset)`
73			`Q=1'b0;`
74			`else`
75			`Q=Din;`
76			`endmodule`
77			`module I2CStart(Clk,SCL,SDA,Start,ResetPON);`
78			`input Clk,SCL,SDA,ResetPON;`
79			`output Start;`
80			`reg [1:0] StState_reg,StNext_state;`
81			`wire Clk,Start,Reset,SCL,SDA;`
82			`reg RstStart,ResetPON;`
83
84			`parameter StReset_state = 2'b00;`
85			`parameter PulseStart_state = 2'b01;`
86			`parameter PulseOff_state = 2'b10;`
87			`assign Reset= (RstStart \|\| ResetPON);`
88			`StartTrigger ModStart(SCL,SDA,Start,Reset);`
89			`always @(posedge ResetPON or posedge Clk)`
90			`if (ResetPON == 1)`
91			`begin`
92			`StState_reg <= StReset_state;`
93			`end`
94			`else`
95			`begin`
96			`StState_reg <= StNext_state;`
97			`end`
98			`always @(StState_reg or Clk)`
99			`case (StState_reg)`
100			`StReset_state:`
101			`if (Start == 1)`
102			`begin`
103			`StNext_state <=PulseStart_state;`
104			`RstStart=0;`
105			`end`
106			`else`
107			`begin`
108			`RstStart=0;`
109			`StNext_state <= StReset_state;`
110			`end`
111			`PulseStart_state:`
112			`begin`
113			`RstStart=0;`
114			`StNext_state <= PulseOff_state;`
115			`end`
116			`PulseOff_state:`
117			`begin`
118			`RstStart=1;`
119			`StNext_state <= StReset_state;`
120			`end`
121			`default: StNext_state <= StReset_state;`
122			`endcase`
123
124			`endmodule`
125			`module I2CStop(Clk,SCL,SDA,Stop,ResetPON);`
126			`input Clk,SCL,SDA,ResetPON;`
127			`output Stop;`
128			`reg [1:0] SpState_reg,SpNext_state;`
129			`wire Clk,Stop,Reset,SCL,SDA;`
130			`reg RstStop,ResetPON;`
131
132			`parameter SpReset_state = 2'b00;`
133			`parameter PulseStop_state = 2'b01;`
134			`parameter PulseOffStop_state = 2'b10;`
135			`assign Reset= (RstStop \|\| ResetPON);`
136			`StopTrigger ModStop(SCL,SDA,Stop,Reset);`
137			`always @(posedge ResetPON or posedge Clk)`
138			`if (ResetPON == 1)`
139			`begin`
140			`SpState_reg <= SpReset_state;`
141			`end`
142			`else`
143			`begin`
144			`SpState_reg <= SpNext_state;`
145			`end`
146			`always @(SpState_reg or Clk)`
147			`case (SpState_reg)`
148			`SpReset_state:`
149			`if (Stop == 1)`
150			`begin`
151			`SpNext_state <=PulseStop_state;`
152			`RstStop=0;`
153			`end`
154			`else`
155			`begin`
156			`RstStop=0;`
157			`SpNext_state <= SpReset_state;`
158			`end`
159			`PulseStop_state:`
160			`begin`
161			`RstStop=0;`
162			`SpNext_state <= PulseOffStop_state;`
163			`end`
164			`PulseOffStop_state:`
165			`begin`
166			`RstStop=1;`
167			`SpNext_state <= SpReset_state;`
168			`end`
169			`default: SpNext_state <= SpReset_state;`
170			`endcase`
171
172			`endmodule`
173			`module I2C(Clk,SCL,SDA,Start,Stop,ResetPON);`
174			`input Clk,SCL,SDA,ResetPON;`
175			`output Start,Stop;`
176			`reg SCL,SDA,ResetPON;`
177			`wire Clk;`
178			`I2CStop mod1(Clk,SCL,SDA,Stop,ResetPON);`
179			`I2CStart mod2(Clk,SCL,SDA,Start,ResetPON);`
180			`endmodule`
181
182			`//Serial to parallel conversion module.`
183			`//This module converts the serial SDA bits into a 9 bit`
184			`//byte format with the 9th bit as ACK. Conversion commences`
185			`//and ends with asserting and de-asserting the input Start`
186			`//signal. The Start behaves like a reset where the output byte is`
187			`//initialized to 0, and bit count is set to 0, and handshake ByteRdy`
188			`//is reseted to 0. ByteRdy is asserted every 9th cycle`
189
190			`module Serial2Byte (SCL,SDA,RW,Start,Reset,Byte,ACK,ByteRdy);`
191			`input SCL,SDA,RW,Start,Reset;`
192			`output[8:0] Byte;`
193			`output ACK,ByteRdy;`
194			`reg[8:0] Byte;`
195			`reg ByteRdy;`
196			`wire RWInv,RstSerial;`
197			`reg[3:0] COUNT;`
198			`reg[1:0] state_reg,next_state;`
199			`parameter reset_state='b00;`
200			`parameter start_state='b01;`
201			`parameter stop_state ='b10;`
202			`assign RWInv=~RW;`
203			`assign RstSerial=Reset\|\|Start;`
204			`always @(posedge SCL or posedge RstSerial or posedge RWInv)`
205			`begin`
206			`if (RstSerial)`
207			`begin`
208			`COUNT = 4'b0;`
209			`ByteRdy =0;`
210			`Byte = 9'b0;`
211			`end`
212			`else if (RWInv)`
213			`begin`
214			`COUNT=4'b0;`
215			`ByteRdy =0;`
216			`Byte=9'b0;`
217			`end`
218			`else`
219			`begin`
220			`Byte = {Byte[7:0],SDA};`
221			`COUNT = COUNT + 1;`
222			`if (COUNT==9)`
223			`begin`
224			`ByteRdy =1;`
225			`COUNT =0;`
226			`end`
227			`else`
228			`ByteRdy=0;`
229			`end`
230			`end`
231			`endmodule`
232
233			`//Write to Ram`
234			`//A repeated read2 and write2 is added to give longer valid write time`
235			`module ByteWr2Ram(Clk,SCL,Rst,ByteRdy,Oe,We,Ce,Din,Dout,ACK,Current_addr);`
236			`input Clk,SCL,Rst,ByteRdy;`
237			`input[8:0] Din;`
238			`output[7:0] Dout;`
239			`output[14:0] Current_addr;`
240			`output Oe,Ce,We,ACK;`
241			`reg Oe,Ce,We;`
242			`reg RstByteRdy,ByteRdyOut,ACK;`
243			`wire Din1,Rst;`
244			`reg[7:0] Dout;`
245			`reg[14:0] Current_addr,Next_addr;`
246			`reg[7:0] Current_data,Next_data;`
247			`reg[2:0] state_reg,next_state;`
248			`assign Din1='b1;`
249			`parameter reset_state = 3'b000;`
250			`parameter load_state = 3'b001;`
251			`parameter write1_state = 3'b010;`
252			`parameter write2_state = 3'b011;`
253			`parameter read1_state = 3'b100;`
254			`parameter read2_state = 3'b101;`
255			`DFF Mod1(ByteRdy,RstByteRdy,Din1,ByteRdyOut);`
256			`always @(posedge Clk or posedge Rst)`
257			`if (Rst)`
258			`state_reg = reset_state;`
259			`else`
260			`state_reg = next_state;`
261			`always @(posedge Clk)`
262			`case (state_reg)`
263			`reset_state:`
264			`begin`
265			`if (Rst)`
266			`begin`
267			`next_state =reset_state;`
268			`Next_addr ='h0000;`
269			`Current_addr ='h0000;`
270			`Dout ='b00000000;`
271			`Oe =1;`
272			`We =1;`
273			`Ce =1;`
274			`RstByteRdy =1;`
275			`end`
276			`else`
277			`begin`
278			`next_state =load_state;`
279			`RstByteRdy =0;`
280			`end`
281			`end`
282
283			`load_state:`
284
285			`if (ByteRdyOut)`
286			`begin`
287			`Oe =1;`
288			`We =1;`
289			`Ce =0;`
290			`Current_addr =Next_addr;`
291			`next_state = write1_state;`
292			`Dout[7:0] =Din[8:1];`
293			`ACK = Din[0];`
294			`RstByteRdy =0;`
295			`end`
296			`else`
297			`begin`
298			`next_state =load_state;`
299			`Current_addr =Next_addr;`
300			`end`
301			`write1_state:`
302			`begin`
303			`We =0;`
304			`Oe =1;`
305			`Ce =0;`
306			`next_state = write2_state;`
307			`RstByteRdy =1;`
308			`end`
309			`write2_state:`
310			`begin`
311			`We=0;`
312			`Oe=1;`
313			`Ce=0;`
314			`RstByteRdy =0;`
315			`next_state = read1_state;`
316			`end`
317
318			`read1_state:`
319			`begin`
320			`We =1;`
321			`Oe =1;`
322			`Ce =0;`
323			`RstByteRdy=0;`
324			`next_state = read2_state;`
325			`end`
326			`read2_state:`
327			`begin`
328			`We=1;`
329			`Oe=1;`
330			`Ce=0;`
331			`next_state = load_state;`
332			`Next_addr =Current_addr+1;`
333
334			`end`
335			`default next_state = load_state;`
336
337			`endcase`
338			`endmodule`
339
340			`module DFF(CLK,RESET,DIN,DOUT);`
341			`input CLK,RESET,DIN;`
342			`output DOUT;`
343			`reg DOUT;`
344			`always @(posedge CLK or posedge RESET)`
345			`begin`
346			`if (RESET)`
347			`DOUT = 1'b0;`
348			`else`
349			`DOUT = DIN;`
350			`end`
351			`endmodule`
352			`//This code generates an one short trigger pulse`
353			`//when arm=1 at trigger in`
354			`//A 3 state machine clocked bythe fast Clk to ensure`
355			`//RW signal responds to Start and Stop signal with little delay`
356			`//The state machine toggles between start and stop signal to`
357			`//generate the RW output for RAM write.`
358			`module RWCtrl (Clk,Start,Stop,Reset,RW);`
359			`input Clk,Start,Stop,Reset;`
360			`output RW;`
361			`wire Clk;`
362			`reg RW;`
363			`reg [2:0] state_reg,next_state;`
364			`parameter start_state = 2'b00;`
365			`parameter arming_state = 2'b01;`
366			`parameter stop_state = 2'b10;`
367			`always @(posedge Clk or posedge Reset)`
368			`if (Reset) state_reg <= start_state;`
369			`else state_reg <= next_state;`
370			`always @(state_reg or Start or Stop)`
371			`case (state_reg)`
372			`start_state:`
373			`if (Start == 1)`
374			`begin`
375			`next_state <= arming_state;`
376			`RW =1;`
377			`end`
378			`else`
379			`begin`
380			`RW =0;`
381			`next_state <= start_state;`
382			`end`
383			`arming_state:`
384			`if (Stop==1)`
385			`begin`
386			`RW=0;`
387			`next_state <= start_state;`
388			`end`
389			`else`
390			`begin`
391			`RW=1;`
392			`next_state <= arming_state;`
393			`end`
394
395			`default: next_state <= start_state;`
396			`endcase`
397			`endmodule`